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8436
8437
8438
8439
8440
8441
8442
8443
8444
8445
8446
8447
8448
8449
8450
8451
8452
8453
8454
8455
8456
8457
8458
8459
8460
8461
8462
8463
8464
8465
8466
8467
8468
8469
8470
8471
8472
8473
8474
8475
8476
8477
8478
8479
8480
8481
8482
8483
8484
8485
8486
8487
8488
8489
8490
8491
8492
8493
8494
8495
8496
8497
8498
8499
8500
8501
8502
8503
8504
8505
8506
8507
8508
8509
8510
8511
8512
8513
8514
8515
8516
8517
8518
8519
8520
8521
8522
8523
8524
8525
8526
8527
8528
8529
8530
8531
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8533
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8536
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8538
8539
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8541
8542
8543
8544
8545
8546
8547
8548
8549
8550
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8552
8553
8554
8555
8556
8557
8558
8559
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8563
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8566
8567
8568
8569
8570
8571
8572
8573
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8575
8576
8577
8578
8579
8580
8581
8582
8583
8584
8585
8586
8587
8588
8589
8590
8591
8592
8593
8594
8595
8596
8597
8598
8599
8600
8601
8602
8603
8604
8605
8606
8607
8608
8609
8610
8611
8612
8613
8614
8615
8616
8617
8618
8619
8620
8621
8622
8623
8624
8625
8626
8627
8628
8629
8630
8631
8632
8633
8634
8635
8636
8637
8638
8639
8640
8641
8642
8643
8644
8645
8646
8647
8648
8649
8650
8651
8652
8653
8654
8655
8656
8657
8658
8659
8660
8661
8662
8663
8664
8665
8666
8667
8668
8669
8670
8671
8672
8673
8674
8675
8676
8677
8678
8679
8680
8681
8682
8683
8684
8685
8686
8687
8688
8689
8690
8691
8692
8693
8694
8695
8696
8697
8698
8699
8700
8701
8702
8703
8704
8705
8706
8707
8708
8709
8710
8711
8712
8713
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8715
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8717
8718
8719
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8721
8722
8723
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8725
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8732
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8739
8740
8741
8742
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8744
8745
8746
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8748
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8751
8752
8753
8754
8755
8756
8757
8758
8759
8760
8761
8762
8763
8764
8765
8766
8767
8768
8769
8770
8771
8772
8773
8774
8775
8776
8777
8778
8779
8780
8781
8782
8783
8784
8785
8786
8787
8788
8789
8790
8791
8792
8793
8794
8795
8796
8797
8798
8799
8800
8801
8802
8803
8804
8805
8806
8807
8808
8809
8810
8811
8812
8813
8814
8815
8816
8817
8818
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8822
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8859
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8895
8896
8897
8898
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8900
8901
8902
8903
8904
8905
8906
8907
8908
8909
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8911
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8914
8915
8916
8917
8918
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8920
8921
8922
8923
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8927
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8929
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8938
8939
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8941
8942
8943
8944
8945
8946
8947
8948
8949
8950
8951
8952
8953
8954
8955
8956
8957
8958
8959
8960
8961
8962
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8964
8965
8966
8967
8968
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8970
8971
8972
8973
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8984
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8988
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8990
8991
8992
8993
8994
8995
8996
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9000
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9041
9042
9043
9044
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9046
9047
9048
9049
9050
9051
9052
9053
9054
9055
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9057
9058
9059
9060
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9100
9101
9102
9103
9104
9105
9106
9107
9108
9109
9110
9111
9112
9113
9114
9115
9116
9117
9118
9119
9120
9121
9122
9123
9124
9125
9126
9127
9128
9129
9130
9131
9132
9133
9134
9135
9136
9137
9138
9139
9140
9141
9142
9143
9144
9145
9146
9147
9148
9149
9150
9151
9152
9153
9154
9155
9156
9157
9158
9159
9160
9161
9162
9163
9164
9165
9166
9167
9168
9169
9170
9171
9172
9173
9174
9175
9176
9177
9178
9179
9180
9181
9182
9183
9184
9185
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9187
9188
9189
9190
9191
9192
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9194
9195
9196
9197
9198
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9200
9201
9202
9203
9204
9205
9206
9207
9208
9209
9210
9211
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9214
9215
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9217
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9220
9221
9222
9223
9224
9225
9226
9227
9228
9229
9230
9231
9232
9233
9234
9235
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9237
9238
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9240
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9260
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9264
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9280
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9297
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9299
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9310
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9321
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9328
9329
9330
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9334
9335
9336
9337
9338
9339
9340
9341
9342
9343
9344
9345
9346
9347
9348
9349
9350
9351
9352
9353
9354
9355
9356
9357
9358
9359
9360
9361
9362
9363
9364
9365
9366
9367
9368
9369
9370
9371
9372
9373
9374
9375
9376
9377
9378
9379
9380
9381
9382
9383
9384
9385
9386
9387
9388
9389
9390
9391
9392
9393
9394
9395
9396
9397
9398
9399
9400
9401
9402
9403
9404
9405
9406
9407
9408
9409
9410
9411
9412
9413
9414
9415
9416
9417
9418
9419
9420
9421
9422
9423
9424
9425
9426
9427
9428
9429
9430
9431
9432
9433
9434
9435
9436
9437
9438
9439
9440
9441
9442
9443
9444
9445
9446
9447
9448
|
package armasm
const (
_ Op = iota
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
ADC_EQ
ADC_NE
ADC_CS
ADC_CC
ADC_MI
ADC_PL
ADC_VS
ADC_VC
ADC_HI
ADC_LS
ADC_GE
ADC_LT
ADC_GT
ADC_LE
ADC
ADC_ZZ
ADC_S_EQ
ADC_S_NE
ADC_S_CS
ADC_S_CC
ADC_S_MI
ADC_S_PL
ADC_S_VS
ADC_S_VC
ADC_S_HI
ADC_S_LS
ADC_S_GE
ADC_S_LT
ADC_S_GT
ADC_S_LE
ADC_S
ADC_S_ZZ
ADD_EQ
ADD_NE
ADD_CS
ADD_CC
ADD_MI
ADD_PL
ADD_VS
ADD_VC
ADD_HI
ADD_LS
ADD_GE
ADD_LT
ADD_GT
ADD_LE
ADD
ADD_ZZ
ADD_S_EQ
ADD_S_NE
ADD_S_CS
ADD_S_CC
ADD_S_MI
ADD_S_PL
ADD_S_VS
ADD_S_VC
ADD_S_HI
ADD_S_LS
ADD_S_GE
ADD_S_LT
ADD_S_GT
ADD_S_LE
ADD_S
ADD_S_ZZ
AND_EQ
AND_NE
AND_CS
AND_CC
AND_MI
AND_PL
AND_VS
AND_VC
AND_HI
AND_LS
AND_GE
AND_LT
AND_GT
AND_LE
AND
AND_ZZ
AND_S_EQ
AND_S_NE
AND_S_CS
AND_S_CC
AND_S_MI
AND_S_PL
AND_S_VS
AND_S_VC
AND_S_HI
AND_S_LS
AND_S_GE
AND_S_LT
AND_S_GT
AND_S_LE
AND_S
AND_S_ZZ
ASR_EQ
ASR_NE
ASR_CS
ASR_CC
ASR_MI
ASR_PL
ASR_VS
ASR_VC
ASR_HI
ASR_LS
ASR_GE
ASR_LT
ASR_GT
ASR_LE
ASR
ASR_ZZ
ASR_S_EQ
ASR_S_NE
ASR_S_CS
ASR_S_CC
ASR_S_MI
ASR_S_PL
ASR_S_VS
ASR_S_VC
ASR_S_HI
ASR_S_LS
ASR_S_GE
ASR_S_LT
ASR_S_GT
ASR_S_LE
ASR_S
ASR_S_ZZ
B_EQ
B_NE
B_CS
B_CC
B_MI
B_PL
B_VS
B_VC
B_HI
B_LS
B_GE
B_LT
B_GT
B_LE
B
B_ZZ
BFC_EQ
BFC_NE
BFC_CS
BFC_CC
BFC_MI
BFC_PL
BFC_VS
BFC_VC
BFC_HI
BFC_LS
BFC_GE
BFC_LT
BFC_GT
BFC_LE
BFC
BFC_ZZ
BFI_EQ
BFI_NE
BFI_CS
BFI_CC
BFI_MI
BFI_PL
BFI_VS
BFI_VC
BFI_HI
BFI_LS
BFI_GE
BFI_LT
BFI_GT
BFI_LE
BFI
BFI_ZZ
BIC_EQ
BIC_NE
BIC_CS
BIC_CC
BIC_MI
BIC_PL
BIC_VS
BIC_VC
BIC_HI
BIC_LS
BIC_GE
BIC_LT
BIC_GT
BIC_LE
BIC
BIC_ZZ
BIC_S_EQ
BIC_S_NE
BIC_S_CS
BIC_S_CC
BIC_S_MI
BIC_S_PL
BIC_S_VS
BIC_S_VC
BIC_S_HI
BIC_S_LS
BIC_S_GE
BIC_S_LT
BIC_S_GT
BIC_S_LE
BIC_S
BIC_S_ZZ
BKPT_EQ
BKPT_NE
BKPT_CS
BKPT_CC
BKPT_MI
BKPT_PL
BKPT_VS
BKPT_VC
BKPT_HI
BKPT_LS
BKPT_GE
BKPT_LT
BKPT_GT
BKPT_LE
BKPT
BKPT_ZZ
BL_EQ
BL_NE
BL_CS
BL_CC
BL_MI
BL_PL
BL_VS
BL_VC
BL_HI
BL_LS
BL_GE
BL_LT
BL_GT
BL_LE
BL
BL_ZZ
BLX_EQ
BLX_NE
BLX_CS
BLX_CC
BLX_MI
BLX_PL
BLX_VS
BLX_VC
BLX_HI
BLX_LS
BLX_GE
BLX_LT
BLX_GT
BLX_LE
BLX
BLX_ZZ
BX_EQ
BX_NE
BX_CS
BX_CC
BX_MI
BX_PL
BX_VS
BX_VC
BX_HI
BX_LS
BX_GE
BX_LT
BX_GT
BX_LE
BX
BX_ZZ
BXJ_EQ
BXJ_NE
BXJ_CS
BXJ_CC
BXJ_MI
BXJ_PL
BXJ_VS
BXJ_VC
BXJ_HI
BXJ_LS
BXJ_GE
BXJ_LT
BXJ_GT
BXJ_LE
BXJ
BXJ_ZZ
CLREX
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
CLZ_EQ
CLZ_NE
CLZ_CS
CLZ_CC
CLZ_MI
CLZ_PL
CLZ_VS
CLZ_VC
CLZ_HI
CLZ_LS
CLZ_GE
CLZ_LT
CLZ_GT
CLZ_LE
CLZ
CLZ_ZZ
CMN_EQ
CMN_NE
CMN_CS
CMN_CC
CMN_MI
CMN_PL
CMN_VS
CMN_VC
CMN_HI
CMN_LS
CMN_GE
CMN_LT
CMN_GT
CMN_LE
CMN
CMN_ZZ
CMP_EQ
CMP_NE
CMP_CS
CMP_CC
CMP_MI
CMP_PL
CMP_VS
CMP_VC
CMP_HI
CMP_LS
CMP_GE
CMP_LT
CMP_GT
CMP_LE
CMP
CMP_ZZ
DBG_EQ
DBG_NE
DBG_CS
DBG_CC
DBG_MI
DBG_PL
DBG_VS
DBG_VC
DBG_HI
DBG_LS
DBG_GE
DBG_LT
DBG_GT
DBG_LE
DBG
DBG_ZZ
DMB
DSB
_
_
_
_
_
_
_
_
_
_
_
_
_
_
EOR_EQ
EOR_NE
EOR_CS
EOR_CC
EOR_MI
EOR_PL
EOR_VS
EOR_VC
EOR_HI
EOR_LS
EOR_GE
EOR_LT
EOR_GT
EOR_LE
EOR
EOR_ZZ
EOR_S_EQ
EOR_S_NE
EOR_S_CS
EOR_S_CC
EOR_S_MI
EOR_S_PL
EOR_S_VS
EOR_S_VC
EOR_S_HI
EOR_S_LS
EOR_S_GE
EOR_S_LT
EOR_S_GT
EOR_S_LE
EOR_S
EOR_S_ZZ
ISB
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
LDM_EQ
LDM_NE
LDM_CS
LDM_CC
LDM_MI
LDM_PL
LDM_VS
LDM_VC
LDM_HI
LDM_LS
LDM_GE
LDM_LT
LDM_GT
LDM_LE
LDM
LDM_ZZ
LDMDA_EQ
LDMDA_NE
LDMDA_CS
LDMDA_CC
LDMDA_MI
LDMDA_PL
LDMDA_VS
LDMDA_VC
LDMDA_HI
LDMDA_LS
LDMDA_GE
LDMDA_LT
LDMDA_GT
LDMDA_LE
LDMDA
LDMDA_ZZ
LDMDB_EQ
LDMDB_NE
LDMDB_CS
LDMDB_CC
LDMDB_MI
LDMDB_PL
LDMDB_VS
LDMDB_VC
LDMDB_HI
LDMDB_LS
LDMDB_GE
LDMDB_LT
LDMDB_GT
LDMDB_LE
LDMDB
LDMDB_ZZ
LDMIB_EQ
LDMIB_NE
LDMIB_CS
LDMIB_CC
LDMIB_MI
LDMIB_PL
LDMIB_VS
LDMIB_VC
LDMIB_HI
LDMIB_LS
LDMIB_GE
LDMIB_LT
LDMIB_GT
LDMIB_LE
LDMIB
LDMIB_ZZ
LDR_EQ
LDR_NE
LDR_CS
LDR_CC
LDR_MI
LDR_PL
LDR_VS
LDR_VC
LDR_HI
LDR_LS
LDR_GE
LDR_LT
LDR_GT
LDR_LE
LDR
LDR_ZZ
LDRB_EQ
LDRB_NE
LDRB_CS
LDRB_CC
LDRB_MI
LDRB_PL
LDRB_VS
LDRB_VC
LDRB_HI
LDRB_LS
LDRB_GE
LDRB_LT
LDRB_GT
LDRB_LE
LDRB
LDRB_ZZ
LDRBT_EQ
LDRBT_NE
LDRBT_CS
LDRBT_CC
LDRBT_MI
LDRBT_PL
LDRBT_VS
LDRBT_VC
LDRBT_HI
LDRBT_LS
LDRBT_GE
LDRBT_LT
LDRBT_GT
LDRBT_LE
LDRBT
LDRBT_ZZ
LDRD_EQ
LDRD_NE
LDRD_CS
LDRD_CC
LDRD_MI
LDRD_PL
LDRD_VS
LDRD_VC
LDRD_HI
LDRD_LS
LDRD_GE
LDRD_LT
LDRD_GT
LDRD_LE
LDRD
LDRD_ZZ
LDREX_EQ
LDREX_NE
LDREX_CS
LDREX_CC
LDREX_MI
LDREX_PL
LDREX_VS
LDREX_VC
LDREX_HI
LDREX_LS
LDREX_GE
LDREX_LT
LDREX_GT
LDREX_LE
LDREX
LDREX_ZZ
LDREXB_EQ
LDREXB_NE
LDREXB_CS
LDREXB_CC
LDREXB_MI
LDREXB_PL
LDREXB_VS
LDREXB_VC
LDREXB_HI
LDREXB_LS
LDREXB_GE
LDREXB_LT
LDREXB_GT
LDREXB_LE
LDREXB
LDREXB_ZZ
LDREXD_EQ
LDREXD_NE
LDREXD_CS
LDREXD_CC
LDREXD_MI
LDREXD_PL
LDREXD_VS
LDREXD_VC
LDREXD_HI
LDREXD_LS
LDREXD_GE
LDREXD_LT
LDREXD_GT
LDREXD_LE
LDREXD
LDREXD_ZZ
LDREXH_EQ
LDREXH_NE
LDREXH_CS
LDREXH_CC
LDREXH_MI
LDREXH_PL
LDREXH_VS
LDREXH_VC
LDREXH_HI
LDREXH_LS
LDREXH_GE
LDREXH_LT
LDREXH_GT
LDREXH_LE
LDREXH
LDREXH_ZZ
LDRH_EQ
LDRH_NE
LDRH_CS
LDRH_CC
LDRH_MI
LDRH_PL
LDRH_VS
LDRH_VC
LDRH_HI
LDRH_LS
LDRH_GE
LDRH_LT
LDRH_GT
LDRH_LE
LDRH
LDRH_ZZ
LDRHT_EQ
LDRHT_NE
LDRHT_CS
LDRHT_CC
LDRHT_MI
LDRHT_PL
LDRHT_VS
LDRHT_VC
LDRHT_HI
LDRHT_LS
LDRHT_GE
LDRHT_LT
LDRHT_GT
LDRHT_LE
LDRHT
LDRHT_ZZ
LDRSB_EQ
LDRSB_NE
LDRSB_CS
LDRSB_CC
LDRSB_MI
LDRSB_PL
LDRSB_VS
LDRSB_VC
LDRSB_HI
LDRSB_LS
LDRSB_GE
LDRSB_LT
LDRSB_GT
LDRSB_LE
LDRSB
LDRSB_ZZ
LDRSBT_EQ
LDRSBT_NE
LDRSBT_CS
LDRSBT_CC
LDRSBT_MI
LDRSBT_PL
LDRSBT_VS
LDRSBT_VC
LDRSBT_HI
LDRSBT_LS
LDRSBT_GE
LDRSBT_LT
LDRSBT_GT
LDRSBT_LE
LDRSBT
LDRSBT_ZZ
LDRSH_EQ
LDRSH_NE
LDRSH_CS
LDRSH_CC
LDRSH_MI
LDRSH_PL
LDRSH_VS
LDRSH_VC
LDRSH_HI
LDRSH_LS
LDRSH_GE
LDRSH_LT
LDRSH_GT
LDRSH_LE
LDRSH
LDRSH_ZZ
LDRSHT_EQ
LDRSHT_NE
LDRSHT_CS
LDRSHT_CC
LDRSHT_MI
LDRSHT_PL
LDRSHT_VS
LDRSHT_VC
LDRSHT_HI
LDRSHT_LS
LDRSHT_GE
LDRSHT_LT
LDRSHT_GT
LDRSHT_LE
LDRSHT
LDRSHT_ZZ
LDRT_EQ
LDRT_NE
LDRT_CS
LDRT_CC
LDRT_MI
LDRT_PL
LDRT_VS
LDRT_VC
LDRT_HI
LDRT_LS
LDRT_GE
LDRT_LT
LDRT_GT
LDRT_LE
LDRT
LDRT_ZZ
LSL_EQ
LSL_NE
LSL_CS
LSL_CC
LSL_MI
LSL_PL
LSL_VS
LSL_VC
LSL_HI
LSL_LS
LSL_GE
LSL_LT
LSL_GT
LSL_LE
LSL
LSL_ZZ
LSL_S_EQ
LSL_S_NE
LSL_S_CS
LSL_S_CC
LSL_S_MI
LSL_S_PL
LSL_S_VS
LSL_S_VC
LSL_S_HI
LSL_S_LS
LSL_S_GE
LSL_S_LT
LSL_S_GT
LSL_S_LE
LSL_S
LSL_S_ZZ
LSR_EQ
LSR_NE
LSR_CS
LSR_CC
LSR_MI
LSR_PL
LSR_VS
LSR_VC
LSR_HI
LSR_LS
LSR_GE
LSR_LT
LSR_GT
LSR_LE
LSR
LSR_ZZ
LSR_S_EQ
LSR_S_NE
LSR_S_CS
LSR_S_CC
LSR_S_MI
LSR_S_PL
LSR_S_VS
LSR_S_VC
LSR_S_HI
LSR_S_LS
LSR_S_GE
LSR_S_LT
LSR_S_GT
LSR_S_LE
LSR_S
LSR_S_ZZ
MLA_EQ
MLA_NE
MLA_CS
MLA_CC
MLA_MI
MLA_PL
MLA_VS
MLA_VC
MLA_HI
MLA_LS
MLA_GE
MLA_LT
MLA_GT
MLA_LE
MLA
MLA_ZZ
MLA_S_EQ
MLA_S_NE
MLA_S_CS
MLA_S_CC
MLA_S_MI
MLA_S_PL
MLA_S_VS
MLA_S_VC
MLA_S_HI
MLA_S_LS
MLA_S_GE
MLA_S_LT
MLA_S_GT
MLA_S_LE
MLA_S
MLA_S_ZZ
MLS_EQ
MLS_NE
MLS_CS
MLS_CC
MLS_MI
MLS_PL
MLS_VS
MLS_VC
MLS_HI
MLS_LS
MLS_GE
MLS_LT
MLS_GT
MLS_LE
MLS
MLS_ZZ
MOV_EQ
MOV_NE
MOV_CS
MOV_CC
MOV_MI
MOV_PL
MOV_VS
MOV_VC
MOV_HI
MOV_LS
MOV_GE
MOV_LT
MOV_GT
MOV_LE
MOV
MOV_ZZ
MOV_S_EQ
MOV_S_NE
MOV_S_CS
MOV_S_CC
MOV_S_MI
MOV_S_PL
MOV_S_VS
MOV_S_VC
MOV_S_HI
MOV_S_LS
MOV_S_GE
MOV_S_LT
MOV_S_GT
MOV_S_LE
MOV_S
MOV_S_ZZ
MOVT_EQ
MOVT_NE
MOVT_CS
MOVT_CC
MOVT_MI
MOVT_PL
MOVT_VS
MOVT_VC
MOVT_HI
MOVT_LS
MOVT_GE
MOVT_LT
MOVT_GT
MOVT_LE
MOVT
MOVT_ZZ
MOVW_EQ
MOVW_NE
MOVW_CS
MOVW_CC
MOVW_MI
MOVW_PL
MOVW_VS
MOVW_VC
MOVW_HI
MOVW_LS
MOVW_GE
MOVW_LT
MOVW_GT
MOVW_LE
MOVW
MOVW_ZZ
MRS_EQ
MRS_NE
MRS_CS
MRS_CC
MRS_MI
MRS_PL
MRS_VS
MRS_VC
MRS_HI
MRS_LS
MRS_GE
MRS_LT
MRS_GT
MRS_LE
MRS
MRS_ZZ
MUL_EQ
MUL_NE
MUL_CS
MUL_CC
MUL_MI
MUL_PL
MUL_VS
MUL_VC
MUL_HI
MUL_LS
MUL_GE
MUL_LT
MUL_GT
MUL_LE
MUL
MUL_ZZ
MUL_S_EQ
MUL_S_NE
MUL_S_CS
MUL_S_CC
MUL_S_MI
MUL_S_PL
MUL_S_VS
MUL_S_VC
MUL_S_HI
MUL_S_LS
MUL_S_GE
MUL_S_LT
MUL_S_GT
MUL_S_LE
MUL_S
MUL_S_ZZ
MVN_EQ
MVN_NE
MVN_CS
MVN_CC
MVN_MI
MVN_PL
MVN_VS
MVN_VC
MVN_HI
MVN_LS
MVN_GE
MVN_LT
MVN_GT
MVN_LE
MVN
MVN_ZZ
MVN_S_EQ
MVN_S_NE
MVN_S_CS
MVN_S_CC
MVN_S_MI
MVN_S_PL
MVN_S_VS
MVN_S_VC
MVN_S_HI
MVN_S_LS
MVN_S_GE
MVN_S_LT
MVN_S_GT
MVN_S_LE
MVN_S
MVN_S_ZZ
NOP_EQ
NOP_NE
NOP_CS
NOP_CC
NOP_MI
NOP_PL
NOP_VS
NOP_VC
NOP_HI
NOP_LS
NOP_GE
NOP_LT
NOP_GT
NOP_LE
NOP
NOP_ZZ
ORR_EQ
ORR_NE
ORR_CS
ORR_CC
ORR_MI
ORR_PL
ORR_VS
ORR_VC
ORR_HI
ORR_LS
ORR_GE
ORR_LT
ORR_GT
ORR_LE
ORR
ORR_ZZ
ORR_S_EQ
ORR_S_NE
ORR_S_CS
ORR_S_CC
ORR_S_MI
ORR_S_PL
ORR_S_VS
ORR_S_VC
ORR_S_HI
ORR_S_LS
ORR_S_GE
ORR_S_LT
ORR_S_GT
ORR_S_LE
ORR_S
ORR_S_ZZ
PKHBT_EQ
PKHBT_NE
PKHBT_CS
PKHBT_CC
PKHBT_MI
PKHBT_PL
PKHBT_VS
PKHBT_VC
PKHBT_HI
PKHBT_LS
PKHBT_GE
PKHBT_LT
PKHBT_GT
PKHBT_LE
PKHBT
PKHBT_ZZ
PKHTB_EQ
PKHTB_NE
PKHTB_CS
PKHTB_CC
PKHTB_MI
PKHTB_PL
PKHTB_VS
PKHTB_VC
PKHTB_HI
PKHTB_LS
PKHTB_GE
PKHTB_LT
PKHTB_GT
PKHTB_LE
PKHTB
PKHTB_ZZ
PLD_W
PLD
PLI
_
_
_
_
_
_
_
_
_
_
_
_
_
POP_EQ
POP_NE
POP_CS
POP_CC
POP_MI
POP_PL
POP_VS
POP_VC
POP_HI
POP_LS
POP_GE
POP_LT
POP_GT
POP_LE
POP
POP_ZZ
PUSH_EQ
PUSH_NE
PUSH_CS
PUSH_CC
PUSH_MI
PUSH_PL
PUSH_VS
PUSH_VC
PUSH_HI
PUSH_LS
PUSH_GE
PUSH_LT
PUSH_GT
PUSH_LE
PUSH
PUSH_ZZ
QADD_EQ
QADD_NE
QADD_CS
QADD_CC
QADD_MI
QADD_PL
QADD_VS
QADD_VC
QADD_HI
QADD_LS
QADD_GE
QADD_LT
QADD_GT
QADD_LE
QADD
QADD_ZZ
QADD16_EQ
QADD16_NE
QADD16_CS
QADD16_CC
QADD16_MI
QADD16_PL
QADD16_VS
QADD16_VC
QADD16_HI
QADD16_LS
QADD16_GE
QADD16_LT
QADD16_GT
QADD16_LE
QADD16
QADD16_ZZ
QADD8_EQ
QADD8_NE
QADD8_CS
QADD8_CC
QADD8_MI
QADD8_PL
QADD8_VS
QADD8_VC
QADD8_HI
QADD8_LS
QADD8_GE
QADD8_LT
QADD8_GT
QADD8_LE
QADD8
QADD8_ZZ
QASX_EQ
QASX_NE
QASX_CS
QASX_CC
QASX_MI
QASX_PL
QASX_VS
QASX_VC
QASX_HI
QASX_LS
QASX_GE
QASX_LT
QASX_GT
QASX_LE
QASX
QASX_ZZ
QDADD_EQ
QDADD_NE
QDADD_CS
QDADD_CC
QDADD_MI
QDADD_PL
QDADD_VS
QDADD_VC
QDADD_HI
QDADD_LS
QDADD_GE
QDADD_LT
QDADD_GT
QDADD_LE
QDADD
QDADD_ZZ
QDSUB_EQ
QDSUB_NE
QDSUB_CS
QDSUB_CC
QDSUB_MI
QDSUB_PL
QDSUB_VS
QDSUB_VC
QDSUB_HI
QDSUB_LS
QDSUB_GE
QDSUB_LT
QDSUB_GT
QDSUB_LE
QDSUB
QDSUB_ZZ
QSAX_EQ
QSAX_NE
QSAX_CS
QSAX_CC
QSAX_MI
QSAX_PL
QSAX_VS
QSAX_VC
QSAX_HI
QSAX_LS
QSAX_GE
QSAX_LT
QSAX_GT
QSAX_LE
QSAX
QSAX_ZZ
QSUB_EQ
QSUB_NE
QSUB_CS
QSUB_CC
QSUB_MI
QSUB_PL
QSUB_VS
QSUB_VC
QSUB_HI
QSUB_LS
QSUB_GE
QSUB_LT
QSUB_GT
QSUB_LE
QSUB
QSUB_ZZ
QSUB16_EQ
QSUB16_NE
QSUB16_CS
QSUB16_CC
QSUB16_MI
QSUB16_PL
QSUB16_VS
QSUB16_VC
QSUB16_HI
QSUB16_LS
QSUB16_GE
QSUB16_LT
QSUB16_GT
QSUB16_LE
QSUB16
QSUB16_ZZ
QSUB8_EQ
QSUB8_NE
QSUB8_CS
QSUB8_CC
QSUB8_MI
QSUB8_PL
QSUB8_VS
QSUB8_VC
QSUB8_HI
QSUB8_LS
QSUB8_GE
QSUB8_LT
QSUB8_GT
QSUB8_LE
QSUB8
QSUB8_ZZ
RBIT_EQ
RBIT_NE
RBIT_CS
RBIT_CC
RBIT_MI
RBIT_PL
RBIT_VS
RBIT_VC
RBIT_HI
RBIT_LS
RBIT_GE
RBIT_LT
RBIT_GT
RBIT_LE
RBIT
RBIT_ZZ
REV_EQ
REV_NE
REV_CS
REV_CC
REV_MI
REV_PL
REV_VS
REV_VC
REV_HI
REV_LS
REV_GE
REV_LT
REV_GT
REV_LE
REV
REV_ZZ
REV16_EQ
REV16_NE
REV16_CS
REV16_CC
REV16_MI
REV16_PL
REV16_VS
REV16_VC
REV16_HI
REV16_LS
REV16_GE
REV16_LT
REV16_GT
REV16_LE
REV16
REV16_ZZ
REVSH_EQ
REVSH_NE
REVSH_CS
REVSH_CC
REVSH_MI
REVSH_PL
REVSH_VS
REVSH_VC
REVSH_HI
REVSH_LS
REVSH_GE
REVSH_LT
REVSH_GT
REVSH_LE
REVSH
REVSH_ZZ
ROR_EQ
ROR_NE
ROR_CS
ROR_CC
ROR_MI
ROR_PL
ROR_VS
ROR_VC
ROR_HI
ROR_LS
ROR_GE
ROR_LT
ROR_GT
ROR_LE
ROR
ROR_ZZ
ROR_S_EQ
ROR_S_NE
ROR_S_CS
ROR_S_CC
ROR_S_MI
ROR_S_PL
ROR_S_VS
ROR_S_VC
ROR_S_HI
ROR_S_LS
ROR_S_GE
ROR_S_LT
ROR_S_GT
ROR_S_LE
ROR_S
ROR_S_ZZ
RRX_EQ
RRX_NE
RRX_CS
RRX_CC
RRX_MI
RRX_PL
RRX_VS
RRX_VC
RRX_HI
RRX_LS
RRX_GE
RRX_LT
RRX_GT
RRX_LE
RRX
RRX_ZZ
RRX_S_EQ
RRX_S_NE
RRX_S_CS
RRX_S_CC
RRX_S_MI
RRX_S_PL
RRX_S_VS
RRX_S_VC
RRX_S_HI
RRX_S_LS
RRX_S_GE
RRX_S_LT
RRX_S_GT
RRX_S_LE
RRX_S
RRX_S_ZZ
RSB_EQ
RSB_NE
RSB_CS
RSB_CC
RSB_MI
RSB_PL
RSB_VS
RSB_VC
RSB_HI
RSB_LS
RSB_GE
RSB_LT
RSB_GT
RSB_LE
RSB
RSB_ZZ
RSB_S_EQ
RSB_S_NE
RSB_S_CS
RSB_S_CC
RSB_S_MI
RSB_S_PL
RSB_S_VS
RSB_S_VC
RSB_S_HI
RSB_S_LS
RSB_S_GE
RSB_S_LT
RSB_S_GT
RSB_S_LE
RSB_S
RSB_S_ZZ
RSC_EQ
RSC_NE
RSC_CS
RSC_CC
RSC_MI
RSC_PL
RSC_VS
RSC_VC
RSC_HI
RSC_LS
RSC_GE
RSC_LT
RSC_GT
RSC_LE
RSC
RSC_ZZ
RSC_S_EQ
RSC_S_NE
RSC_S_CS
RSC_S_CC
RSC_S_MI
RSC_S_PL
RSC_S_VS
RSC_S_VC
RSC_S_HI
RSC_S_LS
RSC_S_GE
RSC_S_LT
RSC_S_GT
RSC_S_LE
RSC_S
RSC_S_ZZ
SADD16_EQ
SADD16_NE
SADD16_CS
SADD16_CC
SADD16_MI
SADD16_PL
SADD16_VS
SADD16_VC
SADD16_HI
SADD16_LS
SADD16_GE
SADD16_LT
SADD16_GT
SADD16_LE
SADD16
SADD16_ZZ
SADD8_EQ
SADD8_NE
SADD8_CS
SADD8_CC
SADD8_MI
SADD8_PL
SADD8_VS
SADD8_VC
SADD8_HI
SADD8_LS
SADD8_GE
SADD8_LT
SADD8_GT
SADD8_LE
SADD8
SADD8_ZZ
SASX_EQ
SASX_NE
SASX_CS
SASX_CC
SASX_MI
SASX_PL
SASX_VS
SASX_VC
SASX_HI
SASX_LS
SASX_GE
SASX_LT
SASX_GT
SASX_LE
SASX
SASX_ZZ
SBC_EQ
SBC_NE
SBC_CS
SBC_CC
SBC_MI
SBC_PL
SBC_VS
SBC_VC
SBC_HI
SBC_LS
SBC_GE
SBC_LT
SBC_GT
SBC_LE
SBC
SBC_ZZ
SBC_S_EQ
SBC_S_NE
SBC_S_CS
SBC_S_CC
SBC_S_MI
SBC_S_PL
SBC_S_VS
SBC_S_VC
SBC_S_HI
SBC_S_LS
SBC_S_GE
SBC_S_LT
SBC_S_GT
SBC_S_LE
SBC_S
SBC_S_ZZ
SBFX_EQ
SBFX_NE
SBFX_CS
SBFX_CC
SBFX_MI
SBFX_PL
SBFX_VS
SBFX_VC
SBFX_HI
SBFX_LS
SBFX_GE
SBFX_LT
SBFX_GT
SBFX_LE
SBFX
SBFX_ZZ
SEL_EQ
SEL_NE
SEL_CS
SEL_CC
SEL_MI
SEL_PL
SEL_VS
SEL_VC
SEL_HI
SEL_LS
SEL_GE
SEL_LT
SEL_GT
SEL_LE
SEL
SEL_ZZ
SETEND
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
SEV_EQ
SEV_NE
SEV_CS
SEV_CC
SEV_MI
SEV_PL
SEV_VS
SEV_VC
SEV_HI
SEV_LS
SEV_GE
SEV_LT
SEV_GT
SEV_LE
SEV
SEV_ZZ
SHADD16_EQ
SHADD16_NE
SHADD16_CS
SHADD16_CC
SHADD16_MI
SHADD16_PL
SHADD16_VS
SHADD16_VC
SHADD16_HI
SHADD16_LS
SHADD16_GE
SHADD16_LT
SHADD16_GT
SHADD16_LE
SHADD16
SHADD16_ZZ
SHADD8_EQ
SHADD8_NE
SHADD8_CS
SHADD8_CC
SHADD8_MI
SHADD8_PL
SHADD8_VS
SHADD8_VC
SHADD8_HI
SHADD8_LS
SHADD8_GE
SHADD8_LT
SHADD8_GT
SHADD8_LE
SHADD8
SHADD8_ZZ
SHASX_EQ
SHASX_NE
SHASX_CS
SHASX_CC
SHASX_MI
SHASX_PL
SHASX_VS
SHASX_VC
SHASX_HI
SHASX_LS
SHASX_GE
SHASX_LT
SHASX_GT
SHASX_LE
SHASX
SHASX_ZZ
SHSAX_EQ
SHSAX_NE
SHSAX_CS
SHSAX_CC
SHSAX_MI
SHSAX_PL
SHSAX_VS
SHSAX_VC
SHSAX_HI
SHSAX_LS
SHSAX_GE
SHSAX_LT
SHSAX_GT
SHSAX_LE
SHSAX
SHSAX_ZZ
SHSUB16_EQ
SHSUB16_NE
SHSUB16_CS
SHSUB16_CC
SHSUB16_MI
SHSUB16_PL
SHSUB16_VS
SHSUB16_VC
SHSUB16_HI
SHSUB16_LS
SHSUB16_GE
SHSUB16_LT
SHSUB16_GT
SHSUB16_LE
SHSUB16
SHSUB16_ZZ
SHSUB8_EQ
SHSUB8_NE
SHSUB8_CS
SHSUB8_CC
SHSUB8_MI
SHSUB8_PL
SHSUB8_VS
SHSUB8_VC
SHSUB8_HI
SHSUB8_LS
SHSUB8_GE
SHSUB8_LT
SHSUB8_GT
SHSUB8_LE
SHSUB8
SHSUB8_ZZ
SMLABB_EQ
SMLABB_NE
SMLABB_CS
SMLABB_CC
SMLABB_MI
SMLABB_PL
SMLABB_VS
SMLABB_VC
SMLABB_HI
SMLABB_LS
SMLABB_GE
SMLABB_LT
SMLABB_GT
SMLABB_LE
SMLABB
SMLABB_ZZ
SMLABT_EQ
SMLABT_NE
SMLABT_CS
SMLABT_CC
SMLABT_MI
SMLABT_PL
SMLABT_VS
SMLABT_VC
SMLABT_HI
SMLABT_LS
SMLABT_GE
SMLABT_LT
SMLABT_GT
SMLABT_LE
SMLABT
SMLABT_ZZ
SMLATB_EQ
SMLATB_NE
SMLATB_CS
SMLATB_CC
SMLATB_MI
SMLATB_PL
SMLATB_VS
SMLATB_VC
SMLATB_HI
SMLATB_LS
SMLATB_GE
SMLATB_LT
SMLATB_GT
SMLATB_LE
SMLATB
SMLATB_ZZ
SMLATT_EQ
SMLATT_NE
SMLATT_CS
SMLATT_CC
SMLATT_MI
SMLATT_PL
SMLATT_VS
SMLATT_VC
SMLATT_HI
SMLATT_LS
SMLATT_GE
SMLATT_LT
SMLATT_GT
SMLATT_LE
SMLATT
SMLATT_ZZ
SMLAD_EQ
SMLAD_NE
SMLAD_CS
SMLAD_CC
SMLAD_MI
SMLAD_PL
SMLAD_VS
SMLAD_VC
SMLAD_HI
SMLAD_LS
SMLAD_GE
SMLAD_LT
SMLAD_GT
SMLAD_LE
SMLAD
SMLAD_ZZ
SMLAD_X_EQ
SMLAD_X_NE
SMLAD_X_CS
SMLAD_X_CC
SMLAD_X_MI
SMLAD_X_PL
SMLAD_X_VS
SMLAD_X_VC
SMLAD_X_HI
SMLAD_X_LS
SMLAD_X_GE
SMLAD_X_LT
SMLAD_X_GT
SMLAD_X_LE
SMLAD_X
SMLAD_X_ZZ
SMLAL_EQ
SMLAL_NE
SMLAL_CS
SMLAL_CC
SMLAL_MI
SMLAL_PL
SMLAL_VS
SMLAL_VC
SMLAL_HI
SMLAL_LS
SMLAL_GE
SMLAL_LT
SMLAL_GT
SMLAL_LE
SMLAL
SMLAL_ZZ
SMLAL_S_EQ
SMLAL_S_NE
SMLAL_S_CS
SMLAL_S_CC
SMLAL_S_MI
SMLAL_S_PL
SMLAL_S_VS
SMLAL_S_VC
SMLAL_S_HI
SMLAL_S_LS
SMLAL_S_GE
SMLAL_S_LT
SMLAL_S_GT
SMLAL_S_LE
SMLAL_S
SMLAL_S_ZZ
SMLALBB_EQ
SMLALBB_NE
SMLALBB_CS
SMLALBB_CC
SMLALBB_MI
SMLALBB_PL
SMLALBB_VS
SMLALBB_VC
SMLALBB_HI
SMLALBB_LS
SMLALBB_GE
SMLALBB_LT
SMLALBB_GT
SMLALBB_LE
SMLALBB
SMLALBB_ZZ
SMLALBT_EQ
SMLALBT_NE
SMLALBT_CS
SMLALBT_CC
SMLALBT_MI
SMLALBT_PL
SMLALBT_VS
SMLALBT_VC
SMLALBT_HI
SMLALBT_LS
SMLALBT_GE
SMLALBT_LT
SMLALBT_GT
SMLALBT_LE
SMLALBT
SMLALBT_ZZ
SMLALTB_EQ
SMLALTB_NE
SMLALTB_CS
SMLALTB_CC
SMLALTB_MI
SMLALTB_PL
SMLALTB_VS
SMLALTB_VC
SMLALTB_HI
SMLALTB_LS
SMLALTB_GE
SMLALTB_LT
SMLALTB_GT
SMLALTB_LE
SMLALTB
SMLALTB_ZZ
SMLALTT_EQ
SMLALTT_NE
SMLALTT_CS
SMLALTT_CC
SMLALTT_MI
SMLALTT_PL
SMLALTT_VS
SMLALTT_VC
SMLALTT_HI
SMLALTT_LS
SMLALTT_GE
SMLALTT_LT
SMLALTT_GT
SMLALTT_LE
SMLALTT
SMLALTT_ZZ
SMLALD_EQ
SMLALD_NE
SMLALD_CS
SMLALD_CC
SMLALD_MI
SMLALD_PL
SMLALD_VS
SMLALD_VC
SMLALD_HI
SMLALD_LS
SMLALD_GE
SMLALD_LT
SMLALD_GT
SMLALD_LE
SMLALD
SMLALD_ZZ
SMLALD_X_EQ
SMLALD_X_NE
SMLALD_X_CS
SMLALD_X_CC
SMLALD_X_MI
SMLALD_X_PL
SMLALD_X_VS
SMLALD_X_VC
SMLALD_X_HI
SMLALD_X_LS
SMLALD_X_GE
SMLALD_X_LT
SMLALD_X_GT
SMLALD_X_LE
SMLALD_X
SMLALD_X_ZZ
SMLAWB_EQ
SMLAWB_NE
SMLAWB_CS
SMLAWB_CC
SMLAWB_MI
SMLAWB_PL
SMLAWB_VS
SMLAWB_VC
SMLAWB_HI
SMLAWB_LS
SMLAWB_GE
SMLAWB_LT
SMLAWB_GT
SMLAWB_LE
SMLAWB
SMLAWB_ZZ
SMLAWT_EQ
SMLAWT_NE
SMLAWT_CS
SMLAWT_CC
SMLAWT_MI
SMLAWT_PL
SMLAWT_VS
SMLAWT_VC
SMLAWT_HI
SMLAWT_LS
SMLAWT_GE
SMLAWT_LT
SMLAWT_GT
SMLAWT_LE
SMLAWT
SMLAWT_ZZ
SMLSD_EQ
SMLSD_NE
SMLSD_CS
SMLSD_CC
SMLSD_MI
SMLSD_PL
SMLSD_VS
SMLSD_VC
SMLSD_HI
SMLSD_LS
SMLSD_GE
SMLSD_LT
SMLSD_GT
SMLSD_LE
SMLSD
SMLSD_ZZ
SMLSD_X_EQ
SMLSD_X_NE
SMLSD_X_CS
SMLSD_X_CC
SMLSD_X_MI
SMLSD_X_PL
SMLSD_X_VS
SMLSD_X_VC
SMLSD_X_HI
SMLSD_X_LS
SMLSD_X_GE
SMLSD_X_LT
SMLSD_X_GT
SMLSD_X_LE
SMLSD_X
SMLSD_X_ZZ
SMLSLD_EQ
SMLSLD_NE
SMLSLD_CS
SMLSLD_CC
SMLSLD_MI
SMLSLD_PL
SMLSLD_VS
SMLSLD_VC
SMLSLD_HI
SMLSLD_LS
SMLSLD_GE
SMLSLD_LT
SMLSLD_GT
SMLSLD_LE
SMLSLD
SMLSLD_ZZ
SMLSLD_X_EQ
SMLSLD_X_NE
SMLSLD_X_CS
SMLSLD_X_CC
SMLSLD_X_MI
SMLSLD_X_PL
SMLSLD_X_VS
SMLSLD_X_VC
SMLSLD_X_HI
SMLSLD_X_LS
SMLSLD_X_GE
SMLSLD_X_LT
SMLSLD_X_GT
SMLSLD_X_LE
SMLSLD_X
SMLSLD_X_ZZ
SMMLA_EQ
SMMLA_NE
SMMLA_CS
SMMLA_CC
SMMLA_MI
SMMLA_PL
SMMLA_VS
SMMLA_VC
SMMLA_HI
SMMLA_LS
SMMLA_GE
SMMLA_LT
SMMLA_GT
SMMLA_LE
SMMLA
SMMLA_ZZ
SMMLA_R_EQ
SMMLA_R_NE
SMMLA_R_CS
SMMLA_R_CC
SMMLA_R_MI
SMMLA_R_PL
SMMLA_R_VS
SMMLA_R_VC
SMMLA_R_HI
SMMLA_R_LS
SMMLA_R_GE
SMMLA_R_LT
SMMLA_R_GT
SMMLA_R_LE
SMMLA_R
SMMLA_R_ZZ
SMMLS_EQ
SMMLS_NE
SMMLS_CS
SMMLS_CC
SMMLS_MI
SMMLS_PL
SMMLS_VS
SMMLS_VC
SMMLS_HI
SMMLS_LS
SMMLS_GE
SMMLS_LT
SMMLS_GT
SMMLS_LE
SMMLS
SMMLS_ZZ
SMMLS_R_EQ
SMMLS_R_NE
SMMLS_R_CS
SMMLS_R_CC
SMMLS_R_MI
SMMLS_R_PL
SMMLS_R_VS
SMMLS_R_VC
SMMLS_R_HI
SMMLS_R_LS
SMMLS_R_GE
SMMLS_R_LT
SMMLS_R_GT
SMMLS_R_LE
SMMLS_R
SMMLS_R_ZZ
SMMUL_EQ
SMMUL_NE
SMMUL_CS
SMMUL_CC
SMMUL_MI
SMMUL_PL
SMMUL_VS
SMMUL_VC
SMMUL_HI
SMMUL_LS
SMMUL_GE
SMMUL_LT
SMMUL_GT
SMMUL_LE
SMMUL
SMMUL_ZZ
SMMUL_R_EQ
SMMUL_R_NE
SMMUL_R_CS
SMMUL_R_CC
SMMUL_R_MI
SMMUL_R_PL
SMMUL_R_VS
SMMUL_R_VC
SMMUL_R_HI
SMMUL_R_LS
SMMUL_R_GE
SMMUL_R_LT
SMMUL_R_GT
SMMUL_R_LE
SMMUL_R
SMMUL_R_ZZ
SMUAD_EQ
SMUAD_NE
SMUAD_CS
SMUAD_CC
SMUAD_MI
SMUAD_PL
SMUAD_VS
SMUAD_VC
SMUAD_HI
SMUAD_LS
SMUAD_GE
SMUAD_LT
SMUAD_GT
SMUAD_LE
SMUAD
SMUAD_ZZ
SMUAD_X_EQ
SMUAD_X_NE
SMUAD_X_CS
SMUAD_X_CC
SMUAD_X_MI
SMUAD_X_PL
SMUAD_X_VS
SMUAD_X_VC
SMUAD_X_HI
SMUAD_X_LS
SMUAD_X_GE
SMUAD_X_LT
SMUAD_X_GT
SMUAD_X_LE
SMUAD_X
SMUAD_X_ZZ
SMULBB_EQ
SMULBB_NE
SMULBB_CS
SMULBB_CC
SMULBB_MI
SMULBB_PL
SMULBB_VS
SMULBB_VC
SMULBB_HI
SMULBB_LS
SMULBB_GE
SMULBB_LT
SMULBB_GT
SMULBB_LE
SMULBB
SMULBB_ZZ
SMULBT_EQ
SMULBT_NE
SMULBT_CS
SMULBT_CC
SMULBT_MI
SMULBT_PL
SMULBT_VS
SMULBT_VC
SMULBT_HI
SMULBT_LS
SMULBT_GE
SMULBT_LT
SMULBT_GT
SMULBT_LE
SMULBT
SMULBT_ZZ
SMULTB_EQ
SMULTB_NE
SMULTB_CS
SMULTB_CC
SMULTB_MI
SMULTB_PL
SMULTB_VS
SMULTB_VC
SMULTB_HI
SMULTB_LS
SMULTB_GE
SMULTB_LT
SMULTB_GT
SMULTB_LE
SMULTB
SMULTB_ZZ
SMULTT_EQ
SMULTT_NE
SMULTT_CS
SMULTT_CC
SMULTT_MI
SMULTT_PL
SMULTT_VS
SMULTT_VC
SMULTT_HI
SMULTT_LS
SMULTT_GE
SMULTT_LT
SMULTT_GT
SMULTT_LE
SMULTT
SMULTT_ZZ
SMULL_EQ
SMULL_NE
SMULL_CS
SMULL_CC
SMULL_MI
SMULL_PL
SMULL_VS
SMULL_VC
SMULL_HI
SMULL_LS
SMULL_GE
SMULL_LT
SMULL_GT
SMULL_LE
SMULL
SMULL_ZZ
SMULL_S_EQ
SMULL_S_NE
SMULL_S_CS
SMULL_S_CC
SMULL_S_MI
SMULL_S_PL
SMULL_S_VS
SMULL_S_VC
SMULL_S_HI
SMULL_S_LS
SMULL_S_GE
SMULL_S_LT
SMULL_S_GT
SMULL_S_LE
SMULL_S
SMULL_S_ZZ
SMULWB_EQ
SMULWB_NE
SMULWB_CS
SMULWB_CC
SMULWB_MI
SMULWB_PL
SMULWB_VS
SMULWB_VC
SMULWB_HI
SMULWB_LS
SMULWB_GE
SMULWB_LT
SMULWB_GT
SMULWB_LE
SMULWB
SMULWB_ZZ
SMULWT_EQ
SMULWT_NE
SMULWT_CS
SMULWT_CC
SMULWT_MI
SMULWT_PL
SMULWT_VS
SMULWT_VC
SMULWT_HI
SMULWT_LS
SMULWT_GE
SMULWT_LT
SMULWT_GT
SMULWT_LE
SMULWT
SMULWT_ZZ
SMUSD_EQ
SMUSD_NE
SMUSD_CS
SMUSD_CC
SMUSD_MI
SMUSD_PL
SMUSD_VS
SMUSD_VC
SMUSD_HI
SMUSD_LS
SMUSD_GE
SMUSD_LT
SMUSD_GT
SMUSD_LE
SMUSD
SMUSD_ZZ
SMUSD_X_EQ
SMUSD_X_NE
SMUSD_X_CS
SMUSD_X_CC
SMUSD_X_MI
SMUSD_X_PL
SMUSD_X_VS
SMUSD_X_VC
SMUSD_X_HI
SMUSD_X_LS
SMUSD_X_GE
SMUSD_X_LT
SMUSD_X_GT
SMUSD_X_LE
SMUSD_X
SMUSD_X_ZZ
SSAT_EQ
SSAT_NE
SSAT_CS
SSAT_CC
SSAT_MI
SSAT_PL
SSAT_VS
SSAT_VC
SSAT_HI
SSAT_LS
SSAT_GE
SSAT_LT
SSAT_GT
SSAT_LE
SSAT
SSAT_ZZ
SSAT16_EQ
SSAT16_NE
SSAT16_CS
SSAT16_CC
SSAT16_MI
SSAT16_PL
SSAT16_VS
SSAT16_VC
SSAT16_HI
SSAT16_LS
SSAT16_GE
SSAT16_LT
SSAT16_GT
SSAT16_LE
SSAT16
SSAT16_ZZ
SSAX_EQ
SSAX_NE
SSAX_CS
SSAX_CC
SSAX_MI
SSAX_PL
SSAX_VS
SSAX_VC
SSAX_HI
SSAX_LS
SSAX_GE
SSAX_LT
SSAX_GT
SSAX_LE
SSAX
SSAX_ZZ
SSUB16_EQ
SSUB16_NE
SSUB16_CS
SSUB16_CC
SSUB16_MI
SSUB16_PL
SSUB16_VS
SSUB16_VC
SSUB16_HI
SSUB16_LS
SSUB16_GE
SSUB16_LT
SSUB16_GT
SSUB16_LE
SSUB16
SSUB16_ZZ
SSUB8_EQ
SSUB8_NE
SSUB8_CS
SSUB8_CC
SSUB8_MI
SSUB8_PL
SSUB8_VS
SSUB8_VC
SSUB8_HI
SSUB8_LS
SSUB8_GE
SSUB8_LT
SSUB8_GT
SSUB8_LE
SSUB8
SSUB8_ZZ
STM_EQ
STM_NE
STM_CS
STM_CC
STM_MI
STM_PL
STM_VS
STM_VC
STM_HI
STM_LS
STM_GE
STM_LT
STM_GT
STM_LE
STM
STM_ZZ
STMDA_EQ
STMDA_NE
STMDA_CS
STMDA_CC
STMDA_MI
STMDA_PL
STMDA_VS
STMDA_VC
STMDA_HI
STMDA_LS
STMDA_GE
STMDA_LT
STMDA_GT
STMDA_LE
STMDA
STMDA_ZZ
STMDB_EQ
STMDB_NE
STMDB_CS
STMDB_CC
STMDB_MI
STMDB_PL
STMDB_VS
STMDB_VC
STMDB_HI
STMDB_LS
STMDB_GE
STMDB_LT
STMDB_GT
STMDB_LE
STMDB
STMDB_ZZ
STMIB_EQ
STMIB_NE
STMIB_CS
STMIB_CC
STMIB_MI
STMIB_PL
STMIB_VS
STMIB_VC
STMIB_HI
STMIB_LS
STMIB_GE
STMIB_LT
STMIB_GT
STMIB_LE
STMIB
STMIB_ZZ
STR_EQ
STR_NE
STR_CS
STR_CC
STR_MI
STR_PL
STR_VS
STR_VC
STR_HI
STR_LS
STR_GE
STR_LT
STR_GT
STR_LE
STR
STR_ZZ
STRB_EQ
STRB_NE
STRB_CS
STRB_CC
STRB_MI
STRB_PL
STRB_VS
STRB_VC
STRB_HI
STRB_LS
STRB_GE
STRB_LT
STRB_GT
STRB_LE
STRB
STRB_ZZ
STRBT_EQ
STRBT_NE
STRBT_CS
STRBT_CC
STRBT_MI
STRBT_PL
STRBT_VS
STRBT_VC
STRBT_HI
STRBT_LS
STRBT_GE
STRBT_LT
STRBT_GT
STRBT_LE
STRBT
STRBT_ZZ
STRD_EQ
STRD_NE
STRD_CS
STRD_CC
STRD_MI
STRD_PL
STRD_VS
STRD_VC
STRD_HI
STRD_LS
STRD_GE
STRD_LT
STRD_GT
STRD_LE
STRD
STRD_ZZ
STREX_EQ
STREX_NE
STREX_CS
STREX_CC
STREX_MI
STREX_PL
STREX_VS
STREX_VC
STREX_HI
STREX_LS
STREX_GE
STREX_LT
STREX_GT
STREX_LE
STREX
STREX_ZZ
STREXB_EQ
STREXB_NE
STREXB_CS
STREXB_CC
STREXB_MI
STREXB_PL
STREXB_VS
STREXB_VC
STREXB_HI
STREXB_LS
STREXB_GE
STREXB_LT
STREXB_GT
STREXB_LE
STREXB
STREXB_ZZ
STREXD_EQ
STREXD_NE
STREXD_CS
STREXD_CC
STREXD_MI
STREXD_PL
STREXD_VS
STREXD_VC
STREXD_HI
STREXD_LS
STREXD_GE
STREXD_LT
STREXD_GT
STREXD_LE
STREXD
STREXD_ZZ
STREXH_EQ
STREXH_NE
STREXH_CS
STREXH_CC
STREXH_MI
STREXH_PL
STREXH_VS
STREXH_VC
STREXH_HI
STREXH_LS
STREXH_GE
STREXH_LT
STREXH_GT
STREXH_LE
STREXH
STREXH_ZZ
STRH_EQ
STRH_NE
STRH_CS
STRH_CC
STRH_MI
STRH_PL
STRH_VS
STRH_VC
STRH_HI
STRH_LS
STRH_GE
STRH_LT
STRH_GT
STRH_LE
STRH
STRH_ZZ
STRHT_EQ
STRHT_NE
STRHT_CS
STRHT_CC
STRHT_MI
STRHT_PL
STRHT_VS
STRHT_VC
STRHT_HI
STRHT_LS
STRHT_GE
STRHT_LT
STRHT_GT
STRHT_LE
STRHT
STRHT_ZZ
STRT_EQ
STRT_NE
STRT_CS
STRT_CC
STRT_MI
STRT_PL
STRT_VS
STRT_VC
STRT_HI
STRT_LS
STRT_GE
STRT_LT
STRT_GT
STRT_LE
STRT
STRT_ZZ
SUB_EQ
SUB_NE
SUB_CS
SUB_CC
SUB_MI
SUB_PL
SUB_VS
SUB_VC
SUB_HI
SUB_LS
SUB_GE
SUB_LT
SUB_GT
SUB_LE
SUB
SUB_ZZ
SUB_S_EQ
SUB_S_NE
SUB_S_CS
SUB_S_CC
SUB_S_MI
SUB_S_PL
SUB_S_VS
SUB_S_VC
SUB_S_HI
SUB_S_LS
SUB_S_GE
SUB_S_LT
SUB_S_GT
SUB_S_LE
SUB_S
SUB_S_ZZ
SVC_EQ
SVC_NE
SVC_CS
SVC_CC
SVC_MI
SVC_PL
SVC_VS
SVC_VC
SVC_HI
SVC_LS
SVC_GE
SVC_LT
SVC_GT
SVC_LE
SVC
SVC_ZZ
SWP_EQ
SWP_NE
SWP_CS
SWP_CC
SWP_MI
SWP_PL
SWP_VS
SWP_VC
SWP_HI
SWP_LS
SWP_GE
SWP_LT
SWP_GT
SWP_LE
SWP
SWP_ZZ
SWP_B_EQ
SWP_B_NE
SWP_B_CS
SWP_B_CC
SWP_B_MI
SWP_B_PL
SWP_B_VS
SWP_B_VC
SWP_B_HI
SWP_B_LS
SWP_B_GE
SWP_B_LT
SWP_B_GT
SWP_B_LE
SWP_B
SWP_B_ZZ
SXTAB_EQ
SXTAB_NE
SXTAB_CS
SXTAB_CC
SXTAB_MI
SXTAB_PL
SXTAB_VS
SXTAB_VC
SXTAB_HI
SXTAB_LS
SXTAB_GE
SXTAB_LT
SXTAB_GT
SXTAB_LE
SXTAB
SXTAB_ZZ
SXTAB16_EQ
SXTAB16_NE
SXTAB16_CS
SXTAB16_CC
SXTAB16_MI
SXTAB16_PL
SXTAB16_VS
SXTAB16_VC
SXTAB16_HI
SXTAB16_LS
SXTAB16_GE
SXTAB16_LT
SXTAB16_GT
SXTAB16_LE
SXTAB16
SXTAB16_ZZ
SXTAH_EQ
SXTAH_NE
SXTAH_CS
SXTAH_CC
SXTAH_MI
SXTAH_PL
SXTAH_VS
SXTAH_VC
SXTAH_HI
SXTAH_LS
SXTAH_GE
SXTAH_LT
SXTAH_GT
SXTAH_LE
SXTAH
SXTAH_ZZ
SXTB_EQ
SXTB_NE
SXTB_CS
SXTB_CC
SXTB_MI
SXTB_PL
SXTB_VS
SXTB_VC
SXTB_HI
SXTB_LS
SXTB_GE
SXTB_LT
SXTB_GT
SXTB_LE
SXTB
SXTB_ZZ
SXTB16_EQ
SXTB16_NE
SXTB16_CS
SXTB16_CC
SXTB16_MI
SXTB16_PL
SXTB16_VS
SXTB16_VC
SXTB16_HI
SXTB16_LS
SXTB16_GE
SXTB16_LT
SXTB16_GT
SXTB16_LE
SXTB16
SXTB16_ZZ
SXTH_EQ
SXTH_NE
SXTH_CS
SXTH_CC
SXTH_MI
SXTH_PL
SXTH_VS
SXTH_VC
SXTH_HI
SXTH_LS
SXTH_GE
SXTH_LT
SXTH_GT
SXTH_LE
SXTH
SXTH_ZZ
TEQ_EQ
TEQ_NE
TEQ_CS
TEQ_CC
TEQ_MI
TEQ_PL
TEQ_VS
TEQ_VC
TEQ_HI
TEQ_LS
TEQ_GE
TEQ_LT
TEQ_GT
TEQ_LE
TEQ
TEQ_ZZ
TST_EQ
TST_NE
TST_CS
TST_CC
TST_MI
TST_PL
TST_VS
TST_VC
TST_HI
TST_LS
TST_GE
TST_LT
TST_GT
TST_LE
TST
TST_ZZ
UADD16_EQ
UADD16_NE
UADD16_CS
UADD16_CC
UADD16_MI
UADD16_PL
UADD16_VS
UADD16_VC
UADD16_HI
UADD16_LS
UADD16_GE
UADD16_LT
UADD16_GT
UADD16_LE
UADD16
UADD16_ZZ
UADD8_EQ
UADD8_NE
UADD8_CS
UADD8_CC
UADD8_MI
UADD8_PL
UADD8_VS
UADD8_VC
UADD8_HI
UADD8_LS
UADD8_GE
UADD8_LT
UADD8_GT
UADD8_LE
UADD8
UADD8_ZZ
UASX_EQ
UASX_NE
UASX_CS
UASX_CC
UASX_MI
UASX_PL
UASX_VS
UASX_VC
UASX_HI
UASX_LS
UASX_GE
UASX_LT
UASX_GT
UASX_LE
UASX
UASX_ZZ
UBFX_EQ
UBFX_NE
UBFX_CS
UBFX_CC
UBFX_MI
UBFX_PL
UBFX_VS
UBFX_VC
UBFX_HI
UBFX_LS
UBFX_GE
UBFX_LT
UBFX_GT
UBFX_LE
UBFX
UBFX_ZZ
UHADD16_EQ
UHADD16_NE
UHADD16_CS
UHADD16_CC
UHADD16_MI
UHADD16_PL
UHADD16_VS
UHADD16_VC
UHADD16_HI
UHADD16_LS
UHADD16_GE
UHADD16_LT
UHADD16_GT
UHADD16_LE
UHADD16
UHADD16_ZZ
UHADD8_EQ
UHADD8_NE
UHADD8_CS
UHADD8_CC
UHADD8_MI
UHADD8_PL
UHADD8_VS
UHADD8_VC
UHADD8_HI
UHADD8_LS
UHADD8_GE
UHADD8_LT
UHADD8_GT
UHADD8_LE
UHADD8
UHADD8_ZZ
UHASX_EQ
UHASX_NE
UHASX_CS
UHASX_CC
UHASX_MI
UHASX_PL
UHASX_VS
UHASX_VC
UHASX_HI
UHASX_LS
UHASX_GE
UHASX_LT
UHASX_GT
UHASX_LE
UHASX
UHASX_ZZ
UHSAX_EQ
UHSAX_NE
UHSAX_CS
UHSAX_CC
UHSAX_MI
UHSAX_PL
UHSAX_VS
UHSAX_VC
UHSAX_HI
UHSAX_LS
UHSAX_GE
UHSAX_LT
UHSAX_GT
UHSAX_LE
UHSAX
UHSAX_ZZ
UHSUB16_EQ
UHSUB16_NE
UHSUB16_CS
UHSUB16_CC
UHSUB16_MI
UHSUB16_PL
UHSUB16_VS
UHSUB16_VC
UHSUB16_HI
UHSUB16_LS
UHSUB16_GE
UHSUB16_LT
UHSUB16_GT
UHSUB16_LE
UHSUB16
UHSUB16_ZZ
UHSUB8_EQ
UHSUB8_NE
UHSUB8_CS
UHSUB8_CC
UHSUB8_MI
UHSUB8_PL
UHSUB8_VS
UHSUB8_VC
UHSUB8_HI
UHSUB8_LS
UHSUB8_GE
UHSUB8_LT
UHSUB8_GT
UHSUB8_LE
UHSUB8
UHSUB8_ZZ
UMAAL_EQ
UMAAL_NE
UMAAL_CS
UMAAL_CC
UMAAL_MI
UMAAL_PL
UMAAL_VS
UMAAL_VC
UMAAL_HI
UMAAL_LS
UMAAL_GE
UMAAL_LT
UMAAL_GT
UMAAL_LE
UMAAL
UMAAL_ZZ
UMLAL_EQ
UMLAL_NE
UMLAL_CS
UMLAL_CC
UMLAL_MI
UMLAL_PL
UMLAL_VS
UMLAL_VC
UMLAL_HI
UMLAL_LS
UMLAL_GE
UMLAL_LT
UMLAL_GT
UMLAL_LE
UMLAL
UMLAL_ZZ
UMLAL_S_EQ
UMLAL_S_NE
UMLAL_S_CS
UMLAL_S_CC
UMLAL_S_MI
UMLAL_S_PL
UMLAL_S_VS
UMLAL_S_VC
UMLAL_S_HI
UMLAL_S_LS
UMLAL_S_GE
UMLAL_S_LT
UMLAL_S_GT
UMLAL_S_LE
UMLAL_S
UMLAL_S_ZZ
UMULL_EQ
UMULL_NE
UMULL_CS
UMULL_CC
UMULL_MI
UMULL_PL
UMULL_VS
UMULL_VC
UMULL_HI
UMULL_LS
UMULL_GE
UMULL_LT
UMULL_GT
UMULL_LE
UMULL
UMULL_ZZ
UMULL_S_EQ
UMULL_S_NE
UMULL_S_CS
UMULL_S_CC
UMULL_S_MI
UMULL_S_PL
UMULL_S_VS
UMULL_S_VC
UMULL_S_HI
UMULL_S_LS
UMULL_S_GE
UMULL_S_LT
UMULL_S_GT
UMULL_S_LE
UMULL_S
UMULL_S_ZZ
UNDEF
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
UQADD16_EQ
UQADD16_NE
UQADD16_CS
UQADD16_CC
UQADD16_MI
UQADD16_PL
UQADD16_VS
UQADD16_VC
UQADD16_HI
UQADD16_LS
UQADD16_GE
UQADD16_LT
UQADD16_GT
UQADD16_LE
UQADD16
UQADD16_ZZ
UQADD8_EQ
UQADD8_NE
UQADD8_CS
UQADD8_CC
UQADD8_MI
UQADD8_PL
UQADD8_VS
UQADD8_VC
UQADD8_HI
UQADD8_LS
UQADD8_GE
UQADD8_LT
UQADD8_GT
UQADD8_LE
UQADD8
UQADD8_ZZ
UQASX_EQ
UQASX_NE
UQASX_CS
UQASX_CC
UQASX_MI
UQASX_PL
UQASX_VS
UQASX_VC
UQASX_HI
UQASX_LS
UQASX_GE
UQASX_LT
UQASX_GT
UQASX_LE
UQASX
UQASX_ZZ
UQSAX_EQ
UQSAX_NE
UQSAX_CS
UQSAX_CC
UQSAX_MI
UQSAX_PL
UQSAX_VS
UQSAX_VC
UQSAX_HI
UQSAX_LS
UQSAX_GE
UQSAX_LT
UQSAX_GT
UQSAX_LE
UQSAX
UQSAX_ZZ
UQSUB16_EQ
UQSUB16_NE
UQSUB16_CS
UQSUB16_CC
UQSUB16_MI
UQSUB16_PL
UQSUB16_VS
UQSUB16_VC
UQSUB16_HI
UQSUB16_LS
UQSUB16_GE
UQSUB16_LT
UQSUB16_GT
UQSUB16_LE
UQSUB16
UQSUB16_ZZ
UQSUB8_EQ
UQSUB8_NE
UQSUB8_CS
UQSUB8_CC
UQSUB8_MI
UQSUB8_PL
UQSUB8_VS
UQSUB8_VC
UQSUB8_HI
UQSUB8_LS
UQSUB8_GE
UQSUB8_LT
UQSUB8_GT
UQSUB8_LE
UQSUB8
UQSUB8_ZZ
USAD8_EQ
USAD8_NE
USAD8_CS
USAD8_CC
USAD8_MI
USAD8_PL
USAD8_VS
USAD8_VC
USAD8_HI
USAD8_LS
USAD8_GE
USAD8_LT
USAD8_GT
USAD8_LE
USAD8
USAD8_ZZ
USADA8_EQ
USADA8_NE
USADA8_CS
USADA8_CC
USADA8_MI
USADA8_PL
USADA8_VS
USADA8_VC
USADA8_HI
USADA8_LS
USADA8_GE
USADA8_LT
USADA8_GT
USADA8_LE
USADA8
USADA8_ZZ
USAT_EQ
USAT_NE
USAT_CS
USAT_CC
USAT_MI
USAT_PL
USAT_VS
USAT_VC
USAT_HI
USAT_LS
USAT_GE
USAT_LT
USAT_GT
USAT_LE
USAT
USAT_ZZ
USAT16_EQ
USAT16_NE
USAT16_CS
USAT16_CC
USAT16_MI
USAT16_PL
USAT16_VS
USAT16_VC
USAT16_HI
USAT16_LS
USAT16_GE
USAT16_LT
USAT16_GT
USAT16_LE
USAT16
USAT16_ZZ
USAX_EQ
USAX_NE
USAX_CS
USAX_CC
USAX_MI
USAX_PL
USAX_VS
USAX_VC
USAX_HI
USAX_LS
USAX_GE
USAX_LT
USAX_GT
USAX_LE
USAX
USAX_ZZ
USUB16_EQ
USUB16_NE
USUB16_CS
USUB16_CC
USUB16_MI
USUB16_PL
USUB16_VS
USUB16_VC
USUB16_HI
USUB16_LS
USUB16_GE
USUB16_LT
USUB16_GT
USUB16_LE
USUB16
USUB16_ZZ
USUB8_EQ
USUB8_NE
USUB8_CS
USUB8_CC
USUB8_MI
USUB8_PL
USUB8_VS
USUB8_VC
USUB8_HI
USUB8_LS
USUB8_GE
USUB8_LT
USUB8_GT
USUB8_LE
USUB8
USUB8_ZZ
UXTAB_EQ
UXTAB_NE
UXTAB_CS
UXTAB_CC
UXTAB_MI
UXTAB_PL
UXTAB_VS
UXTAB_VC
UXTAB_HI
UXTAB_LS
UXTAB_GE
UXTAB_LT
UXTAB_GT
UXTAB_LE
UXTAB
UXTAB_ZZ
UXTAB16_EQ
UXTAB16_NE
UXTAB16_CS
UXTAB16_CC
UXTAB16_MI
UXTAB16_PL
UXTAB16_VS
UXTAB16_VC
UXTAB16_HI
UXTAB16_LS
UXTAB16_GE
UXTAB16_LT
UXTAB16_GT
UXTAB16_LE
UXTAB16
UXTAB16_ZZ
UXTAH_EQ
UXTAH_NE
UXTAH_CS
UXTAH_CC
UXTAH_MI
UXTAH_PL
UXTAH_VS
UXTAH_VC
UXTAH_HI
UXTAH_LS
UXTAH_GE
UXTAH_LT
UXTAH_GT
UXTAH_LE
UXTAH
UXTAH_ZZ
UXTB_EQ
UXTB_NE
UXTB_CS
UXTB_CC
UXTB_MI
UXTB_PL
UXTB_VS
UXTB_VC
UXTB_HI
UXTB_LS
UXTB_GE
UXTB_LT
UXTB_GT
UXTB_LE
UXTB
UXTB_ZZ
UXTB16_EQ
UXTB16_NE
UXTB16_CS
UXTB16_CC
UXTB16_MI
UXTB16_PL
UXTB16_VS
UXTB16_VC
UXTB16_HI
UXTB16_LS
UXTB16_GE
UXTB16_LT
UXTB16_GT
UXTB16_LE
UXTB16
UXTB16_ZZ
UXTH_EQ
UXTH_NE
UXTH_CS
UXTH_CC
UXTH_MI
UXTH_PL
UXTH_VS
UXTH_VC
UXTH_HI
UXTH_LS
UXTH_GE
UXTH_LT
UXTH_GT
UXTH_LE
UXTH
UXTH_ZZ
VABS_EQ_F32
VABS_NE_F32
VABS_CS_F32
VABS_CC_F32
VABS_MI_F32
VABS_PL_F32
VABS_VS_F32
VABS_VC_F32
VABS_HI_F32
VABS_LS_F32
VABS_GE_F32
VABS_LT_F32
VABS_GT_F32
VABS_LE_F32
VABS_F32
VABS_ZZ_F32
VABS_EQ_F64
VABS_NE_F64
VABS_CS_F64
VABS_CC_F64
VABS_MI_F64
VABS_PL_F64
VABS_VS_F64
VABS_VC_F64
VABS_HI_F64
VABS_LS_F64
VABS_GE_F64
VABS_LT_F64
VABS_GT_F64
VABS_LE_F64
VABS_F64
VABS_ZZ_F64
VADD_EQ_F32
VADD_NE_F32
VADD_CS_F32
VADD_CC_F32
VADD_MI_F32
VADD_PL_F32
VADD_VS_F32
VADD_VC_F32
VADD_HI_F32
VADD_LS_F32
VADD_GE_F32
VADD_LT_F32
VADD_GT_F32
VADD_LE_F32
VADD_F32
VADD_ZZ_F32
VADD_EQ_F64
VADD_NE_F64
VADD_CS_F64
VADD_CC_F64
VADD_MI_F64
VADD_PL_F64
VADD_VS_F64
VADD_VC_F64
VADD_HI_F64
VADD_LS_F64
VADD_GE_F64
VADD_LT_F64
VADD_GT_F64
VADD_LE_F64
VADD_F64
VADD_ZZ_F64
VCMP_EQ_F32
VCMP_NE_F32
VCMP_CS_F32
VCMP_CC_F32
VCMP_MI_F32
VCMP_PL_F32
VCMP_VS_F32
VCMP_VC_F32
VCMP_HI_F32
VCMP_LS_F32
VCMP_GE_F32
VCMP_LT_F32
VCMP_GT_F32
VCMP_LE_F32
VCMP_F32
VCMP_ZZ_F32
VCMP_EQ_F64
VCMP_NE_F64
VCMP_CS_F64
VCMP_CC_F64
VCMP_MI_F64
VCMP_PL_F64
VCMP_VS_F64
VCMP_VC_F64
VCMP_HI_F64
VCMP_LS_F64
VCMP_GE_F64
VCMP_LT_F64
VCMP_GT_F64
VCMP_LE_F64
VCMP_F64
VCMP_ZZ_F64
VCMP_E_EQ_F32
VCMP_E_NE_F32
VCMP_E_CS_F32
VCMP_E_CC_F32
VCMP_E_MI_F32
VCMP_E_PL_F32
VCMP_E_VS_F32
VCMP_E_VC_F32
VCMP_E_HI_F32
VCMP_E_LS_F32
VCMP_E_GE_F32
VCMP_E_LT_F32
VCMP_E_GT_F32
VCMP_E_LE_F32
VCMP_E_F32
VCMP_E_ZZ_F32
VCMP_E_EQ_F64
VCMP_E_NE_F64
VCMP_E_CS_F64
VCMP_E_CC_F64
VCMP_E_MI_F64
VCMP_E_PL_F64
VCMP_E_VS_F64
VCMP_E_VC_F64
VCMP_E_HI_F64
VCMP_E_LS_F64
VCMP_E_GE_F64
VCMP_E_LT_F64
VCMP_E_GT_F64
VCMP_E_LE_F64
VCMP_E_F64
VCMP_E_ZZ_F64
VCVT_EQ_F32_FXS16
VCVT_NE_F32_FXS16
VCVT_CS_F32_FXS16
VCVT_CC_F32_FXS16
VCVT_MI_F32_FXS16
VCVT_PL_F32_FXS16
VCVT_VS_F32_FXS16
VCVT_VC_F32_FXS16
VCVT_HI_F32_FXS16
VCVT_LS_F32_FXS16
VCVT_GE_F32_FXS16
VCVT_LT_F32_FXS16
VCVT_GT_F32_FXS16
VCVT_LE_F32_FXS16
VCVT_F32_FXS16
VCVT_ZZ_F32_FXS16
VCVT_EQ_F32_FXS32
VCVT_NE_F32_FXS32
VCVT_CS_F32_FXS32
VCVT_CC_F32_FXS32
VCVT_MI_F32_FXS32
VCVT_PL_F32_FXS32
VCVT_VS_F32_FXS32
VCVT_VC_F32_FXS32
VCVT_HI_F32_FXS32
VCVT_LS_F32_FXS32
VCVT_GE_F32_FXS32
VCVT_LT_F32_FXS32
VCVT_GT_F32_FXS32
VCVT_LE_F32_FXS32
VCVT_F32_FXS32
VCVT_ZZ_F32_FXS32
VCVT_EQ_F32_FXU16
VCVT_NE_F32_FXU16
VCVT_CS_F32_FXU16
VCVT_CC_F32_FXU16
VCVT_MI_F32_FXU16
VCVT_PL_F32_FXU16
VCVT_VS_F32_FXU16
VCVT_VC_F32_FXU16
VCVT_HI_F32_FXU16
VCVT_LS_F32_FXU16
VCVT_GE_F32_FXU16
VCVT_LT_F32_FXU16
VCVT_GT_F32_FXU16
VCVT_LE_F32_FXU16
VCVT_F32_FXU16
VCVT_ZZ_F32_FXU16
VCVT_EQ_F32_FXU32
VCVT_NE_F32_FXU32
VCVT_CS_F32_FXU32
VCVT_CC_F32_FXU32
VCVT_MI_F32_FXU32
VCVT_PL_F32_FXU32
VCVT_VS_F32_FXU32
VCVT_VC_F32_FXU32
VCVT_HI_F32_FXU32
VCVT_LS_F32_FXU32
VCVT_GE_F32_FXU32
VCVT_LT_F32_FXU32
VCVT_GT_F32_FXU32
VCVT_LE_F32_FXU32
VCVT_F32_FXU32
VCVT_ZZ_F32_FXU32
VCVT_EQ_F64_FXS16
VCVT_NE_F64_FXS16
VCVT_CS_F64_FXS16
VCVT_CC_F64_FXS16
VCVT_MI_F64_FXS16
VCVT_PL_F64_FXS16
VCVT_VS_F64_FXS16
VCVT_VC_F64_FXS16
VCVT_HI_F64_FXS16
VCVT_LS_F64_FXS16
VCVT_GE_F64_FXS16
VCVT_LT_F64_FXS16
VCVT_GT_F64_FXS16
VCVT_LE_F64_FXS16
VCVT_F64_FXS16
VCVT_ZZ_F64_FXS16
VCVT_EQ_F64_FXS32
VCVT_NE_F64_FXS32
VCVT_CS_F64_FXS32
VCVT_CC_F64_FXS32
VCVT_MI_F64_FXS32
VCVT_PL_F64_FXS32
VCVT_VS_F64_FXS32
VCVT_VC_F64_FXS32
VCVT_HI_F64_FXS32
VCVT_LS_F64_FXS32
VCVT_GE_F64_FXS32
VCVT_LT_F64_FXS32
VCVT_GT_F64_FXS32
VCVT_LE_F64_FXS32
VCVT_F64_FXS32
VCVT_ZZ_F64_FXS32
VCVT_EQ_F64_FXU16
VCVT_NE_F64_FXU16
VCVT_CS_F64_FXU16
VCVT_CC_F64_FXU16
VCVT_MI_F64_FXU16
VCVT_PL_F64_FXU16
VCVT_VS_F64_FXU16
VCVT_VC_F64_FXU16
VCVT_HI_F64_FXU16
VCVT_LS_F64_FXU16
VCVT_GE_F64_FXU16
VCVT_LT_F64_FXU16
VCVT_GT_F64_FXU16
VCVT_LE_F64_FXU16
VCVT_F64_FXU16
VCVT_ZZ_F64_FXU16
VCVT_EQ_F64_FXU32
VCVT_NE_F64_FXU32
VCVT_CS_F64_FXU32
VCVT_CC_F64_FXU32
VCVT_MI_F64_FXU32
VCVT_PL_F64_FXU32
VCVT_VS_F64_FXU32
VCVT_VC_F64_FXU32
VCVT_HI_F64_FXU32
VCVT_LS_F64_FXU32
VCVT_GE_F64_FXU32
VCVT_LT_F64_FXU32
VCVT_GT_F64_FXU32
VCVT_LE_F64_FXU32
VCVT_F64_FXU32
VCVT_ZZ_F64_FXU32
VCVT_EQ_F32_U32
VCVT_NE_F32_U32
VCVT_CS_F32_U32
VCVT_CC_F32_U32
VCVT_MI_F32_U32
VCVT_PL_F32_U32
VCVT_VS_F32_U32
VCVT_VC_F32_U32
VCVT_HI_F32_U32
VCVT_LS_F32_U32
VCVT_GE_F32_U32
VCVT_LT_F32_U32
VCVT_GT_F32_U32
VCVT_LE_F32_U32
VCVT_F32_U32
VCVT_ZZ_F32_U32
VCVT_EQ_F32_S32
VCVT_NE_F32_S32
VCVT_CS_F32_S32
VCVT_CC_F32_S32
VCVT_MI_F32_S32
VCVT_PL_F32_S32
VCVT_VS_F32_S32
VCVT_VC_F32_S32
VCVT_HI_F32_S32
VCVT_LS_F32_S32
VCVT_GE_F32_S32
VCVT_LT_F32_S32
VCVT_GT_F32_S32
VCVT_LE_F32_S32
VCVT_F32_S32
VCVT_ZZ_F32_S32
VCVT_EQ_F64_U32
VCVT_NE_F64_U32
VCVT_CS_F64_U32
VCVT_CC_F64_U32
VCVT_MI_F64_U32
VCVT_PL_F64_U32
VCVT_VS_F64_U32
VCVT_VC_F64_U32
VCVT_HI_F64_U32
VCVT_LS_F64_U32
VCVT_GE_F64_U32
VCVT_LT_F64_U32
VCVT_GT_F64_U32
VCVT_LE_F64_U32
VCVT_F64_U32
VCVT_ZZ_F64_U32
VCVT_EQ_F64_S32
VCVT_NE_F64_S32
VCVT_CS_F64_S32
VCVT_CC_F64_S32
VCVT_MI_F64_S32
VCVT_PL_F64_S32
VCVT_VS_F64_S32
VCVT_VC_F64_S32
VCVT_HI_F64_S32
VCVT_LS_F64_S32
VCVT_GE_F64_S32
VCVT_LT_F64_S32
VCVT_GT_F64_S32
VCVT_LE_F64_S32
VCVT_F64_S32
VCVT_ZZ_F64_S32
VCVT_EQ_F64_F32
VCVT_NE_F64_F32
VCVT_CS_F64_F32
VCVT_CC_F64_F32
VCVT_MI_F64_F32
VCVT_PL_F64_F32
VCVT_VS_F64_F32
VCVT_VC_F64_F32
VCVT_HI_F64_F32
VCVT_LS_F64_F32
VCVT_GE_F64_F32
VCVT_LT_F64_F32
VCVT_GT_F64_F32
VCVT_LE_F64_F32
VCVT_F64_F32
VCVT_ZZ_F64_F32
VCVT_EQ_F32_F64
VCVT_NE_F32_F64
VCVT_CS_F32_F64
VCVT_CC_F32_F64
VCVT_MI_F32_F64
VCVT_PL_F32_F64
VCVT_VS_F32_F64
VCVT_VC_F32_F64
VCVT_HI_F32_F64
VCVT_LS_F32_F64
VCVT_GE_F32_F64
VCVT_LT_F32_F64
VCVT_GT_F32_F64
VCVT_LE_F32_F64
VCVT_F32_F64
VCVT_ZZ_F32_F64
VCVT_EQ_FXS16_F32
VCVT_NE_FXS16_F32
VCVT_CS_FXS16_F32
VCVT_CC_FXS16_F32
VCVT_MI_FXS16_F32
VCVT_PL_FXS16_F32
VCVT_VS_FXS16_F32
VCVT_VC_FXS16_F32
VCVT_HI_FXS16_F32
VCVT_LS_FXS16_F32
VCVT_GE_FXS16_F32
VCVT_LT_FXS16_F32
VCVT_GT_FXS16_F32
VCVT_LE_FXS16_F32
VCVT_FXS16_F32
VCVT_ZZ_FXS16_F32
VCVT_EQ_FXS16_F64
VCVT_NE_FXS16_F64
VCVT_CS_FXS16_F64
VCVT_CC_FXS16_F64
VCVT_MI_FXS16_F64
VCVT_PL_FXS16_F64
VCVT_VS_FXS16_F64
VCVT_VC_FXS16_F64
VCVT_HI_FXS16_F64
VCVT_LS_FXS16_F64
VCVT_GE_FXS16_F64
VCVT_LT_FXS16_F64
VCVT_GT_FXS16_F64
VCVT_LE_FXS16_F64
VCVT_FXS16_F64
VCVT_ZZ_FXS16_F64
VCVT_EQ_FXS32_F32
VCVT_NE_FXS32_F32
VCVT_CS_FXS32_F32
VCVT_CC_FXS32_F32
VCVT_MI_FXS32_F32
VCVT_PL_FXS32_F32
VCVT_VS_FXS32_F32
VCVT_VC_FXS32_F32
VCVT_HI_FXS32_F32
VCVT_LS_FXS32_F32
VCVT_GE_FXS32_F32
VCVT_LT_FXS32_F32
VCVT_GT_FXS32_F32
VCVT_LE_FXS32_F32
VCVT_FXS32_F32
VCVT_ZZ_FXS32_F32
VCVT_EQ_FXS32_F64
VCVT_NE_FXS32_F64
VCVT_CS_FXS32_F64
VCVT_CC_FXS32_F64
VCVT_MI_FXS32_F64
VCVT_PL_FXS32_F64
VCVT_VS_FXS32_F64
VCVT_VC_FXS32_F64
VCVT_HI_FXS32_F64
VCVT_LS_FXS32_F64
VCVT_GE_FXS32_F64
VCVT_LT_FXS32_F64
VCVT_GT_FXS32_F64
VCVT_LE_FXS32_F64
VCVT_FXS32_F64
VCVT_ZZ_FXS32_F64
VCVT_EQ_FXU16_F32
VCVT_NE_FXU16_F32
VCVT_CS_FXU16_F32
VCVT_CC_FXU16_F32
VCVT_MI_FXU16_F32
VCVT_PL_FXU16_F32
VCVT_VS_FXU16_F32
VCVT_VC_FXU16_F32
VCVT_HI_FXU16_F32
VCVT_LS_FXU16_F32
VCVT_GE_FXU16_F32
VCVT_LT_FXU16_F32
VCVT_GT_FXU16_F32
VCVT_LE_FXU16_F32
VCVT_FXU16_F32
VCVT_ZZ_FXU16_F32
VCVT_EQ_FXU16_F64
VCVT_NE_FXU16_F64
VCVT_CS_FXU16_F64
VCVT_CC_FXU16_F64
VCVT_MI_FXU16_F64
VCVT_PL_FXU16_F64
VCVT_VS_FXU16_F64
VCVT_VC_FXU16_F64
VCVT_HI_FXU16_F64
VCVT_LS_FXU16_F64
VCVT_GE_FXU16_F64
VCVT_LT_FXU16_F64
VCVT_GT_FXU16_F64
VCVT_LE_FXU16_F64
VCVT_FXU16_F64
VCVT_ZZ_FXU16_F64
VCVT_EQ_FXU32_F32
VCVT_NE_FXU32_F32
VCVT_CS_FXU32_F32
VCVT_CC_FXU32_F32
VCVT_MI_FXU32_F32
VCVT_PL_FXU32_F32
VCVT_VS_FXU32_F32
VCVT_VC_FXU32_F32
VCVT_HI_FXU32_F32
VCVT_LS_FXU32_F32
VCVT_GE_FXU32_F32
VCVT_LT_FXU32_F32
VCVT_GT_FXU32_F32
VCVT_LE_FXU32_F32
VCVT_FXU32_F32
VCVT_ZZ_FXU32_F32
VCVT_EQ_FXU32_F64
VCVT_NE_FXU32_F64
VCVT_CS_FXU32_F64
VCVT_CC_FXU32_F64
VCVT_MI_FXU32_F64
VCVT_PL_FXU32_F64
VCVT_VS_FXU32_F64
VCVT_VC_FXU32_F64
VCVT_HI_FXU32_F64
VCVT_LS_FXU32_F64
VCVT_GE_FXU32_F64
VCVT_LT_FXU32_F64
VCVT_GT_FXU32_F64
VCVT_LE_FXU32_F64
VCVT_FXU32_F64
VCVT_ZZ_FXU32_F64
VCVTB_EQ_F32_F16
VCVTB_NE_F32_F16
VCVTB_CS_F32_F16
VCVTB_CC_F32_F16
VCVTB_MI_F32_F16
VCVTB_PL_F32_F16
VCVTB_VS_F32_F16
VCVTB_VC_F32_F16
VCVTB_HI_F32_F16
VCVTB_LS_F32_F16
VCVTB_GE_F32_F16
VCVTB_LT_F32_F16
VCVTB_GT_F32_F16
VCVTB_LE_F32_F16
VCVTB_F32_F16
VCVTB_ZZ_F32_F16
VCVTB_EQ_F16_F32
VCVTB_NE_F16_F32
VCVTB_CS_F16_F32
VCVTB_CC_F16_F32
VCVTB_MI_F16_F32
VCVTB_PL_F16_F32
VCVTB_VS_F16_F32
VCVTB_VC_F16_F32
VCVTB_HI_F16_F32
VCVTB_LS_F16_F32
VCVTB_GE_F16_F32
VCVTB_LT_F16_F32
VCVTB_GT_F16_F32
VCVTB_LE_F16_F32
VCVTB_F16_F32
VCVTB_ZZ_F16_F32
VCVTT_EQ_F32_F16
VCVTT_NE_F32_F16
VCVTT_CS_F32_F16
VCVTT_CC_F32_F16
VCVTT_MI_F32_F16
VCVTT_PL_F32_F16
VCVTT_VS_F32_F16
VCVTT_VC_F32_F16
VCVTT_HI_F32_F16
VCVTT_LS_F32_F16
VCVTT_GE_F32_F16
VCVTT_LT_F32_F16
VCVTT_GT_F32_F16
VCVTT_LE_F32_F16
VCVTT_F32_F16
VCVTT_ZZ_F32_F16
VCVTT_EQ_F16_F32
VCVTT_NE_F16_F32
VCVTT_CS_F16_F32
VCVTT_CC_F16_F32
VCVTT_MI_F16_F32
VCVTT_PL_F16_F32
VCVTT_VS_F16_F32
VCVTT_VC_F16_F32
VCVTT_HI_F16_F32
VCVTT_LS_F16_F32
VCVTT_GE_F16_F32
VCVTT_LT_F16_F32
VCVTT_GT_F16_F32
VCVTT_LE_F16_F32
VCVTT_F16_F32
VCVTT_ZZ_F16_F32
VCVTR_EQ_U32_F32
VCVTR_NE_U32_F32
VCVTR_CS_U32_F32
VCVTR_CC_U32_F32
VCVTR_MI_U32_F32
VCVTR_PL_U32_F32
VCVTR_VS_U32_F32
VCVTR_VC_U32_F32
VCVTR_HI_U32_F32
VCVTR_LS_U32_F32
VCVTR_GE_U32_F32
VCVTR_LT_U32_F32
VCVTR_GT_U32_F32
VCVTR_LE_U32_F32
VCVTR_U32_F32
VCVTR_ZZ_U32_F32
VCVTR_EQ_U32_F64
VCVTR_NE_U32_F64
VCVTR_CS_U32_F64
VCVTR_CC_U32_F64
VCVTR_MI_U32_F64
VCVTR_PL_U32_F64
VCVTR_VS_U32_F64
VCVTR_VC_U32_F64
VCVTR_HI_U32_F64
VCVTR_LS_U32_F64
VCVTR_GE_U32_F64
VCVTR_LT_U32_F64
VCVTR_GT_U32_F64
VCVTR_LE_U32_F64
VCVTR_U32_F64
VCVTR_ZZ_U32_F64
VCVTR_EQ_S32_F32
VCVTR_NE_S32_F32
VCVTR_CS_S32_F32
VCVTR_CC_S32_F32
VCVTR_MI_S32_F32
VCVTR_PL_S32_F32
VCVTR_VS_S32_F32
VCVTR_VC_S32_F32
VCVTR_HI_S32_F32
VCVTR_LS_S32_F32
VCVTR_GE_S32_F32
VCVTR_LT_S32_F32
VCVTR_GT_S32_F32
VCVTR_LE_S32_F32
VCVTR_S32_F32
VCVTR_ZZ_S32_F32
VCVTR_EQ_S32_F64
VCVTR_NE_S32_F64
VCVTR_CS_S32_F64
VCVTR_CC_S32_F64
VCVTR_MI_S32_F64
VCVTR_PL_S32_F64
VCVTR_VS_S32_F64
VCVTR_VC_S32_F64
VCVTR_HI_S32_F64
VCVTR_LS_S32_F64
VCVTR_GE_S32_F64
VCVTR_LT_S32_F64
VCVTR_GT_S32_F64
VCVTR_LE_S32_F64
VCVTR_S32_F64
VCVTR_ZZ_S32_F64
VCVT_EQ_U32_F32
VCVT_NE_U32_F32
VCVT_CS_U32_F32
VCVT_CC_U32_F32
VCVT_MI_U32_F32
VCVT_PL_U32_F32
VCVT_VS_U32_F32
VCVT_VC_U32_F32
VCVT_HI_U32_F32
VCVT_LS_U32_F32
VCVT_GE_U32_F32
VCVT_LT_U32_F32
VCVT_GT_U32_F32
VCVT_LE_U32_F32
VCVT_U32_F32
VCVT_ZZ_U32_F32
VCVT_EQ_U32_F64
VCVT_NE_U32_F64
VCVT_CS_U32_F64
VCVT_CC_U32_F64
VCVT_MI_U32_F64
VCVT_PL_U32_F64
VCVT_VS_U32_F64
VCVT_VC_U32_F64
VCVT_HI_U32_F64
VCVT_LS_U32_F64
VCVT_GE_U32_F64
VCVT_LT_U32_F64
VCVT_GT_U32_F64
VCVT_LE_U32_F64
VCVT_U32_F64
VCVT_ZZ_U32_F64
VCVT_EQ_S32_F32
VCVT_NE_S32_F32
VCVT_CS_S32_F32
VCVT_CC_S32_F32
VCVT_MI_S32_F32
VCVT_PL_S32_F32
VCVT_VS_S32_F32
VCVT_VC_S32_F32
VCVT_HI_S32_F32
VCVT_LS_S32_F32
VCVT_GE_S32_F32
VCVT_LT_S32_F32
VCVT_GT_S32_F32
VCVT_LE_S32_F32
VCVT_S32_F32
VCVT_ZZ_S32_F32
VCVT_EQ_S32_F64
VCVT_NE_S32_F64
VCVT_CS_S32_F64
VCVT_CC_S32_F64
VCVT_MI_S32_F64
VCVT_PL_S32_F64
VCVT_VS_S32_F64
VCVT_VC_S32_F64
VCVT_HI_S32_F64
VCVT_LS_S32_F64
VCVT_GE_S32_F64
VCVT_LT_S32_F64
VCVT_GT_S32_F64
VCVT_LE_S32_F64
VCVT_S32_F64
VCVT_ZZ_S32_F64
VDIV_EQ_F32
VDIV_NE_F32
VDIV_CS_F32
VDIV_CC_F32
VDIV_MI_F32
VDIV_PL_F32
VDIV_VS_F32
VDIV_VC_F32
VDIV_HI_F32
VDIV_LS_F32
VDIV_GE_F32
VDIV_LT_F32
VDIV_GT_F32
VDIV_LE_F32
VDIV_F32
VDIV_ZZ_F32
VDIV_EQ_F64
VDIV_NE_F64
VDIV_CS_F64
VDIV_CC_F64
VDIV_MI_F64
VDIV_PL_F64
VDIV_VS_F64
VDIV_VC_F64
VDIV_HI_F64
VDIV_LS_F64
VDIV_GE_F64
VDIV_LT_F64
VDIV_GT_F64
VDIV_LE_F64
VDIV_F64
VDIV_ZZ_F64
VLDR_EQ
VLDR_NE
VLDR_CS
VLDR_CC
VLDR_MI
VLDR_PL
VLDR_VS
VLDR_VC
VLDR_HI
VLDR_LS
VLDR_GE
VLDR_LT
VLDR_GT
VLDR_LE
VLDR
VLDR_ZZ
VMLA_EQ_F32
VMLA_NE_F32
VMLA_CS_F32
VMLA_CC_F32
VMLA_MI_F32
VMLA_PL_F32
VMLA_VS_F32
VMLA_VC_F32
VMLA_HI_F32
VMLA_LS_F32
VMLA_GE_F32
VMLA_LT_F32
VMLA_GT_F32
VMLA_LE_F32
VMLA_F32
VMLA_ZZ_F32
VMLA_EQ_F64
VMLA_NE_F64
VMLA_CS_F64
VMLA_CC_F64
VMLA_MI_F64
VMLA_PL_F64
VMLA_VS_F64
VMLA_VC_F64
VMLA_HI_F64
VMLA_LS_F64
VMLA_GE_F64
VMLA_LT_F64
VMLA_GT_F64
VMLA_LE_F64
VMLA_F64
VMLA_ZZ_F64
VMLS_EQ_F32
VMLS_NE_F32
VMLS_CS_F32
VMLS_CC_F32
VMLS_MI_F32
VMLS_PL_F32
VMLS_VS_F32
VMLS_VC_F32
VMLS_HI_F32
VMLS_LS_F32
VMLS_GE_F32
VMLS_LT_F32
VMLS_GT_F32
VMLS_LE_F32
VMLS_F32
VMLS_ZZ_F32
VMLS_EQ_F64
VMLS_NE_F64
VMLS_CS_F64
VMLS_CC_F64
VMLS_MI_F64
VMLS_PL_F64
VMLS_VS_F64
VMLS_VC_F64
VMLS_HI_F64
VMLS_LS_F64
VMLS_GE_F64
VMLS_LT_F64
VMLS_GT_F64
VMLS_LE_F64
VMLS_F64
VMLS_ZZ_F64
VMOV_EQ
VMOV_NE
VMOV_CS
VMOV_CC
VMOV_MI
VMOV_PL
VMOV_VS
VMOV_VC
VMOV_HI
VMOV_LS
VMOV_GE
VMOV_LT
VMOV_GT
VMOV_LE
VMOV
VMOV_ZZ
VMOV_EQ_32
VMOV_NE_32
VMOV_CS_32
VMOV_CC_32
VMOV_MI_32
VMOV_PL_32
VMOV_VS_32
VMOV_VC_32
VMOV_HI_32
VMOV_LS_32
VMOV_GE_32
VMOV_LT_32
VMOV_GT_32
VMOV_LE_32
VMOV_32
VMOV_ZZ_32
VMOV_EQ_F32
VMOV_NE_F32
VMOV_CS_F32
VMOV_CC_F32
VMOV_MI_F32
VMOV_PL_F32
VMOV_VS_F32
VMOV_VC_F32
VMOV_HI_F32
VMOV_LS_F32
VMOV_GE_F32
VMOV_LT_F32
VMOV_GT_F32
VMOV_LE_F32
VMOV_F32
VMOV_ZZ_F32
VMOV_EQ_F64
VMOV_NE_F64
VMOV_CS_F64
VMOV_CC_F64
VMOV_MI_F64
VMOV_PL_F64
VMOV_VS_F64
VMOV_VC_F64
VMOV_HI_F64
VMOV_LS_F64
VMOV_GE_F64
VMOV_LT_F64
VMOV_GT_F64
VMOV_LE_F64
VMOV_F64
VMOV_ZZ_F64
VMRS_EQ
VMRS_NE
VMRS_CS
VMRS_CC
VMRS_MI
VMRS_PL
VMRS_VS
VMRS_VC
VMRS_HI
VMRS_LS
VMRS_GE
VMRS_LT
VMRS_GT
VMRS_LE
VMRS
VMRS_ZZ
VMSR_EQ
VMSR_NE
VMSR_CS
VMSR_CC
VMSR_MI
VMSR_PL
VMSR_VS
VMSR_VC
VMSR_HI
VMSR_LS
VMSR_GE
VMSR_LT
VMSR_GT
VMSR_LE
VMSR
VMSR_ZZ
VMUL_EQ_F32
VMUL_NE_F32
VMUL_CS_F32
VMUL_CC_F32
VMUL_MI_F32
VMUL_PL_F32
VMUL_VS_F32
VMUL_VC_F32
VMUL_HI_F32
VMUL_LS_F32
VMUL_GE_F32
VMUL_LT_F32
VMUL_GT_F32
VMUL_LE_F32
VMUL_F32
VMUL_ZZ_F32
VMUL_EQ_F64
VMUL_NE_F64
VMUL_CS_F64
VMUL_CC_F64
VMUL_MI_F64
VMUL_PL_F64
VMUL_VS_F64
VMUL_VC_F64
VMUL_HI_F64
VMUL_LS_F64
VMUL_GE_F64
VMUL_LT_F64
VMUL_GT_F64
VMUL_LE_F64
VMUL_F64
VMUL_ZZ_F64
VNEG_EQ_F32
VNEG_NE_F32
VNEG_CS_F32
VNEG_CC_F32
VNEG_MI_F32
VNEG_PL_F32
VNEG_VS_F32
VNEG_VC_F32
VNEG_HI_F32
VNEG_LS_F32
VNEG_GE_F32
VNEG_LT_F32
VNEG_GT_F32
VNEG_LE_F32
VNEG_F32
VNEG_ZZ_F32
VNEG_EQ_F64
VNEG_NE_F64
VNEG_CS_F64
VNEG_CC_F64
VNEG_MI_F64
VNEG_PL_F64
VNEG_VS_F64
VNEG_VC_F64
VNEG_HI_F64
VNEG_LS_F64
VNEG_GE_F64
VNEG_LT_F64
VNEG_GT_F64
VNEG_LE_F64
VNEG_F64
VNEG_ZZ_F64
VNMLS_EQ_F32
VNMLS_NE_F32
VNMLS_CS_F32
VNMLS_CC_F32
VNMLS_MI_F32
VNMLS_PL_F32
VNMLS_VS_F32
VNMLS_VC_F32
VNMLS_HI_F32
VNMLS_LS_F32
VNMLS_GE_F32
VNMLS_LT_F32
VNMLS_GT_F32
VNMLS_LE_F32
VNMLS_F32
VNMLS_ZZ_F32
VNMLS_EQ_F64
VNMLS_NE_F64
VNMLS_CS_F64
VNMLS_CC_F64
VNMLS_MI_F64
VNMLS_PL_F64
VNMLS_VS_F64
VNMLS_VC_F64
VNMLS_HI_F64
VNMLS_LS_F64
VNMLS_GE_F64
VNMLS_LT_F64
VNMLS_GT_F64
VNMLS_LE_F64
VNMLS_F64
VNMLS_ZZ_F64
VNMLA_EQ_F32
VNMLA_NE_F32
VNMLA_CS_F32
VNMLA_CC_F32
VNMLA_MI_F32
VNMLA_PL_F32
VNMLA_VS_F32
VNMLA_VC_F32
VNMLA_HI_F32
VNMLA_LS_F32
VNMLA_GE_F32
VNMLA_LT_F32
VNMLA_GT_F32
VNMLA_LE_F32
VNMLA_F32
VNMLA_ZZ_F32
VNMLA_EQ_F64
VNMLA_NE_F64
VNMLA_CS_F64
VNMLA_CC_F64
VNMLA_MI_F64
VNMLA_PL_F64
VNMLA_VS_F64
VNMLA_VC_F64
VNMLA_HI_F64
VNMLA_LS_F64
VNMLA_GE_F64
VNMLA_LT_F64
VNMLA_GT_F64
VNMLA_LE_F64
VNMLA_F64
VNMLA_ZZ_F64
VNMUL_EQ_F32
VNMUL_NE_F32
VNMUL_CS_F32
VNMUL_CC_F32
VNMUL_MI_F32
VNMUL_PL_F32
VNMUL_VS_F32
VNMUL_VC_F32
VNMUL_HI_F32
VNMUL_LS_F32
VNMUL_GE_F32
VNMUL_LT_F32
VNMUL_GT_F32
VNMUL_LE_F32
VNMUL_F32
VNMUL_ZZ_F32
VNMUL_EQ_F64
VNMUL_NE_F64
VNMUL_CS_F64
VNMUL_CC_F64
VNMUL_MI_F64
VNMUL_PL_F64
VNMUL_VS_F64
VNMUL_VC_F64
VNMUL_HI_F64
VNMUL_LS_F64
VNMUL_GE_F64
VNMUL_LT_F64
VNMUL_GT_F64
VNMUL_LE_F64
VNMUL_F64
VNMUL_ZZ_F64
VSQRT_EQ_F32
VSQRT_NE_F32
VSQRT_CS_F32
VSQRT_CC_F32
VSQRT_MI_F32
VSQRT_PL_F32
VSQRT_VS_F32
VSQRT_VC_F32
VSQRT_HI_F32
VSQRT_LS_F32
VSQRT_GE_F32
VSQRT_LT_F32
VSQRT_GT_F32
VSQRT_LE_F32
VSQRT_F32
VSQRT_ZZ_F32
VSQRT_EQ_F64
VSQRT_NE_F64
VSQRT_CS_F64
VSQRT_CC_F64
VSQRT_MI_F64
VSQRT_PL_F64
VSQRT_VS_F64
VSQRT_VC_F64
VSQRT_HI_F64
VSQRT_LS_F64
VSQRT_GE_F64
VSQRT_LT_F64
VSQRT_GT_F64
VSQRT_LE_F64
VSQRT_F64
VSQRT_ZZ_F64
VSTR_EQ
VSTR_NE
VSTR_CS
VSTR_CC
VSTR_MI
VSTR_PL
VSTR_VS
VSTR_VC
VSTR_HI
VSTR_LS
VSTR_GE
VSTR_LT
VSTR_GT
VSTR_LE
VSTR
VSTR_ZZ
VSUB_EQ_F32
VSUB_NE_F32
VSUB_CS_F32
VSUB_CC_F32
VSUB_MI_F32
VSUB_PL_F32
VSUB_VS_F32
VSUB_VC_F32
VSUB_HI_F32
VSUB_LS_F32
VSUB_GE_F32
VSUB_LT_F32
VSUB_GT_F32
VSUB_LE_F32
VSUB_F32
VSUB_ZZ_F32
VSUB_EQ_F64
VSUB_NE_F64
VSUB_CS_F64
VSUB_CC_F64
VSUB_MI_F64
VSUB_PL_F64
VSUB_VS_F64
VSUB_VC_F64
VSUB_HI_F64
VSUB_LS_F64
VSUB_GE_F64
VSUB_LT_F64
VSUB_GT_F64
VSUB_LE_F64
VSUB_F64
VSUB_ZZ_F64
WFE_EQ
WFE_NE
WFE_CS
WFE_CC
WFE_MI
WFE_PL
WFE_VS
WFE_VC
WFE_HI
WFE_LS
WFE_GE
WFE_LT
WFE_GT
WFE_LE
WFE
WFE_ZZ
WFI_EQ
WFI_NE
WFI_CS
WFI_CC
WFI_MI
WFI_PL
WFI_VS
WFI_VC
WFI_HI
WFI_LS
WFI_GE
WFI_LT
WFI_GT
WFI_LE
WFI
WFI_ZZ
YIELD_EQ
YIELD_NE
YIELD_CS
YIELD_CC
YIELD_MI
YIELD_PL
YIELD_VS
YIELD_VC
YIELD_HI
YIELD_LS
YIELD_GE
YIELD_LT
YIELD_GT
YIELD_LE
YIELD
YIELD_ZZ
)
var opstr = [...]string{
ADC_EQ: "ADC.EQ",
ADC_NE: "ADC.NE",
ADC_CS: "ADC.CS",
ADC_CC: "ADC.CC",
ADC_MI: "ADC.MI",
ADC_PL: "ADC.PL",
ADC_VS: "ADC.VS",
ADC_VC: "ADC.VC",
ADC_HI: "ADC.HI",
ADC_LS: "ADC.LS",
ADC_GE: "ADC.GE",
ADC_LT: "ADC.LT",
ADC_GT: "ADC.GT",
ADC_LE: "ADC.LE",
ADC: "ADC",
ADC_ZZ: "ADC.ZZ",
ADC_S_EQ: "ADC.S.EQ",
ADC_S_NE: "ADC.S.NE",
ADC_S_CS: "ADC.S.CS",
ADC_S_CC: "ADC.S.CC",
ADC_S_MI: "ADC.S.MI",
ADC_S_PL: "ADC.S.PL",
ADC_S_VS: "ADC.S.VS",
ADC_S_VC: "ADC.S.VC",
ADC_S_HI: "ADC.S.HI",
ADC_S_LS: "ADC.S.LS",
ADC_S_GE: "ADC.S.GE",
ADC_S_LT: "ADC.S.LT",
ADC_S_GT: "ADC.S.GT",
ADC_S_LE: "ADC.S.LE",
ADC_S: "ADC.S",
ADC_S_ZZ: "ADC.S.ZZ",
ADD_EQ: "ADD.EQ",
ADD_NE: "ADD.NE",
ADD_CS: "ADD.CS",
ADD_CC: "ADD.CC",
ADD_MI: "ADD.MI",
ADD_PL: "ADD.PL",
ADD_VS: "ADD.VS",
ADD_VC: "ADD.VC",
ADD_HI: "ADD.HI",
ADD_LS: "ADD.LS",
ADD_GE: "ADD.GE",
ADD_LT: "ADD.LT",
ADD_GT: "ADD.GT",
ADD_LE: "ADD.LE",
ADD: "ADD",
ADD_ZZ: "ADD.ZZ",
ADD_S_EQ: "ADD.S.EQ",
ADD_S_NE: "ADD.S.NE",
ADD_S_CS: "ADD.S.CS",
ADD_S_CC: "ADD.S.CC",
ADD_S_MI: "ADD.S.MI",
ADD_S_PL: "ADD.S.PL",
ADD_S_VS: "ADD.S.VS",
ADD_S_VC: "ADD.S.VC",
ADD_S_HI: "ADD.S.HI",
ADD_S_LS: "ADD.S.LS",
ADD_S_GE: "ADD.S.GE",
ADD_S_LT: "ADD.S.LT",
ADD_S_GT: "ADD.S.GT",
ADD_S_LE: "ADD.S.LE",
ADD_S: "ADD.S",
ADD_S_ZZ: "ADD.S.ZZ",
AND_EQ: "AND.EQ",
AND_NE: "AND.NE",
AND_CS: "AND.CS",
AND_CC: "AND.CC",
AND_MI: "AND.MI",
AND_PL: "AND.PL",
AND_VS: "AND.VS",
AND_VC: "AND.VC",
AND_HI: "AND.HI",
AND_LS: "AND.LS",
AND_GE: "AND.GE",
AND_LT: "AND.LT",
AND_GT: "AND.GT",
AND_LE: "AND.LE",
AND: "AND",
AND_ZZ: "AND.ZZ",
AND_S_EQ: "AND.S.EQ",
AND_S_NE: "AND.S.NE",
AND_S_CS: "AND.S.CS",
AND_S_CC: "AND.S.CC",
AND_S_MI: "AND.S.MI",
AND_S_PL: "AND.S.PL",
AND_S_VS: "AND.S.VS",
AND_S_VC: "AND.S.VC",
AND_S_HI: "AND.S.HI",
AND_S_LS: "AND.S.LS",
AND_S_GE: "AND.S.GE",
AND_S_LT: "AND.S.LT",
AND_S_GT: "AND.S.GT",
AND_S_LE: "AND.S.LE",
AND_S: "AND.S",
AND_S_ZZ: "AND.S.ZZ",
ASR_EQ: "ASR.EQ",
ASR_NE: "ASR.NE",
ASR_CS: "ASR.CS",
ASR_CC: "ASR.CC",
ASR_MI: "ASR.MI",
ASR_PL: "ASR.PL",
ASR_VS: "ASR.VS",
ASR_VC: "ASR.VC",
ASR_HI: "ASR.HI",
ASR_LS: "ASR.LS",
ASR_GE: "ASR.GE",
ASR_LT: "ASR.LT",
ASR_GT: "ASR.GT",
ASR_LE: "ASR.LE",
ASR: "ASR",
ASR_ZZ: "ASR.ZZ",
ASR_S_EQ: "ASR.S.EQ",
ASR_S_NE: "ASR.S.NE",
ASR_S_CS: "ASR.S.CS",
ASR_S_CC: "ASR.S.CC",
ASR_S_MI: "ASR.S.MI",
ASR_S_PL: "ASR.S.PL",
ASR_S_VS: "ASR.S.VS",
ASR_S_VC: "ASR.S.VC",
ASR_S_HI: "ASR.S.HI",
ASR_S_LS: "ASR.S.LS",
ASR_S_GE: "ASR.S.GE",
ASR_S_LT: "ASR.S.LT",
ASR_S_GT: "ASR.S.GT",
ASR_S_LE: "ASR.S.LE",
ASR_S: "ASR.S",
ASR_S_ZZ: "ASR.S.ZZ",
B_EQ: "B.EQ",
B_NE: "B.NE",
B_CS: "B.CS",
B_CC: "B.CC",
B_MI: "B.MI",
B_PL: "B.PL",
B_VS: "B.VS",
B_VC: "B.VC",
B_HI: "B.HI",
B_LS: "B.LS",
B_GE: "B.GE",
B_LT: "B.LT",
B_GT: "B.GT",
B_LE: "B.LE",
B: "B",
B_ZZ: "B.ZZ",
BFC_EQ: "BFC.EQ",
BFC_NE: "BFC.NE",
BFC_CS: "BFC.CS",
BFC_CC: "BFC.CC",
BFC_MI: "BFC.MI",
BFC_PL: "BFC.PL",
BFC_VS: "BFC.VS",
BFC_VC: "BFC.VC",
BFC_HI: "BFC.HI",
BFC_LS: "BFC.LS",
BFC_GE: "BFC.GE",
BFC_LT: "BFC.LT",
BFC_GT: "BFC.GT",
BFC_LE: "BFC.LE",
BFC: "BFC",
BFC_ZZ: "BFC.ZZ",
BFI_EQ: "BFI.EQ",
BFI_NE: "BFI.NE",
BFI_CS: "BFI.CS",
BFI_CC: "BFI.CC",
BFI_MI: "BFI.MI",
BFI_PL: "BFI.PL",
BFI_VS: "BFI.VS",
BFI_VC: "BFI.VC",
BFI_HI: "BFI.HI",
BFI_LS: "BFI.LS",
BFI_GE: "BFI.GE",
BFI_LT: "BFI.LT",
BFI_GT: "BFI.GT",
BFI_LE: "BFI.LE",
BFI: "BFI",
BFI_ZZ: "BFI.ZZ",
BIC_EQ: "BIC.EQ",
BIC_NE: "BIC.NE",
BIC_CS: "BIC.CS",
BIC_CC: "BIC.CC",
BIC_MI: "BIC.MI",
BIC_PL: "BIC.PL",
BIC_VS: "BIC.VS",
BIC_VC: "BIC.VC",
BIC_HI: "BIC.HI",
BIC_LS: "BIC.LS",
BIC_GE: "BIC.GE",
BIC_LT: "BIC.LT",
BIC_GT: "BIC.GT",
BIC_LE: "BIC.LE",
BIC: "BIC",
BIC_ZZ: "BIC.ZZ",
BIC_S_EQ: "BIC.S.EQ",
BIC_S_NE: "BIC.S.NE",
BIC_S_CS: "BIC.S.CS",
BIC_S_CC: "BIC.S.CC",
BIC_S_MI: "BIC.S.MI",
BIC_S_PL: "BIC.S.PL",
BIC_S_VS: "BIC.S.VS",
BIC_S_VC: "BIC.S.VC",
BIC_S_HI: "BIC.S.HI",
BIC_S_LS: "BIC.S.LS",
BIC_S_GE: "BIC.S.GE",
BIC_S_LT: "BIC.S.LT",
BIC_S_GT: "BIC.S.GT",
BIC_S_LE: "BIC.S.LE",
BIC_S: "BIC.S",
BIC_S_ZZ: "BIC.S.ZZ",
BKPT_EQ: "BKPT.EQ",
BKPT_NE: "BKPT.NE",
BKPT_CS: "BKPT.CS",
BKPT_CC: "BKPT.CC",
BKPT_MI: "BKPT.MI",
BKPT_PL: "BKPT.PL",
BKPT_VS: "BKPT.VS",
BKPT_VC: "BKPT.VC",
BKPT_HI: "BKPT.HI",
BKPT_LS: "BKPT.LS",
BKPT_GE: "BKPT.GE",
BKPT_LT: "BKPT.LT",
BKPT_GT: "BKPT.GT",
BKPT_LE: "BKPT.LE",
BKPT: "BKPT",
BKPT_ZZ: "BKPT.ZZ",
BL_EQ: "BL.EQ",
BL_NE: "BL.NE",
BL_CS: "BL.CS",
BL_CC: "BL.CC",
BL_MI: "BL.MI",
BL_PL: "BL.PL",
BL_VS: "BL.VS",
BL_VC: "BL.VC",
BL_HI: "BL.HI",
BL_LS: "BL.LS",
BL_GE: "BL.GE",
BL_LT: "BL.LT",
BL_GT: "BL.GT",
BL_LE: "BL.LE",
BL: "BL",
BL_ZZ: "BL.ZZ",
BLX_EQ: "BLX.EQ",
BLX_NE: "BLX.NE",
BLX_CS: "BLX.CS",
BLX_CC: "BLX.CC",
BLX_MI: "BLX.MI",
BLX_PL: "BLX.PL",
BLX_VS: "BLX.VS",
BLX_VC: "BLX.VC",
BLX_HI: "BLX.HI",
BLX_LS: "BLX.LS",
BLX_GE: "BLX.GE",
BLX_LT: "BLX.LT",
BLX_GT: "BLX.GT",
BLX_LE: "BLX.LE",
BLX: "BLX",
BLX_ZZ: "BLX.ZZ",
BX_EQ: "BX.EQ",
BX_NE: "BX.NE",
BX_CS: "BX.CS",
BX_CC: "BX.CC",
BX_MI: "BX.MI",
BX_PL: "BX.PL",
BX_VS: "BX.VS",
BX_VC: "BX.VC",
BX_HI: "BX.HI",
BX_LS: "BX.LS",
BX_GE: "BX.GE",
BX_LT: "BX.LT",
BX_GT: "BX.GT",
BX_LE: "BX.LE",
BX: "BX",
BX_ZZ: "BX.ZZ",
BXJ_EQ: "BXJ.EQ",
BXJ_NE: "BXJ.NE",
BXJ_CS: "BXJ.CS",
BXJ_CC: "BXJ.CC",
BXJ_MI: "BXJ.MI",
BXJ_PL: "BXJ.PL",
BXJ_VS: "BXJ.VS",
BXJ_VC: "BXJ.VC",
BXJ_HI: "BXJ.HI",
BXJ_LS: "BXJ.LS",
BXJ_GE: "BXJ.GE",
BXJ_LT: "BXJ.LT",
BXJ_GT: "BXJ.GT",
BXJ_LE: "BXJ.LE",
BXJ: "BXJ",
BXJ_ZZ: "BXJ.ZZ",
CLREX: "CLREX",
CLZ_EQ: "CLZ.EQ",
CLZ_NE: "CLZ.NE",
CLZ_CS: "CLZ.CS",
CLZ_CC: "CLZ.CC",
CLZ_MI: "CLZ.MI",
CLZ_PL: "CLZ.PL",
CLZ_VS: "CLZ.VS",
CLZ_VC: "CLZ.VC",
CLZ_HI: "CLZ.HI",
CLZ_LS: "CLZ.LS",
CLZ_GE: "CLZ.GE",
CLZ_LT: "CLZ.LT",
CLZ_GT: "CLZ.GT",
CLZ_LE: "CLZ.LE",
CLZ: "CLZ",
CLZ_ZZ: "CLZ.ZZ",
CMN_EQ: "CMN.EQ",
CMN_NE: "CMN.NE",
CMN_CS: "CMN.CS",
CMN_CC: "CMN.CC",
CMN_MI: "CMN.MI",
CMN_PL: "CMN.PL",
CMN_VS: "CMN.VS",
CMN_VC: "CMN.VC",
CMN_HI: "CMN.HI",
CMN_LS: "CMN.LS",
CMN_GE: "CMN.GE",
CMN_LT: "CMN.LT",
CMN_GT: "CMN.GT",
CMN_LE: "CMN.LE",
CMN: "CMN",
CMN_ZZ: "CMN.ZZ",
CMP_EQ: "CMP.EQ",
CMP_NE: "CMP.NE",
CMP_CS: "CMP.CS",
CMP_CC: "CMP.CC",
CMP_MI: "CMP.MI",
CMP_PL: "CMP.PL",
CMP_VS: "CMP.VS",
CMP_VC: "CMP.VC",
CMP_HI: "CMP.HI",
CMP_LS: "CMP.LS",
CMP_GE: "CMP.GE",
CMP_LT: "CMP.LT",
CMP_GT: "CMP.GT",
CMP_LE: "CMP.LE",
CMP: "CMP",
CMP_ZZ: "CMP.ZZ",
DBG_EQ: "DBG.EQ",
DBG_NE: "DBG.NE",
DBG_CS: "DBG.CS",
DBG_CC: "DBG.CC",
DBG_MI: "DBG.MI",
DBG_PL: "DBG.PL",
DBG_VS: "DBG.VS",
DBG_VC: "DBG.VC",
DBG_HI: "DBG.HI",
DBG_LS: "DBG.LS",
DBG_GE: "DBG.GE",
DBG_LT: "DBG.LT",
DBG_GT: "DBG.GT",
DBG_LE: "DBG.LE",
DBG: "DBG",
DBG_ZZ: "DBG.ZZ",
DMB: "DMB",
DSB: "DSB",
EOR_EQ: "EOR.EQ",
EOR_NE: "EOR.NE",
EOR_CS: "EOR.CS",
EOR_CC: "EOR.CC",
EOR_MI: "EOR.MI",
EOR_PL: "EOR.PL",
EOR_VS: "EOR.VS",
EOR_VC: "EOR.VC",
EOR_HI: "EOR.HI",
EOR_LS: "EOR.LS",
EOR_GE: "EOR.GE",
EOR_LT: "EOR.LT",
EOR_GT: "EOR.GT",
EOR_LE: "EOR.LE",
EOR: "EOR",
EOR_ZZ: "EOR.ZZ",
EOR_S_EQ: "EOR.S.EQ",
EOR_S_NE: "EOR.S.NE",
EOR_S_CS: "EOR.S.CS",
EOR_S_CC: "EOR.S.CC",
EOR_S_MI: "EOR.S.MI",
EOR_S_PL: "EOR.S.PL",
EOR_S_VS: "EOR.S.VS",
EOR_S_VC: "EOR.S.VC",
EOR_S_HI: "EOR.S.HI",
EOR_S_LS: "EOR.S.LS",
EOR_S_GE: "EOR.S.GE",
EOR_S_LT: "EOR.S.LT",
EOR_S_GT: "EOR.S.GT",
EOR_S_LE: "EOR.S.LE",
EOR_S: "EOR.S",
EOR_S_ZZ: "EOR.S.ZZ",
ISB: "ISB",
LDM_EQ: "LDM.EQ",
LDM_NE: "LDM.NE",
LDM_CS: "LDM.CS",
LDM_CC: "LDM.CC",
LDM_MI: "LDM.MI",
LDM_PL: "LDM.PL",
LDM_VS: "LDM.VS",
LDM_VC: "LDM.VC",
LDM_HI: "LDM.HI",
LDM_LS: "LDM.LS",
LDM_GE: "LDM.GE",
LDM_LT: "LDM.LT",
LDM_GT: "LDM.GT",
LDM_LE: "LDM.LE",
LDM: "LDM",
LDM_ZZ: "LDM.ZZ",
LDMDA_EQ: "LDMDA.EQ",
LDMDA_NE: "LDMDA.NE",
LDMDA_CS: "LDMDA.CS",
LDMDA_CC: "LDMDA.CC",
LDMDA_MI: "LDMDA.MI",
LDMDA_PL: "LDMDA.PL",
LDMDA_VS: "LDMDA.VS",
LDMDA_VC: "LDMDA.VC",
LDMDA_HI: "LDMDA.HI",
LDMDA_LS: "LDMDA.LS",
LDMDA_GE: "LDMDA.GE",
LDMDA_LT: "LDMDA.LT",
LDMDA_GT: "LDMDA.GT",
LDMDA_LE: "LDMDA.LE",
LDMDA: "LDMDA",
LDMDA_ZZ: "LDMDA.ZZ",
LDMDB_EQ: "LDMDB.EQ",
LDMDB_NE: "LDMDB.NE",
LDMDB_CS: "LDMDB.CS",
LDMDB_CC: "LDMDB.CC",
LDMDB_MI: "LDMDB.MI",
LDMDB_PL: "LDMDB.PL",
LDMDB_VS: "LDMDB.VS",
LDMDB_VC: "LDMDB.VC",
LDMDB_HI: "LDMDB.HI",
LDMDB_LS: "LDMDB.LS",
LDMDB_GE: "LDMDB.GE",
LDMDB_LT: "LDMDB.LT",
LDMDB_GT: "LDMDB.GT",
LDMDB_LE: "LDMDB.LE",
LDMDB: "LDMDB",
LDMDB_ZZ: "LDMDB.ZZ",
LDMIB_EQ: "LDMIB.EQ",
LDMIB_NE: "LDMIB.NE",
LDMIB_CS: "LDMIB.CS",
LDMIB_CC: "LDMIB.CC",
LDMIB_MI: "LDMIB.MI",
LDMIB_PL: "LDMIB.PL",
LDMIB_VS: "LDMIB.VS",
LDMIB_VC: "LDMIB.VC",
LDMIB_HI: "LDMIB.HI",
LDMIB_LS: "LDMIB.LS",
LDMIB_GE: "LDMIB.GE",
LDMIB_LT: "LDMIB.LT",
LDMIB_GT: "LDMIB.GT",
LDMIB_LE: "LDMIB.LE",
LDMIB: "LDMIB",
LDMIB_ZZ: "LDMIB.ZZ",
LDR_EQ: "LDR.EQ",
LDR_NE: "LDR.NE",
LDR_CS: "LDR.CS",
LDR_CC: "LDR.CC",
LDR_MI: "LDR.MI",
LDR_PL: "LDR.PL",
LDR_VS: "LDR.VS",
LDR_VC: "LDR.VC",
LDR_HI: "LDR.HI",
LDR_LS: "LDR.LS",
LDR_GE: "LDR.GE",
LDR_LT: "LDR.LT",
LDR_GT: "LDR.GT",
LDR_LE: "LDR.LE",
LDR: "LDR",
LDR_ZZ: "LDR.ZZ",
LDRB_EQ: "LDRB.EQ",
LDRB_NE: "LDRB.NE",
LDRB_CS: "LDRB.CS",
LDRB_CC: "LDRB.CC",
LDRB_MI: "LDRB.MI",
LDRB_PL: "LDRB.PL",
LDRB_VS: "LDRB.VS",
LDRB_VC: "LDRB.VC",
LDRB_HI: "LDRB.HI",
LDRB_LS: "LDRB.LS",
LDRB_GE: "LDRB.GE",
LDRB_LT: "LDRB.LT",
LDRB_GT: "LDRB.GT",
LDRB_LE: "LDRB.LE",
LDRB: "LDRB",
LDRB_ZZ: "LDRB.ZZ",
LDRBT_EQ: "LDRBT.EQ",
LDRBT_NE: "LDRBT.NE",
LDRBT_CS: "LDRBT.CS",
LDRBT_CC: "LDRBT.CC",
LDRBT_MI: "LDRBT.MI",
LDRBT_PL: "LDRBT.PL",
LDRBT_VS: "LDRBT.VS",
LDRBT_VC: "LDRBT.VC",
LDRBT_HI: "LDRBT.HI",
LDRBT_LS: "LDRBT.LS",
LDRBT_GE: "LDRBT.GE",
LDRBT_LT: "LDRBT.LT",
LDRBT_GT: "LDRBT.GT",
LDRBT_LE: "LDRBT.LE",
LDRBT: "LDRBT",
LDRBT_ZZ: "LDRBT.ZZ",
LDRD_EQ: "LDRD.EQ",
LDRD_NE: "LDRD.NE",
LDRD_CS: "LDRD.CS",
LDRD_CC: "LDRD.CC",
LDRD_MI: "LDRD.MI",
LDRD_PL: "LDRD.PL",
LDRD_VS: "LDRD.VS",
LDRD_VC: "LDRD.VC",
LDRD_HI: "LDRD.HI",
LDRD_LS: "LDRD.LS",
LDRD_GE: "LDRD.GE",
LDRD_LT: "LDRD.LT",
LDRD_GT: "LDRD.GT",
LDRD_LE: "LDRD.LE",
LDRD: "LDRD",
LDRD_ZZ: "LDRD.ZZ",
LDREX_EQ: "LDREX.EQ",
LDREX_NE: "LDREX.NE",
LDREX_CS: "LDREX.CS",
LDREX_CC: "LDREX.CC",
LDREX_MI: "LDREX.MI",
LDREX_PL: "LDREX.PL",
LDREX_VS: "LDREX.VS",
LDREX_VC: "LDREX.VC",
LDREX_HI: "LDREX.HI",
LDREX_LS: "LDREX.LS",
LDREX_GE: "LDREX.GE",
LDREX_LT: "LDREX.LT",
LDREX_GT: "LDREX.GT",
LDREX_LE: "LDREX.LE",
LDREX: "LDREX",
LDREX_ZZ: "LDREX.ZZ",
LDREXB_EQ: "LDREXB.EQ",
LDREXB_NE: "LDREXB.NE",
LDREXB_CS: "LDREXB.CS",
LDREXB_CC: "LDREXB.CC",
LDREXB_MI: "LDREXB.MI",
LDREXB_PL: "LDREXB.PL",
LDREXB_VS: "LDREXB.VS",
LDREXB_VC: "LDREXB.VC",
LDREXB_HI: "LDREXB.HI",
LDREXB_LS: "LDREXB.LS",
LDREXB_GE: "LDREXB.GE",
LDREXB_LT: "LDREXB.LT",
LDREXB_GT: "LDREXB.GT",
LDREXB_LE: "LDREXB.LE",
LDREXB: "LDREXB",
LDREXB_ZZ: "LDREXB.ZZ",
LDREXD_EQ: "LDREXD.EQ",
LDREXD_NE: "LDREXD.NE",
LDREXD_CS: "LDREXD.CS",
LDREXD_CC: "LDREXD.CC",
LDREXD_MI: "LDREXD.MI",
LDREXD_PL: "LDREXD.PL",
LDREXD_VS: "LDREXD.VS",
LDREXD_VC: "LDREXD.VC",
LDREXD_HI: "LDREXD.HI",
LDREXD_LS: "LDREXD.LS",
LDREXD_GE: "LDREXD.GE",
LDREXD_LT: "LDREXD.LT",
LDREXD_GT: "LDREXD.GT",
LDREXD_LE: "LDREXD.LE",
LDREXD: "LDREXD",
LDREXD_ZZ: "LDREXD.ZZ",
LDREXH_EQ: "LDREXH.EQ",
LDREXH_NE: "LDREXH.NE",
LDREXH_CS: "LDREXH.CS",
LDREXH_CC: "LDREXH.CC",
LDREXH_MI: "LDREXH.MI",
LDREXH_PL: "LDREXH.PL",
LDREXH_VS: "LDREXH.VS",
LDREXH_VC: "LDREXH.VC",
LDREXH_HI: "LDREXH.HI",
LDREXH_LS: "LDREXH.LS",
LDREXH_GE: "LDREXH.GE",
LDREXH_LT: "LDREXH.LT",
LDREXH_GT: "LDREXH.GT",
LDREXH_LE: "LDREXH.LE",
LDREXH: "LDREXH",
LDREXH_ZZ: "LDREXH.ZZ",
LDRH_EQ: "LDRH.EQ",
LDRH_NE: "LDRH.NE",
LDRH_CS: "LDRH.CS",
LDRH_CC: "LDRH.CC",
LDRH_MI: "LDRH.MI",
LDRH_PL: "LDRH.PL",
LDRH_VS: "LDRH.VS",
LDRH_VC: "LDRH.VC",
LDRH_HI: "LDRH.HI",
LDRH_LS: "LDRH.LS",
LDRH_GE: "LDRH.GE",
LDRH_LT: "LDRH.LT",
LDRH_GT: "LDRH.GT",
LDRH_LE: "LDRH.LE",
LDRH: "LDRH",
LDRH_ZZ: "LDRH.ZZ",
LDRHT_EQ: "LDRHT.EQ",
LDRHT_NE: "LDRHT.NE",
LDRHT_CS: "LDRHT.CS",
LDRHT_CC: "LDRHT.CC",
LDRHT_MI: "LDRHT.MI",
LDRHT_PL: "LDRHT.PL",
LDRHT_VS: "LDRHT.VS",
LDRHT_VC: "LDRHT.VC",
LDRHT_HI: "LDRHT.HI",
LDRHT_LS: "LDRHT.LS",
LDRHT_GE: "LDRHT.GE",
LDRHT_LT: "LDRHT.LT",
LDRHT_GT: "LDRHT.GT",
LDRHT_LE: "LDRHT.LE",
LDRHT: "LDRHT",
LDRHT_ZZ: "LDRHT.ZZ",
LDRSB_EQ: "LDRSB.EQ",
LDRSB_NE: "LDRSB.NE",
LDRSB_CS: "LDRSB.CS",
LDRSB_CC: "LDRSB.CC",
LDRSB_MI: "LDRSB.MI",
LDRSB_PL: "LDRSB.PL",
LDRSB_VS: "LDRSB.VS",
LDRSB_VC: "LDRSB.VC",
LDRSB_HI: "LDRSB.HI",
LDRSB_LS: "LDRSB.LS",
LDRSB_GE: "LDRSB.GE",
LDRSB_LT: "LDRSB.LT",
LDRSB_GT: "LDRSB.GT",
LDRSB_LE: "LDRSB.LE",
LDRSB: "LDRSB",
LDRSB_ZZ: "LDRSB.ZZ",
LDRSBT_EQ: "LDRSBT.EQ",
LDRSBT_NE: "LDRSBT.NE",
LDRSBT_CS: "LDRSBT.CS",
LDRSBT_CC: "LDRSBT.CC",
LDRSBT_MI: "LDRSBT.MI",
LDRSBT_PL: "LDRSBT.PL",
LDRSBT_VS: "LDRSBT.VS",
LDRSBT_VC: "LDRSBT.VC",
LDRSBT_HI: "LDRSBT.HI",
LDRSBT_LS: "LDRSBT.LS",
LDRSBT_GE: "LDRSBT.GE",
LDRSBT_LT: "LDRSBT.LT",
LDRSBT_GT: "LDRSBT.GT",
LDRSBT_LE: "LDRSBT.LE",
LDRSBT: "LDRSBT",
LDRSBT_ZZ: "LDRSBT.ZZ",
LDRSH_EQ: "LDRSH.EQ",
LDRSH_NE: "LDRSH.NE",
LDRSH_CS: "LDRSH.CS",
LDRSH_CC: "LDRSH.CC",
LDRSH_MI: "LDRSH.MI",
LDRSH_PL: "LDRSH.PL",
LDRSH_VS: "LDRSH.VS",
LDRSH_VC: "LDRSH.VC",
LDRSH_HI: "LDRSH.HI",
LDRSH_LS: "LDRSH.LS",
LDRSH_GE: "LDRSH.GE",
LDRSH_LT: "LDRSH.LT",
LDRSH_GT: "LDRSH.GT",
LDRSH_LE: "LDRSH.LE",
LDRSH: "LDRSH",
LDRSH_ZZ: "LDRSH.ZZ",
LDRSHT_EQ: "LDRSHT.EQ",
LDRSHT_NE: "LDRSHT.NE",
LDRSHT_CS: "LDRSHT.CS",
LDRSHT_CC: "LDRSHT.CC",
LDRSHT_MI: "LDRSHT.MI",
LDRSHT_PL: "LDRSHT.PL",
LDRSHT_VS: "LDRSHT.VS",
LDRSHT_VC: "LDRSHT.VC",
LDRSHT_HI: "LDRSHT.HI",
LDRSHT_LS: "LDRSHT.LS",
LDRSHT_GE: "LDRSHT.GE",
LDRSHT_LT: "LDRSHT.LT",
LDRSHT_GT: "LDRSHT.GT",
LDRSHT_LE: "LDRSHT.LE",
LDRSHT: "LDRSHT",
LDRSHT_ZZ: "LDRSHT.ZZ",
LDRT_EQ: "LDRT.EQ",
LDRT_NE: "LDRT.NE",
LDRT_CS: "LDRT.CS",
LDRT_CC: "LDRT.CC",
LDRT_MI: "LDRT.MI",
LDRT_PL: "LDRT.PL",
LDRT_VS: "LDRT.VS",
LDRT_VC: "LDRT.VC",
LDRT_HI: "LDRT.HI",
LDRT_LS: "LDRT.LS",
LDRT_GE: "LDRT.GE",
LDRT_LT: "LDRT.LT",
LDRT_GT: "LDRT.GT",
LDRT_LE: "LDRT.LE",
LDRT: "LDRT",
LDRT_ZZ: "LDRT.ZZ",
LSL_EQ: "LSL.EQ",
LSL_NE: "LSL.NE",
LSL_CS: "LSL.CS",
LSL_CC: "LSL.CC",
LSL_MI: "LSL.MI",
LSL_PL: "LSL.PL",
LSL_VS: "LSL.VS",
LSL_VC: "LSL.VC",
LSL_HI: "LSL.HI",
LSL_LS: "LSL.LS",
LSL_GE: "LSL.GE",
LSL_LT: "LSL.LT",
LSL_GT: "LSL.GT",
LSL_LE: "LSL.LE",
LSL: "LSL",
LSL_ZZ: "LSL.ZZ",
LSL_S_EQ: "LSL.S.EQ",
LSL_S_NE: "LSL.S.NE",
LSL_S_CS: "LSL.S.CS",
LSL_S_CC: "LSL.S.CC",
LSL_S_MI: "LSL.S.MI",
LSL_S_PL: "LSL.S.PL",
LSL_S_VS: "LSL.S.VS",
LSL_S_VC: "LSL.S.VC",
LSL_S_HI: "LSL.S.HI",
LSL_S_LS: "LSL.S.LS",
LSL_S_GE: "LSL.S.GE",
LSL_S_LT: "LSL.S.LT",
LSL_S_GT: "LSL.S.GT",
LSL_S_LE: "LSL.S.LE",
LSL_S: "LSL.S",
LSL_S_ZZ: "LSL.S.ZZ",
LSR_EQ: "LSR.EQ",
LSR_NE: "LSR.NE",
LSR_CS: "LSR.CS",
LSR_CC: "LSR.CC",
LSR_MI: "LSR.MI",
LSR_PL: "LSR.PL",
LSR_VS: "LSR.VS",
LSR_VC: "LSR.VC",
LSR_HI: "LSR.HI",
LSR_LS: "LSR.LS",
LSR_GE: "LSR.GE",
LSR_LT: "LSR.LT",
LSR_GT: "LSR.GT",
LSR_LE: "LSR.LE",
LSR: "LSR",
LSR_ZZ: "LSR.ZZ",
LSR_S_EQ: "LSR.S.EQ",
LSR_S_NE: "LSR.S.NE",
LSR_S_CS: "LSR.S.CS",
LSR_S_CC: "LSR.S.CC",
LSR_S_MI: "LSR.S.MI",
LSR_S_PL: "LSR.S.PL",
LSR_S_VS: "LSR.S.VS",
LSR_S_VC: "LSR.S.VC",
LSR_S_HI: "LSR.S.HI",
LSR_S_LS: "LSR.S.LS",
LSR_S_GE: "LSR.S.GE",
LSR_S_LT: "LSR.S.LT",
LSR_S_GT: "LSR.S.GT",
LSR_S_LE: "LSR.S.LE",
LSR_S: "LSR.S",
LSR_S_ZZ: "LSR.S.ZZ",
MLA_EQ: "MLA.EQ",
MLA_NE: "MLA.NE",
MLA_CS: "MLA.CS",
MLA_CC: "MLA.CC",
MLA_MI: "MLA.MI",
MLA_PL: "MLA.PL",
MLA_VS: "MLA.VS",
MLA_VC: "MLA.VC",
MLA_HI: "MLA.HI",
MLA_LS: "MLA.LS",
MLA_GE: "MLA.GE",
MLA_LT: "MLA.LT",
MLA_GT: "MLA.GT",
MLA_LE: "MLA.LE",
MLA: "MLA",
MLA_ZZ: "MLA.ZZ",
MLA_S_EQ: "MLA.S.EQ",
MLA_S_NE: "MLA.S.NE",
MLA_S_CS: "MLA.S.CS",
MLA_S_CC: "MLA.S.CC",
MLA_S_MI: "MLA.S.MI",
MLA_S_PL: "MLA.S.PL",
MLA_S_VS: "MLA.S.VS",
MLA_S_VC: "MLA.S.VC",
MLA_S_HI: "MLA.S.HI",
MLA_S_LS: "MLA.S.LS",
MLA_S_GE: "MLA.S.GE",
MLA_S_LT: "MLA.S.LT",
MLA_S_GT: "MLA.S.GT",
MLA_S_LE: "MLA.S.LE",
MLA_S: "MLA.S",
MLA_S_ZZ: "MLA.S.ZZ",
MLS_EQ: "MLS.EQ",
MLS_NE: "MLS.NE",
MLS_CS: "MLS.CS",
MLS_CC: "MLS.CC",
MLS_MI: "MLS.MI",
MLS_PL: "MLS.PL",
MLS_VS: "MLS.VS",
MLS_VC: "MLS.VC",
MLS_HI: "MLS.HI",
MLS_LS: "MLS.LS",
MLS_GE: "MLS.GE",
MLS_LT: "MLS.LT",
MLS_GT: "MLS.GT",
MLS_LE: "MLS.LE",
MLS: "MLS",
MLS_ZZ: "MLS.ZZ",
MOV_EQ: "MOV.EQ",
MOV_NE: "MOV.NE",
MOV_CS: "MOV.CS",
MOV_CC: "MOV.CC",
MOV_MI: "MOV.MI",
MOV_PL: "MOV.PL",
MOV_VS: "MOV.VS",
MOV_VC: "MOV.VC",
MOV_HI: "MOV.HI",
MOV_LS: "MOV.LS",
MOV_GE: "MOV.GE",
MOV_LT: "MOV.LT",
MOV_GT: "MOV.GT",
MOV_LE: "MOV.LE",
MOV: "MOV",
MOV_ZZ: "MOV.ZZ",
MOV_S_EQ: "MOV.S.EQ",
MOV_S_NE: "MOV.S.NE",
MOV_S_CS: "MOV.S.CS",
MOV_S_CC: "MOV.S.CC",
MOV_S_MI: "MOV.S.MI",
MOV_S_PL: "MOV.S.PL",
MOV_S_VS: "MOV.S.VS",
MOV_S_VC: "MOV.S.VC",
MOV_S_HI: "MOV.S.HI",
MOV_S_LS: "MOV.S.LS",
MOV_S_GE: "MOV.S.GE",
MOV_S_LT: "MOV.S.LT",
MOV_S_GT: "MOV.S.GT",
MOV_S_LE: "MOV.S.LE",
MOV_S: "MOV.S",
MOV_S_ZZ: "MOV.S.ZZ",
MOVT_EQ: "MOVT.EQ",
MOVT_NE: "MOVT.NE",
MOVT_CS: "MOVT.CS",
MOVT_CC: "MOVT.CC",
MOVT_MI: "MOVT.MI",
MOVT_PL: "MOVT.PL",
MOVT_VS: "MOVT.VS",
MOVT_VC: "MOVT.VC",
MOVT_HI: "MOVT.HI",
MOVT_LS: "MOVT.LS",
MOVT_GE: "MOVT.GE",
MOVT_LT: "MOVT.LT",
MOVT_GT: "MOVT.GT",
MOVT_LE: "MOVT.LE",
MOVT: "MOVT",
MOVT_ZZ: "MOVT.ZZ",
MOVW_EQ: "MOVW.EQ",
MOVW_NE: "MOVW.NE",
MOVW_CS: "MOVW.CS",
MOVW_CC: "MOVW.CC",
MOVW_MI: "MOVW.MI",
MOVW_PL: "MOVW.PL",
MOVW_VS: "MOVW.VS",
MOVW_VC: "MOVW.VC",
MOVW_HI: "MOVW.HI",
MOVW_LS: "MOVW.LS",
MOVW_GE: "MOVW.GE",
MOVW_LT: "MOVW.LT",
MOVW_GT: "MOVW.GT",
MOVW_LE: "MOVW.LE",
MOVW: "MOVW",
MOVW_ZZ: "MOVW.ZZ",
MRS_EQ: "MRS.EQ",
MRS_NE: "MRS.NE",
MRS_CS: "MRS.CS",
MRS_CC: "MRS.CC",
MRS_MI: "MRS.MI",
MRS_PL: "MRS.PL",
MRS_VS: "MRS.VS",
MRS_VC: "MRS.VC",
MRS_HI: "MRS.HI",
MRS_LS: "MRS.LS",
MRS_GE: "MRS.GE",
MRS_LT: "MRS.LT",
MRS_GT: "MRS.GT",
MRS_LE: "MRS.LE",
MRS: "MRS",
MRS_ZZ: "MRS.ZZ",
MUL_EQ: "MUL.EQ",
MUL_NE: "MUL.NE",
MUL_CS: "MUL.CS",
MUL_CC: "MUL.CC",
MUL_MI: "MUL.MI",
MUL_PL: "MUL.PL",
MUL_VS: "MUL.VS",
MUL_VC: "MUL.VC",
MUL_HI: "MUL.HI",
MUL_LS: "MUL.LS",
MUL_GE: "MUL.GE",
MUL_LT: "MUL.LT",
MUL_GT: "MUL.GT",
MUL_LE: "MUL.LE",
MUL: "MUL",
MUL_ZZ: "MUL.ZZ",
MUL_S_EQ: "MUL.S.EQ",
MUL_S_NE: "MUL.S.NE",
MUL_S_CS: "MUL.S.CS",
MUL_S_CC: "MUL.S.CC",
MUL_S_MI: "MUL.S.MI",
MUL_S_PL: "MUL.S.PL",
MUL_S_VS: "MUL.S.VS",
MUL_S_VC: "MUL.S.VC",
MUL_S_HI: "MUL.S.HI",
MUL_S_LS: "MUL.S.LS",
MUL_S_GE: "MUL.S.GE",
MUL_S_LT: "MUL.S.LT",
MUL_S_GT: "MUL.S.GT",
MUL_S_LE: "MUL.S.LE",
MUL_S: "MUL.S",
MUL_S_ZZ: "MUL.S.ZZ",
MVN_EQ: "MVN.EQ",
MVN_NE: "MVN.NE",
MVN_CS: "MVN.CS",
MVN_CC: "MVN.CC",
MVN_MI: "MVN.MI",
MVN_PL: "MVN.PL",
MVN_VS: "MVN.VS",
MVN_VC: "MVN.VC",
MVN_HI: "MVN.HI",
MVN_LS: "MVN.LS",
MVN_GE: "MVN.GE",
MVN_LT: "MVN.LT",
MVN_GT: "MVN.GT",
MVN_LE: "MVN.LE",
MVN: "MVN",
MVN_ZZ: "MVN.ZZ",
MVN_S_EQ: "MVN.S.EQ",
MVN_S_NE: "MVN.S.NE",
MVN_S_CS: "MVN.S.CS",
MVN_S_CC: "MVN.S.CC",
MVN_S_MI: "MVN.S.MI",
MVN_S_PL: "MVN.S.PL",
MVN_S_VS: "MVN.S.VS",
MVN_S_VC: "MVN.S.VC",
MVN_S_HI: "MVN.S.HI",
MVN_S_LS: "MVN.S.LS",
MVN_S_GE: "MVN.S.GE",
MVN_S_LT: "MVN.S.LT",
MVN_S_GT: "MVN.S.GT",
MVN_S_LE: "MVN.S.LE",
MVN_S: "MVN.S",
MVN_S_ZZ: "MVN.S.ZZ",
NOP_EQ: "NOP.EQ",
NOP_NE: "NOP.NE",
NOP_CS: "NOP.CS",
NOP_CC: "NOP.CC",
NOP_MI: "NOP.MI",
NOP_PL: "NOP.PL",
NOP_VS: "NOP.VS",
NOP_VC: "NOP.VC",
NOP_HI: "NOP.HI",
NOP_LS: "NOP.LS",
NOP_GE: "NOP.GE",
NOP_LT: "NOP.LT",
NOP_GT: "NOP.GT",
NOP_LE: "NOP.LE",
NOP: "NOP",
NOP_ZZ: "NOP.ZZ",
ORR_EQ: "ORR.EQ",
ORR_NE: "ORR.NE",
ORR_CS: "ORR.CS",
ORR_CC: "ORR.CC",
ORR_MI: "ORR.MI",
ORR_PL: "ORR.PL",
ORR_VS: "ORR.VS",
ORR_VC: "ORR.VC",
ORR_HI: "ORR.HI",
ORR_LS: "ORR.LS",
ORR_GE: "ORR.GE",
ORR_LT: "ORR.LT",
ORR_GT: "ORR.GT",
ORR_LE: "ORR.LE",
ORR: "ORR",
ORR_ZZ: "ORR.ZZ",
ORR_S_EQ: "ORR.S.EQ",
ORR_S_NE: "ORR.S.NE",
ORR_S_CS: "ORR.S.CS",
ORR_S_CC: "ORR.S.CC",
ORR_S_MI: "ORR.S.MI",
ORR_S_PL: "ORR.S.PL",
ORR_S_VS: "ORR.S.VS",
ORR_S_VC: "ORR.S.VC",
ORR_S_HI: "ORR.S.HI",
ORR_S_LS: "ORR.S.LS",
ORR_S_GE: "ORR.S.GE",
ORR_S_LT: "ORR.S.LT",
ORR_S_GT: "ORR.S.GT",
ORR_S_LE: "ORR.S.LE",
ORR_S: "ORR.S",
ORR_S_ZZ: "ORR.S.ZZ",
PKHBT_EQ: "PKHBT.EQ",
PKHBT_NE: "PKHBT.NE",
PKHBT_CS: "PKHBT.CS",
PKHBT_CC: "PKHBT.CC",
PKHBT_MI: "PKHBT.MI",
PKHBT_PL: "PKHBT.PL",
PKHBT_VS: "PKHBT.VS",
PKHBT_VC: "PKHBT.VC",
PKHBT_HI: "PKHBT.HI",
PKHBT_LS: "PKHBT.LS",
PKHBT_GE: "PKHBT.GE",
PKHBT_LT: "PKHBT.LT",
PKHBT_GT: "PKHBT.GT",
PKHBT_LE: "PKHBT.LE",
PKHBT: "PKHBT",
PKHBT_ZZ: "PKHBT.ZZ",
PKHTB_EQ: "PKHTB.EQ",
PKHTB_NE: "PKHTB.NE",
PKHTB_CS: "PKHTB.CS",
PKHTB_CC: "PKHTB.CC",
PKHTB_MI: "PKHTB.MI",
PKHTB_PL: "PKHTB.PL",
PKHTB_VS: "PKHTB.VS",
PKHTB_VC: "PKHTB.VC",
PKHTB_HI: "PKHTB.HI",
PKHTB_LS: "PKHTB.LS",
PKHTB_GE: "PKHTB.GE",
PKHTB_LT: "PKHTB.LT",
PKHTB_GT: "PKHTB.GT",
PKHTB_LE: "PKHTB.LE",
PKHTB: "PKHTB",
PKHTB_ZZ: "PKHTB.ZZ",
PLD_W: "PLD.W",
PLD: "PLD",
PLI: "PLI",
POP_EQ: "POP.EQ",
POP_NE: "POP.NE",
POP_CS: "POP.CS",
POP_CC: "POP.CC",
POP_MI: "POP.MI",
POP_PL: "POP.PL",
POP_VS: "POP.VS",
POP_VC: "POP.VC",
POP_HI: "POP.HI",
POP_LS: "POP.LS",
POP_GE: "POP.GE",
POP_LT: "POP.LT",
POP_GT: "POP.GT",
POP_LE: "POP.LE",
POP: "POP",
POP_ZZ: "POP.ZZ",
PUSH_EQ: "PUSH.EQ",
PUSH_NE: "PUSH.NE",
PUSH_CS: "PUSH.CS",
PUSH_CC: "PUSH.CC",
PUSH_MI: "PUSH.MI",
PUSH_PL: "PUSH.PL",
PUSH_VS: "PUSH.VS",
PUSH_VC: "PUSH.VC",
PUSH_HI: "PUSH.HI",
PUSH_LS: "PUSH.LS",
PUSH_GE: "PUSH.GE",
PUSH_LT: "PUSH.LT",
PUSH_GT: "PUSH.GT",
PUSH_LE: "PUSH.LE",
PUSH: "PUSH",
PUSH_ZZ: "PUSH.ZZ",
QADD_EQ: "QADD.EQ",
QADD_NE: "QADD.NE",
QADD_CS: "QADD.CS",
QADD_CC: "QADD.CC",
QADD_MI: "QADD.MI",
QADD_PL: "QADD.PL",
QADD_VS: "QADD.VS",
QADD_VC: "QADD.VC",
QADD_HI: "QADD.HI",
QADD_LS: "QADD.LS",
QADD_GE: "QADD.GE",
QADD_LT: "QADD.LT",
QADD_GT: "QADD.GT",
QADD_LE: "QADD.LE",
QADD: "QADD",
QADD_ZZ: "QADD.ZZ",
QADD16_EQ: "QADD16.EQ",
QADD16_NE: "QADD16.NE",
QADD16_CS: "QADD16.CS",
QADD16_CC: "QADD16.CC",
QADD16_MI: "QADD16.MI",
QADD16_PL: "QADD16.PL",
QADD16_VS: "QADD16.VS",
QADD16_VC: "QADD16.VC",
QADD16_HI: "QADD16.HI",
QADD16_LS: "QADD16.LS",
QADD16_GE: "QADD16.GE",
QADD16_LT: "QADD16.LT",
QADD16_GT: "QADD16.GT",
QADD16_LE: "QADD16.LE",
QADD16: "QADD16",
QADD16_ZZ: "QADD16.ZZ",
QADD8_EQ: "QADD8.EQ",
QADD8_NE: "QADD8.NE",
QADD8_CS: "QADD8.CS",
QADD8_CC: "QADD8.CC",
QADD8_MI: "QADD8.MI",
QADD8_PL: "QADD8.PL",
QADD8_VS: "QADD8.VS",
QADD8_VC: "QADD8.VC",
QADD8_HI: "QADD8.HI",
QADD8_LS: "QADD8.LS",
QADD8_GE: "QADD8.GE",
QADD8_LT: "QADD8.LT",
QADD8_GT: "QADD8.GT",
QADD8_LE: "QADD8.LE",
QADD8: "QADD8",
QADD8_ZZ: "QADD8.ZZ",
QASX_EQ: "QASX.EQ",
QASX_NE: "QASX.NE",
QASX_CS: "QASX.CS",
QASX_CC: "QASX.CC",
QASX_MI: "QASX.MI",
QASX_PL: "QASX.PL",
QASX_VS: "QASX.VS",
QASX_VC: "QASX.VC",
QASX_HI: "QASX.HI",
QASX_LS: "QASX.LS",
QASX_GE: "QASX.GE",
QASX_LT: "QASX.LT",
QASX_GT: "QASX.GT",
QASX_LE: "QASX.LE",
QASX: "QASX",
QASX_ZZ: "QASX.ZZ",
QDADD_EQ: "QDADD.EQ",
QDADD_NE: "QDADD.NE",
QDADD_CS: "QDADD.CS",
QDADD_CC: "QDADD.CC",
QDADD_MI: "QDADD.MI",
QDADD_PL: "QDADD.PL",
QDADD_VS: "QDADD.VS",
QDADD_VC: "QDADD.VC",
QDADD_HI: "QDADD.HI",
QDADD_LS: "QDADD.LS",
QDADD_GE: "QDADD.GE",
QDADD_LT: "QDADD.LT",
QDADD_GT: "QDADD.GT",
QDADD_LE: "QDADD.LE",
QDADD: "QDADD",
QDADD_ZZ: "QDADD.ZZ",
QDSUB_EQ: "QDSUB.EQ",
QDSUB_NE: "QDSUB.NE",
QDSUB_CS: "QDSUB.CS",
QDSUB_CC: "QDSUB.CC",
QDSUB_MI: "QDSUB.MI",
QDSUB_PL: "QDSUB.PL",
QDSUB_VS: "QDSUB.VS",
QDSUB_VC: "QDSUB.VC",
QDSUB_HI: "QDSUB.HI",
QDSUB_LS: "QDSUB.LS",
QDSUB_GE: "QDSUB.GE",
QDSUB_LT: "QDSUB.LT",
QDSUB_GT: "QDSUB.GT",
QDSUB_LE: "QDSUB.LE",
QDSUB: "QDSUB",
QDSUB_ZZ: "QDSUB.ZZ",
QSAX_EQ: "QSAX.EQ",
QSAX_NE: "QSAX.NE",
QSAX_CS: "QSAX.CS",
QSAX_CC: "QSAX.CC",
QSAX_MI: "QSAX.MI",
QSAX_PL: "QSAX.PL",
QSAX_VS: "QSAX.VS",
QSAX_VC: "QSAX.VC",
QSAX_HI: "QSAX.HI",
QSAX_LS: "QSAX.LS",
QSAX_GE: "QSAX.GE",
QSAX_LT: "QSAX.LT",
QSAX_GT: "QSAX.GT",
QSAX_LE: "QSAX.LE",
QSAX: "QSAX",
QSAX_ZZ: "QSAX.ZZ",
QSUB_EQ: "QSUB.EQ",
QSUB_NE: "QSUB.NE",
QSUB_CS: "QSUB.CS",
QSUB_CC: "QSUB.CC",
QSUB_MI: "QSUB.MI",
QSUB_PL: "QSUB.PL",
QSUB_VS: "QSUB.VS",
QSUB_VC: "QSUB.VC",
QSUB_HI: "QSUB.HI",
QSUB_LS: "QSUB.LS",
QSUB_GE: "QSUB.GE",
QSUB_LT: "QSUB.LT",
QSUB_GT: "QSUB.GT",
QSUB_LE: "QSUB.LE",
QSUB: "QSUB",
QSUB_ZZ: "QSUB.ZZ",
QSUB16_EQ: "QSUB16.EQ",
QSUB16_NE: "QSUB16.NE",
QSUB16_CS: "QSUB16.CS",
QSUB16_CC: "QSUB16.CC",
QSUB16_MI: "QSUB16.MI",
QSUB16_PL: "QSUB16.PL",
QSUB16_VS: "QSUB16.VS",
QSUB16_VC: "QSUB16.VC",
QSUB16_HI: "QSUB16.HI",
QSUB16_LS: "QSUB16.LS",
QSUB16_GE: "QSUB16.GE",
QSUB16_LT: "QSUB16.LT",
QSUB16_GT: "QSUB16.GT",
QSUB16_LE: "QSUB16.LE",
QSUB16: "QSUB16",
QSUB16_ZZ: "QSUB16.ZZ",
QSUB8_EQ: "QSUB8.EQ",
QSUB8_NE: "QSUB8.NE",
QSUB8_CS: "QSUB8.CS",
QSUB8_CC: "QSUB8.CC",
QSUB8_MI: "QSUB8.MI",
QSUB8_PL: "QSUB8.PL",
QSUB8_VS: "QSUB8.VS",
QSUB8_VC: "QSUB8.VC",
QSUB8_HI: "QSUB8.HI",
QSUB8_LS: "QSUB8.LS",
QSUB8_GE: "QSUB8.GE",
QSUB8_LT: "QSUB8.LT",
QSUB8_GT: "QSUB8.GT",
QSUB8_LE: "QSUB8.LE",
QSUB8: "QSUB8",
QSUB8_ZZ: "QSUB8.ZZ",
RBIT_EQ: "RBIT.EQ",
RBIT_NE: "RBIT.NE",
RBIT_CS: "RBIT.CS",
RBIT_CC: "RBIT.CC",
RBIT_MI: "RBIT.MI",
RBIT_PL: "RBIT.PL",
RBIT_VS: "RBIT.VS",
RBIT_VC: "RBIT.VC",
RBIT_HI: "RBIT.HI",
RBIT_LS: "RBIT.LS",
RBIT_GE: "RBIT.GE",
RBIT_LT: "RBIT.LT",
RBIT_GT: "RBIT.GT",
RBIT_LE: "RBIT.LE",
RBIT: "RBIT",
RBIT_ZZ: "RBIT.ZZ",
REV_EQ: "REV.EQ",
REV_NE: "REV.NE",
REV_CS: "REV.CS",
REV_CC: "REV.CC",
REV_MI: "REV.MI",
REV_PL: "REV.PL",
REV_VS: "REV.VS",
REV_VC: "REV.VC",
REV_HI: "REV.HI",
REV_LS: "REV.LS",
REV_GE: "REV.GE",
REV_LT: "REV.LT",
REV_GT: "REV.GT",
REV_LE: "REV.LE",
REV: "REV",
REV_ZZ: "REV.ZZ",
REV16_EQ: "REV16.EQ",
REV16_NE: "REV16.NE",
REV16_CS: "REV16.CS",
REV16_CC: "REV16.CC",
REV16_MI: "REV16.MI",
REV16_PL: "REV16.PL",
REV16_VS: "REV16.VS",
REV16_VC: "REV16.VC",
REV16_HI: "REV16.HI",
REV16_LS: "REV16.LS",
REV16_GE: "REV16.GE",
REV16_LT: "REV16.LT",
REV16_GT: "REV16.GT",
REV16_LE: "REV16.LE",
REV16: "REV16",
REV16_ZZ: "REV16.ZZ",
REVSH_EQ: "REVSH.EQ",
REVSH_NE: "REVSH.NE",
REVSH_CS: "REVSH.CS",
REVSH_CC: "REVSH.CC",
REVSH_MI: "REVSH.MI",
REVSH_PL: "REVSH.PL",
REVSH_VS: "REVSH.VS",
REVSH_VC: "REVSH.VC",
REVSH_HI: "REVSH.HI",
REVSH_LS: "REVSH.LS",
REVSH_GE: "REVSH.GE",
REVSH_LT: "REVSH.LT",
REVSH_GT: "REVSH.GT",
REVSH_LE: "REVSH.LE",
REVSH: "REVSH",
REVSH_ZZ: "REVSH.ZZ",
ROR_EQ: "ROR.EQ",
ROR_NE: "ROR.NE",
ROR_CS: "ROR.CS",
ROR_CC: "ROR.CC",
ROR_MI: "ROR.MI",
ROR_PL: "ROR.PL",
ROR_VS: "ROR.VS",
ROR_VC: "ROR.VC",
ROR_HI: "ROR.HI",
ROR_LS: "ROR.LS",
ROR_GE: "ROR.GE",
ROR_LT: "ROR.LT",
ROR_GT: "ROR.GT",
ROR_LE: "ROR.LE",
ROR: "ROR",
ROR_ZZ: "ROR.ZZ",
ROR_S_EQ: "ROR.S.EQ",
ROR_S_NE: "ROR.S.NE",
ROR_S_CS: "ROR.S.CS",
ROR_S_CC: "ROR.S.CC",
ROR_S_MI: "ROR.S.MI",
ROR_S_PL: "ROR.S.PL",
ROR_S_VS: "ROR.S.VS",
ROR_S_VC: "ROR.S.VC",
ROR_S_HI: "ROR.S.HI",
ROR_S_LS: "ROR.S.LS",
ROR_S_GE: "ROR.S.GE",
ROR_S_LT: "ROR.S.LT",
ROR_S_GT: "ROR.S.GT",
ROR_S_LE: "ROR.S.LE",
ROR_S: "ROR.S",
ROR_S_ZZ: "ROR.S.ZZ",
RRX_EQ: "RRX.EQ",
RRX_NE: "RRX.NE",
RRX_CS: "RRX.CS",
RRX_CC: "RRX.CC",
RRX_MI: "RRX.MI",
RRX_PL: "RRX.PL",
RRX_VS: "RRX.VS",
RRX_VC: "RRX.VC",
RRX_HI: "RRX.HI",
RRX_LS: "RRX.LS",
RRX_GE: "RRX.GE",
RRX_LT: "RRX.LT",
RRX_GT: "RRX.GT",
RRX_LE: "RRX.LE",
RRX: "RRX",
RRX_ZZ: "RRX.ZZ",
RRX_S_EQ: "RRX.S.EQ",
RRX_S_NE: "RRX.S.NE",
RRX_S_CS: "RRX.S.CS",
RRX_S_CC: "RRX.S.CC",
RRX_S_MI: "RRX.S.MI",
RRX_S_PL: "RRX.S.PL",
RRX_S_VS: "RRX.S.VS",
RRX_S_VC: "RRX.S.VC",
RRX_S_HI: "RRX.S.HI",
RRX_S_LS: "RRX.S.LS",
RRX_S_GE: "RRX.S.GE",
RRX_S_LT: "RRX.S.LT",
RRX_S_GT: "RRX.S.GT",
RRX_S_LE: "RRX.S.LE",
RRX_S: "RRX.S",
RRX_S_ZZ: "RRX.S.ZZ",
RSB_EQ: "RSB.EQ",
RSB_NE: "RSB.NE",
RSB_CS: "RSB.CS",
RSB_CC: "RSB.CC",
RSB_MI: "RSB.MI",
RSB_PL: "RSB.PL",
RSB_VS: "RSB.VS",
RSB_VC: "RSB.VC",
RSB_HI: "RSB.HI",
RSB_LS: "RSB.LS",
RSB_GE: "RSB.GE",
RSB_LT: "RSB.LT",
RSB_GT: "RSB.GT",
RSB_LE: "RSB.LE",
RSB: "RSB",
RSB_ZZ: "RSB.ZZ",
RSB_S_EQ: "RSB.S.EQ",
RSB_S_NE: "RSB.S.NE",
RSB_S_CS: "RSB.S.CS",
RSB_S_CC: "RSB.S.CC",
RSB_S_MI: "RSB.S.MI",
RSB_S_PL: "RSB.S.PL",
RSB_S_VS: "RSB.S.VS",
RSB_S_VC: "RSB.S.VC",
RSB_S_HI: "RSB.S.HI",
RSB_S_LS: "RSB.S.LS",
RSB_S_GE: "RSB.S.GE",
RSB_S_LT: "RSB.S.LT",
RSB_S_GT: "RSB.S.GT",
RSB_S_LE: "RSB.S.LE",
RSB_S: "RSB.S",
RSB_S_ZZ: "RSB.S.ZZ",
RSC_EQ: "RSC.EQ",
RSC_NE: "RSC.NE",
RSC_CS: "RSC.CS",
RSC_CC: "RSC.CC",
RSC_MI: "RSC.MI",
RSC_PL: "RSC.PL",
RSC_VS: "RSC.VS",
RSC_VC: "RSC.VC",
RSC_HI: "RSC.HI",
RSC_LS: "RSC.LS",
RSC_GE: "RSC.GE",
RSC_LT: "RSC.LT",
RSC_GT: "RSC.GT",
RSC_LE: "RSC.LE",
RSC: "RSC",
RSC_ZZ: "RSC.ZZ",
RSC_S_EQ: "RSC.S.EQ",
RSC_S_NE: "RSC.S.NE",
RSC_S_CS: "RSC.S.CS",
RSC_S_CC: "RSC.S.CC",
RSC_S_MI: "RSC.S.MI",
RSC_S_PL: "RSC.S.PL",
RSC_S_VS: "RSC.S.VS",
RSC_S_VC: "RSC.S.VC",
RSC_S_HI: "RSC.S.HI",
RSC_S_LS: "RSC.S.LS",
RSC_S_GE: "RSC.S.GE",
RSC_S_LT: "RSC.S.LT",
RSC_S_GT: "RSC.S.GT",
RSC_S_LE: "RSC.S.LE",
RSC_S: "RSC.S",
RSC_S_ZZ: "RSC.S.ZZ",
SADD16_EQ: "SADD16.EQ",
SADD16_NE: "SADD16.NE",
SADD16_CS: "SADD16.CS",
SADD16_CC: "SADD16.CC",
SADD16_MI: "SADD16.MI",
SADD16_PL: "SADD16.PL",
SADD16_VS: "SADD16.VS",
SADD16_VC: "SADD16.VC",
SADD16_HI: "SADD16.HI",
SADD16_LS: "SADD16.LS",
SADD16_GE: "SADD16.GE",
SADD16_LT: "SADD16.LT",
SADD16_GT: "SADD16.GT",
SADD16_LE: "SADD16.LE",
SADD16: "SADD16",
SADD16_ZZ: "SADD16.ZZ",
SADD8_EQ: "SADD8.EQ",
SADD8_NE: "SADD8.NE",
SADD8_CS: "SADD8.CS",
SADD8_CC: "SADD8.CC",
SADD8_MI: "SADD8.MI",
SADD8_PL: "SADD8.PL",
SADD8_VS: "SADD8.VS",
SADD8_VC: "SADD8.VC",
SADD8_HI: "SADD8.HI",
SADD8_LS: "SADD8.LS",
SADD8_GE: "SADD8.GE",
SADD8_LT: "SADD8.LT",
SADD8_GT: "SADD8.GT",
SADD8_LE: "SADD8.LE",
SADD8: "SADD8",
SADD8_ZZ: "SADD8.ZZ",
SASX_EQ: "SASX.EQ",
SASX_NE: "SASX.NE",
SASX_CS: "SASX.CS",
SASX_CC: "SASX.CC",
SASX_MI: "SASX.MI",
SASX_PL: "SASX.PL",
SASX_VS: "SASX.VS",
SASX_VC: "SASX.VC",
SASX_HI: "SASX.HI",
SASX_LS: "SASX.LS",
SASX_GE: "SASX.GE",
SASX_LT: "SASX.LT",
SASX_GT: "SASX.GT",
SASX_LE: "SASX.LE",
SASX: "SASX",
SASX_ZZ: "SASX.ZZ",
SBC_EQ: "SBC.EQ",
SBC_NE: "SBC.NE",
SBC_CS: "SBC.CS",
SBC_CC: "SBC.CC",
SBC_MI: "SBC.MI",
SBC_PL: "SBC.PL",
SBC_VS: "SBC.VS",
SBC_VC: "SBC.VC",
SBC_HI: "SBC.HI",
SBC_LS: "SBC.LS",
SBC_GE: "SBC.GE",
SBC_LT: "SBC.LT",
SBC_GT: "SBC.GT",
SBC_LE: "SBC.LE",
SBC: "SBC",
SBC_ZZ: "SBC.ZZ",
SBC_S_EQ: "SBC.S.EQ",
SBC_S_NE: "SBC.S.NE",
SBC_S_CS: "SBC.S.CS",
SBC_S_CC: "SBC.S.CC",
SBC_S_MI: "SBC.S.MI",
SBC_S_PL: "SBC.S.PL",
SBC_S_VS: "SBC.S.VS",
SBC_S_VC: "SBC.S.VC",
SBC_S_HI: "SBC.S.HI",
SBC_S_LS: "SBC.S.LS",
SBC_S_GE: "SBC.S.GE",
SBC_S_LT: "SBC.S.LT",
SBC_S_GT: "SBC.S.GT",
SBC_S_LE: "SBC.S.LE",
SBC_S: "SBC.S",
SBC_S_ZZ: "SBC.S.ZZ",
SBFX_EQ: "SBFX.EQ",
SBFX_NE: "SBFX.NE",
SBFX_CS: "SBFX.CS",
SBFX_CC: "SBFX.CC",
SBFX_MI: "SBFX.MI",
SBFX_PL: "SBFX.PL",
SBFX_VS: "SBFX.VS",
SBFX_VC: "SBFX.VC",
SBFX_HI: "SBFX.HI",
SBFX_LS: "SBFX.LS",
SBFX_GE: "SBFX.GE",
SBFX_LT: "SBFX.LT",
SBFX_GT: "SBFX.GT",
SBFX_LE: "SBFX.LE",
SBFX: "SBFX",
SBFX_ZZ: "SBFX.ZZ",
SEL_EQ: "SEL.EQ",
SEL_NE: "SEL.NE",
SEL_CS: "SEL.CS",
SEL_CC: "SEL.CC",
SEL_MI: "SEL.MI",
SEL_PL: "SEL.PL",
SEL_VS: "SEL.VS",
SEL_VC: "SEL.VC",
SEL_HI: "SEL.HI",
SEL_LS: "SEL.LS",
SEL_GE: "SEL.GE",
SEL_LT: "SEL.LT",
SEL_GT: "SEL.GT",
SEL_LE: "SEL.LE",
SEL: "SEL",
SEL_ZZ: "SEL.ZZ",
SETEND: "SETEND",
SEV_EQ: "SEV.EQ",
SEV_NE: "SEV.NE",
SEV_CS: "SEV.CS",
SEV_CC: "SEV.CC",
SEV_MI: "SEV.MI",
SEV_PL: "SEV.PL",
SEV_VS: "SEV.VS",
SEV_VC: "SEV.VC",
SEV_HI: "SEV.HI",
SEV_LS: "SEV.LS",
SEV_GE: "SEV.GE",
SEV_LT: "SEV.LT",
SEV_GT: "SEV.GT",
SEV_LE: "SEV.LE",
SEV: "SEV",
SEV_ZZ: "SEV.ZZ",
SHADD16_EQ: "SHADD16.EQ",
SHADD16_NE: "SHADD16.NE",
SHADD16_CS: "SHADD16.CS",
SHADD16_CC: "SHADD16.CC",
SHADD16_MI: "SHADD16.MI",
SHADD16_PL: "SHADD16.PL",
SHADD16_VS: "SHADD16.VS",
SHADD16_VC: "SHADD16.VC",
SHADD16_HI: "SHADD16.HI",
SHADD16_LS: "SHADD16.LS",
SHADD16_GE: "SHADD16.GE",
SHADD16_LT: "SHADD16.LT",
SHADD16_GT: "SHADD16.GT",
SHADD16_LE: "SHADD16.LE",
SHADD16: "SHADD16",
SHADD16_ZZ: "SHADD16.ZZ",
SHADD8_EQ: "SHADD8.EQ",
SHADD8_NE: "SHADD8.NE",
SHADD8_CS: "SHADD8.CS",
SHADD8_CC: "SHADD8.CC",
SHADD8_MI: "SHADD8.MI",
SHADD8_PL: "SHADD8.PL",
SHADD8_VS: "SHADD8.VS",
SHADD8_VC: "SHADD8.VC",
SHADD8_HI: "SHADD8.HI",
SHADD8_LS: "SHADD8.LS",
SHADD8_GE: "SHADD8.GE",
SHADD8_LT: "SHADD8.LT",
SHADD8_GT: "SHADD8.GT",
SHADD8_LE: "SHADD8.LE",
SHADD8: "SHADD8",
SHADD8_ZZ: "SHADD8.ZZ",
SHASX_EQ: "SHASX.EQ",
SHASX_NE: "SHASX.NE",
SHASX_CS: "SHASX.CS",
SHASX_CC: "SHASX.CC",
SHASX_MI: "SHASX.MI",
SHASX_PL: "SHASX.PL",
SHASX_VS: "SHASX.VS",
SHASX_VC: "SHASX.VC",
SHASX_HI: "SHASX.HI",
SHASX_LS: "SHASX.LS",
SHASX_GE: "SHASX.GE",
SHASX_LT: "SHASX.LT",
SHASX_GT: "SHASX.GT",
SHASX_LE: "SHASX.LE",
SHASX: "SHASX",
SHASX_ZZ: "SHASX.ZZ",
SHSAX_EQ: "SHSAX.EQ",
SHSAX_NE: "SHSAX.NE",
SHSAX_CS: "SHSAX.CS",
SHSAX_CC: "SHSAX.CC",
SHSAX_MI: "SHSAX.MI",
SHSAX_PL: "SHSAX.PL",
SHSAX_VS: "SHSAX.VS",
SHSAX_VC: "SHSAX.VC",
SHSAX_HI: "SHSAX.HI",
SHSAX_LS: "SHSAX.LS",
SHSAX_GE: "SHSAX.GE",
SHSAX_LT: "SHSAX.LT",
SHSAX_GT: "SHSAX.GT",
SHSAX_LE: "SHSAX.LE",
SHSAX: "SHSAX",
SHSAX_ZZ: "SHSAX.ZZ",
SHSUB16_EQ: "SHSUB16.EQ",
SHSUB16_NE: "SHSUB16.NE",
SHSUB16_CS: "SHSUB16.CS",
SHSUB16_CC: "SHSUB16.CC",
SHSUB16_MI: "SHSUB16.MI",
SHSUB16_PL: "SHSUB16.PL",
SHSUB16_VS: "SHSUB16.VS",
SHSUB16_VC: "SHSUB16.VC",
SHSUB16_HI: "SHSUB16.HI",
SHSUB16_LS: "SHSUB16.LS",
SHSUB16_GE: "SHSUB16.GE",
SHSUB16_LT: "SHSUB16.LT",
SHSUB16_GT: "SHSUB16.GT",
SHSUB16_LE: "SHSUB16.LE",
SHSUB16: "SHSUB16",
SHSUB16_ZZ: "SHSUB16.ZZ",
SHSUB8_EQ: "SHSUB8.EQ",
SHSUB8_NE: "SHSUB8.NE",
SHSUB8_CS: "SHSUB8.CS",
SHSUB8_CC: "SHSUB8.CC",
SHSUB8_MI: "SHSUB8.MI",
SHSUB8_PL: "SHSUB8.PL",
SHSUB8_VS: "SHSUB8.VS",
SHSUB8_VC: "SHSUB8.VC",
SHSUB8_HI: "SHSUB8.HI",
SHSUB8_LS: "SHSUB8.LS",
SHSUB8_GE: "SHSUB8.GE",
SHSUB8_LT: "SHSUB8.LT",
SHSUB8_GT: "SHSUB8.GT",
SHSUB8_LE: "SHSUB8.LE",
SHSUB8: "SHSUB8",
SHSUB8_ZZ: "SHSUB8.ZZ",
SMLABB_EQ: "SMLABB.EQ",
SMLABB_NE: "SMLABB.NE",
SMLABB_CS: "SMLABB.CS",
SMLABB_CC: "SMLABB.CC",
SMLABB_MI: "SMLABB.MI",
SMLABB_PL: "SMLABB.PL",
SMLABB_VS: "SMLABB.VS",
SMLABB_VC: "SMLABB.VC",
SMLABB_HI: "SMLABB.HI",
SMLABB_LS: "SMLABB.LS",
SMLABB_GE: "SMLABB.GE",
SMLABB_LT: "SMLABB.LT",
SMLABB_GT: "SMLABB.GT",
SMLABB_LE: "SMLABB.LE",
SMLABB: "SMLABB",
SMLABB_ZZ: "SMLABB.ZZ",
SMLABT_EQ: "SMLABT.EQ",
SMLABT_NE: "SMLABT.NE",
SMLABT_CS: "SMLABT.CS",
SMLABT_CC: "SMLABT.CC",
SMLABT_MI: "SMLABT.MI",
SMLABT_PL: "SMLABT.PL",
SMLABT_VS: "SMLABT.VS",
SMLABT_VC: "SMLABT.VC",
SMLABT_HI: "SMLABT.HI",
SMLABT_LS: "SMLABT.LS",
SMLABT_GE: "SMLABT.GE",
SMLABT_LT: "SMLABT.LT",
SMLABT_GT: "SMLABT.GT",
SMLABT_LE: "SMLABT.LE",
SMLABT: "SMLABT",
SMLABT_ZZ: "SMLABT.ZZ",
SMLATB_EQ: "SMLATB.EQ",
SMLATB_NE: "SMLATB.NE",
SMLATB_CS: "SMLATB.CS",
SMLATB_CC: "SMLATB.CC",
SMLATB_MI: "SMLATB.MI",
SMLATB_PL: "SMLATB.PL",
SMLATB_VS: "SMLATB.VS",
SMLATB_VC: "SMLATB.VC",
SMLATB_HI: "SMLATB.HI",
SMLATB_LS: "SMLATB.LS",
SMLATB_GE: "SMLATB.GE",
SMLATB_LT: "SMLATB.LT",
SMLATB_GT: "SMLATB.GT",
SMLATB_LE: "SMLATB.LE",
SMLATB: "SMLATB",
SMLATB_ZZ: "SMLATB.ZZ",
SMLATT_EQ: "SMLATT.EQ",
SMLATT_NE: "SMLATT.NE",
SMLATT_CS: "SMLATT.CS",
SMLATT_CC: "SMLATT.CC",
SMLATT_MI: "SMLATT.MI",
SMLATT_PL: "SMLATT.PL",
SMLATT_VS: "SMLATT.VS",
SMLATT_VC: "SMLATT.VC",
SMLATT_HI: "SMLATT.HI",
SMLATT_LS: "SMLATT.LS",
SMLATT_GE: "SMLATT.GE",
SMLATT_LT: "SMLATT.LT",
SMLATT_GT: "SMLATT.GT",
SMLATT_LE: "SMLATT.LE",
SMLATT: "SMLATT",
SMLATT_ZZ: "SMLATT.ZZ",
SMLAD_EQ: "SMLAD.EQ",
SMLAD_NE: "SMLAD.NE",
SMLAD_CS: "SMLAD.CS",
SMLAD_CC: "SMLAD.CC",
SMLAD_MI: "SMLAD.MI",
SMLAD_PL: "SMLAD.PL",
SMLAD_VS: "SMLAD.VS",
SMLAD_VC: "SMLAD.VC",
SMLAD_HI: "SMLAD.HI",
SMLAD_LS: "SMLAD.LS",
SMLAD_GE: "SMLAD.GE",
SMLAD_LT: "SMLAD.LT",
SMLAD_GT: "SMLAD.GT",
SMLAD_LE: "SMLAD.LE",
SMLAD: "SMLAD",
SMLAD_ZZ: "SMLAD.ZZ",
SMLAD_X_EQ: "SMLAD.X.EQ",
SMLAD_X_NE: "SMLAD.X.NE",
SMLAD_X_CS: "SMLAD.X.CS",
SMLAD_X_CC: "SMLAD.X.CC",
SMLAD_X_MI: "SMLAD.X.MI",
SMLAD_X_PL: "SMLAD.X.PL",
SMLAD_X_VS: "SMLAD.X.VS",
SMLAD_X_VC: "SMLAD.X.VC",
SMLAD_X_HI: "SMLAD.X.HI",
SMLAD_X_LS: "SMLAD.X.LS",
SMLAD_X_GE: "SMLAD.X.GE",
SMLAD_X_LT: "SMLAD.X.LT",
SMLAD_X_GT: "SMLAD.X.GT",
SMLAD_X_LE: "SMLAD.X.LE",
SMLAD_X: "SMLAD.X",
SMLAD_X_ZZ: "SMLAD.X.ZZ",
SMLAL_EQ: "SMLAL.EQ",
SMLAL_NE: "SMLAL.NE",
SMLAL_CS: "SMLAL.CS",
SMLAL_CC: "SMLAL.CC",
SMLAL_MI: "SMLAL.MI",
SMLAL_PL: "SMLAL.PL",
SMLAL_VS: "SMLAL.VS",
SMLAL_VC: "SMLAL.VC",
SMLAL_HI: "SMLAL.HI",
SMLAL_LS: "SMLAL.LS",
SMLAL_GE: "SMLAL.GE",
SMLAL_LT: "SMLAL.LT",
SMLAL_GT: "SMLAL.GT",
SMLAL_LE: "SMLAL.LE",
SMLAL: "SMLAL",
SMLAL_ZZ: "SMLAL.ZZ",
SMLAL_S_EQ: "SMLAL.S.EQ",
SMLAL_S_NE: "SMLAL.S.NE",
SMLAL_S_CS: "SMLAL.S.CS",
SMLAL_S_CC: "SMLAL.S.CC",
SMLAL_S_MI: "SMLAL.S.MI",
SMLAL_S_PL: "SMLAL.S.PL",
SMLAL_S_VS: "SMLAL.S.VS",
SMLAL_S_VC: "SMLAL.S.VC",
SMLAL_S_HI: "SMLAL.S.HI",
SMLAL_S_LS: "SMLAL.S.LS",
SMLAL_S_GE: "SMLAL.S.GE",
SMLAL_S_LT: "SMLAL.S.LT",
SMLAL_S_GT: "SMLAL.S.GT",
SMLAL_S_LE: "SMLAL.S.LE",
SMLAL_S: "SMLAL.S",
SMLAL_S_ZZ: "SMLAL.S.ZZ",
SMLALBB_EQ: "SMLALBB.EQ",
SMLALBB_NE: "SMLALBB.NE",
SMLALBB_CS: "SMLALBB.CS",
SMLALBB_CC: "SMLALBB.CC",
SMLALBB_MI: "SMLALBB.MI",
SMLALBB_PL: "SMLALBB.PL",
SMLALBB_VS: "SMLALBB.VS",
SMLALBB_VC: "SMLALBB.VC",
SMLALBB_HI: "SMLALBB.HI",
SMLALBB_LS: "SMLALBB.LS",
SMLALBB_GE: "SMLALBB.GE",
SMLALBB_LT: "SMLALBB.LT",
SMLALBB_GT: "SMLALBB.GT",
SMLALBB_LE: "SMLALBB.LE",
SMLALBB: "SMLALBB",
SMLALBB_ZZ: "SMLALBB.ZZ",
SMLALBT_EQ: "SMLALBT.EQ",
SMLALBT_NE: "SMLALBT.NE",
SMLALBT_CS: "SMLALBT.CS",
SMLALBT_CC: "SMLALBT.CC",
SMLALBT_MI: "SMLALBT.MI",
SMLALBT_PL: "SMLALBT.PL",
SMLALBT_VS: "SMLALBT.VS",
SMLALBT_VC: "SMLALBT.VC",
SMLALBT_HI: "SMLALBT.HI",
SMLALBT_LS: "SMLALBT.LS",
SMLALBT_GE: "SMLALBT.GE",
SMLALBT_LT: "SMLALBT.LT",
SMLALBT_GT: "SMLALBT.GT",
SMLALBT_LE: "SMLALBT.LE",
SMLALBT: "SMLALBT",
SMLALBT_ZZ: "SMLALBT.ZZ",
SMLALTB_EQ: "SMLALTB.EQ",
SMLALTB_NE: "SMLALTB.NE",
SMLALTB_CS: "SMLALTB.CS",
SMLALTB_CC: "SMLALTB.CC",
SMLALTB_MI: "SMLALTB.MI",
SMLALTB_PL: "SMLALTB.PL",
SMLALTB_VS: "SMLALTB.VS",
SMLALTB_VC: "SMLALTB.VC",
SMLALTB_HI: "SMLALTB.HI",
SMLALTB_LS: "SMLALTB.LS",
SMLALTB_GE: "SMLALTB.GE",
SMLALTB_LT: "SMLALTB.LT",
SMLALTB_GT: "SMLALTB.GT",
SMLALTB_LE: "SMLALTB.LE",
SMLALTB: "SMLALTB",
SMLALTB_ZZ: "SMLALTB.ZZ",
SMLALTT_EQ: "SMLALTT.EQ",
SMLALTT_NE: "SMLALTT.NE",
SMLALTT_CS: "SMLALTT.CS",
SMLALTT_CC: "SMLALTT.CC",
SMLALTT_MI: "SMLALTT.MI",
SMLALTT_PL: "SMLALTT.PL",
SMLALTT_VS: "SMLALTT.VS",
SMLALTT_VC: "SMLALTT.VC",
SMLALTT_HI: "SMLALTT.HI",
SMLALTT_LS: "SMLALTT.LS",
SMLALTT_GE: "SMLALTT.GE",
SMLALTT_LT: "SMLALTT.LT",
SMLALTT_GT: "SMLALTT.GT",
SMLALTT_LE: "SMLALTT.LE",
SMLALTT: "SMLALTT",
SMLALTT_ZZ: "SMLALTT.ZZ",
SMLALD_EQ: "SMLALD.EQ",
SMLALD_NE: "SMLALD.NE",
SMLALD_CS: "SMLALD.CS",
SMLALD_CC: "SMLALD.CC",
SMLALD_MI: "SMLALD.MI",
SMLALD_PL: "SMLALD.PL",
SMLALD_VS: "SMLALD.VS",
SMLALD_VC: "SMLALD.VC",
SMLALD_HI: "SMLALD.HI",
SMLALD_LS: "SMLALD.LS",
SMLALD_GE: "SMLALD.GE",
SMLALD_LT: "SMLALD.LT",
SMLALD_GT: "SMLALD.GT",
SMLALD_LE: "SMLALD.LE",
SMLALD: "SMLALD",
SMLALD_ZZ: "SMLALD.ZZ",
SMLALD_X_EQ: "SMLALD.X.EQ",
SMLALD_X_NE: "SMLALD.X.NE",
SMLALD_X_CS: "SMLALD.X.CS",
SMLALD_X_CC: "SMLALD.X.CC",
SMLALD_X_MI: "SMLALD.X.MI",
SMLALD_X_PL: "SMLALD.X.PL",
SMLALD_X_VS: "SMLALD.X.VS",
SMLALD_X_VC: "SMLALD.X.VC",
SMLALD_X_HI: "SMLALD.X.HI",
SMLALD_X_LS: "SMLALD.X.LS",
SMLALD_X_GE: "SMLALD.X.GE",
SMLALD_X_LT: "SMLALD.X.LT",
SMLALD_X_GT: "SMLALD.X.GT",
SMLALD_X_LE: "SMLALD.X.LE",
SMLALD_X: "SMLALD.X",
SMLALD_X_ZZ: "SMLALD.X.ZZ",
SMLAWB_EQ: "SMLAWB.EQ",
SMLAWB_NE: "SMLAWB.NE",
SMLAWB_CS: "SMLAWB.CS",
SMLAWB_CC: "SMLAWB.CC",
SMLAWB_MI: "SMLAWB.MI",
SMLAWB_PL: "SMLAWB.PL",
SMLAWB_VS: "SMLAWB.VS",
SMLAWB_VC: "SMLAWB.VC",
SMLAWB_HI: "SMLAWB.HI",
SMLAWB_LS: "SMLAWB.LS",
SMLAWB_GE: "SMLAWB.GE",
SMLAWB_LT: "SMLAWB.LT",
SMLAWB_GT: "SMLAWB.GT",
SMLAWB_LE: "SMLAWB.LE",
SMLAWB: "SMLAWB",
SMLAWB_ZZ: "SMLAWB.ZZ",
SMLAWT_EQ: "SMLAWT.EQ",
SMLAWT_NE: "SMLAWT.NE",
SMLAWT_CS: "SMLAWT.CS",
SMLAWT_CC: "SMLAWT.CC",
SMLAWT_MI: "SMLAWT.MI",
SMLAWT_PL: "SMLAWT.PL",
SMLAWT_VS: "SMLAWT.VS",
SMLAWT_VC: "SMLAWT.VC",
SMLAWT_HI: "SMLAWT.HI",
SMLAWT_LS: "SMLAWT.LS",
SMLAWT_GE: "SMLAWT.GE",
SMLAWT_LT: "SMLAWT.LT",
SMLAWT_GT: "SMLAWT.GT",
SMLAWT_LE: "SMLAWT.LE",
SMLAWT: "SMLAWT",
SMLAWT_ZZ: "SMLAWT.ZZ",
SMLSD_EQ: "SMLSD.EQ",
SMLSD_NE: "SMLSD.NE",
SMLSD_CS: "SMLSD.CS",
SMLSD_CC: "SMLSD.CC",
SMLSD_MI: "SMLSD.MI",
SMLSD_PL: "SMLSD.PL",
SMLSD_VS: "SMLSD.VS",
SMLSD_VC: "SMLSD.VC",
SMLSD_HI: "SMLSD.HI",
SMLSD_LS: "SMLSD.LS",
SMLSD_GE: "SMLSD.GE",
SMLSD_LT: "SMLSD.LT",
SMLSD_GT: "SMLSD.GT",
SMLSD_LE: "SMLSD.LE",
SMLSD: "SMLSD",
SMLSD_ZZ: "SMLSD.ZZ",
SMLSD_X_EQ: "SMLSD.X.EQ",
SMLSD_X_NE: "SMLSD.X.NE",
SMLSD_X_CS: "SMLSD.X.CS",
SMLSD_X_CC: "SMLSD.X.CC",
SMLSD_X_MI: "SMLSD.X.MI",
SMLSD_X_PL: "SMLSD.X.PL",
SMLSD_X_VS: "SMLSD.X.VS",
SMLSD_X_VC: "SMLSD.X.VC",
SMLSD_X_HI: "SMLSD.X.HI",
SMLSD_X_LS: "SMLSD.X.LS",
SMLSD_X_GE: "SMLSD.X.GE",
SMLSD_X_LT: "SMLSD.X.LT",
SMLSD_X_GT: "SMLSD.X.GT",
SMLSD_X_LE: "SMLSD.X.LE",
SMLSD_X: "SMLSD.X",
SMLSD_X_ZZ: "SMLSD.X.ZZ",
SMLSLD_EQ: "SMLSLD.EQ",
SMLSLD_NE: "SMLSLD.NE",
SMLSLD_CS: "SMLSLD.CS",
SMLSLD_CC: "SMLSLD.CC",
SMLSLD_MI: "SMLSLD.MI",
SMLSLD_PL: "SMLSLD.PL",
SMLSLD_VS: "SMLSLD.VS",
SMLSLD_VC: "SMLSLD.VC",
SMLSLD_HI: "SMLSLD.HI",
SMLSLD_LS: "SMLSLD.LS",
SMLSLD_GE: "SMLSLD.GE",
SMLSLD_LT: "SMLSLD.LT",
SMLSLD_GT: "SMLSLD.GT",
SMLSLD_LE: "SMLSLD.LE",
SMLSLD: "SMLSLD",
SMLSLD_ZZ: "SMLSLD.ZZ",
SMLSLD_X_EQ: "SMLSLD.X.EQ",
SMLSLD_X_NE: "SMLSLD.X.NE",
SMLSLD_X_CS: "SMLSLD.X.CS",
SMLSLD_X_CC: "SMLSLD.X.CC",
SMLSLD_X_MI: "SMLSLD.X.MI",
SMLSLD_X_PL: "SMLSLD.X.PL",
SMLSLD_X_VS: "SMLSLD.X.VS",
SMLSLD_X_VC: "SMLSLD.X.VC",
SMLSLD_X_HI: "SMLSLD.X.HI",
SMLSLD_X_LS: "SMLSLD.X.LS",
SMLSLD_X_GE: "SMLSLD.X.GE",
SMLSLD_X_LT: "SMLSLD.X.LT",
SMLSLD_X_GT: "SMLSLD.X.GT",
SMLSLD_X_LE: "SMLSLD.X.LE",
SMLSLD_X: "SMLSLD.X",
SMLSLD_X_ZZ: "SMLSLD.X.ZZ",
SMMLA_EQ: "SMMLA.EQ",
SMMLA_NE: "SMMLA.NE",
SMMLA_CS: "SMMLA.CS",
SMMLA_CC: "SMMLA.CC",
SMMLA_MI: "SMMLA.MI",
SMMLA_PL: "SMMLA.PL",
SMMLA_VS: "SMMLA.VS",
SMMLA_VC: "SMMLA.VC",
SMMLA_HI: "SMMLA.HI",
SMMLA_LS: "SMMLA.LS",
SMMLA_GE: "SMMLA.GE",
SMMLA_LT: "SMMLA.LT",
SMMLA_GT: "SMMLA.GT",
SMMLA_LE: "SMMLA.LE",
SMMLA: "SMMLA",
SMMLA_ZZ: "SMMLA.ZZ",
SMMLA_R_EQ: "SMMLA.R.EQ",
SMMLA_R_NE: "SMMLA.R.NE",
SMMLA_R_CS: "SMMLA.R.CS",
SMMLA_R_CC: "SMMLA.R.CC",
SMMLA_R_MI: "SMMLA.R.MI",
SMMLA_R_PL: "SMMLA.R.PL",
SMMLA_R_VS: "SMMLA.R.VS",
SMMLA_R_VC: "SMMLA.R.VC",
SMMLA_R_HI: "SMMLA.R.HI",
SMMLA_R_LS: "SMMLA.R.LS",
SMMLA_R_GE: "SMMLA.R.GE",
SMMLA_R_LT: "SMMLA.R.LT",
SMMLA_R_GT: "SMMLA.R.GT",
SMMLA_R_LE: "SMMLA.R.LE",
SMMLA_R: "SMMLA.R",
SMMLA_R_ZZ: "SMMLA.R.ZZ",
SMMLS_EQ: "SMMLS.EQ",
SMMLS_NE: "SMMLS.NE",
SMMLS_CS: "SMMLS.CS",
SMMLS_CC: "SMMLS.CC",
SMMLS_MI: "SMMLS.MI",
SMMLS_PL: "SMMLS.PL",
SMMLS_VS: "SMMLS.VS",
SMMLS_VC: "SMMLS.VC",
SMMLS_HI: "SMMLS.HI",
SMMLS_LS: "SMMLS.LS",
SMMLS_GE: "SMMLS.GE",
SMMLS_LT: "SMMLS.LT",
SMMLS_GT: "SMMLS.GT",
SMMLS_LE: "SMMLS.LE",
SMMLS: "SMMLS",
SMMLS_ZZ: "SMMLS.ZZ",
SMMLS_R_EQ: "SMMLS.R.EQ",
SMMLS_R_NE: "SMMLS.R.NE",
SMMLS_R_CS: "SMMLS.R.CS",
SMMLS_R_CC: "SMMLS.R.CC",
SMMLS_R_MI: "SMMLS.R.MI",
SMMLS_R_PL: "SMMLS.R.PL",
SMMLS_R_VS: "SMMLS.R.VS",
SMMLS_R_VC: "SMMLS.R.VC",
SMMLS_R_HI: "SMMLS.R.HI",
SMMLS_R_LS: "SMMLS.R.LS",
SMMLS_R_GE: "SMMLS.R.GE",
SMMLS_R_LT: "SMMLS.R.LT",
SMMLS_R_GT: "SMMLS.R.GT",
SMMLS_R_LE: "SMMLS.R.LE",
SMMLS_R: "SMMLS.R",
SMMLS_R_ZZ: "SMMLS.R.ZZ",
SMMUL_EQ: "SMMUL.EQ",
SMMUL_NE: "SMMUL.NE",
SMMUL_CS: "SMMUL.CS",
SMMUL_CC: "SMMUL.CC",
SMMUL_MI: "SMMUL.MI",
SMMUL_PL: "SMMUL.PL",
SMMUL_VS: "SMMUL.VS",
SMMUL_VC: "SMMUL.VC",
SMMUL_HI: "SMMUL.HI",
SMMUL_LS: "SMMUL.LS",
SMMUL_GE: "SMMUL.GE",
SMMUL_LT: "SMMUL.LT",
SMMUL_GT: "SMMUL.GT",
SMMUL_LE: "SMMUL.LE",
SMMUL: "SMMUL",
SMMUL_ZZ: "SMMUL.ZZ",
SMMUL_R_EQ: "SMMUL.R.EQ",
SMMUL_R_NE: "SMMUL.R.NE",
SMMUL_R_CS: "SMMUL.R.CS",
SMMUL_R_CC: "SMMUL.R.CC",
SMMUL_R_MI: "SMMUL.R.MI",
SMMUL_R_PL: "SMMUL.R.PL",
SMMUL_R_VS: "SMMUL.R.VS",
SMMUL_R_VC: "SMMUL.R.VC",
SMMUL_R_HI: "SMMUL.R.HI",
SMMUL_R_LS: "SMMUL.R.LS",
SMMUL_R_GE: "SMMUL.R.GE",
SMMUL_R_LT: "SMMUL.R.LT",
SMMUL_R_GT: "SMMUL.R.GT",
SMMUL_R_LE: "SMMUL.R.LE",
SMMUL_R: "SMMUL.R",
SMMUL_R_ZZ: "SMMUL.R.ZZ",
SMUAD_EQ: "SMUAD.EQ",
SMUAD_NE: "SMUAD.NE",
SMUAD_CS: "SMUAD.CS",
SMUAD_CC: "SMUAD.CC",
SMUAD_MI: "SMUAD.MI",
SMUAD_PL: "SMUAD.PL",
SMUAD_VS: "SMUAD.VS",
SMUAD_VC: "SMUAD.VC",
SMUAD_HI: "SMUAD.HI",
SMUAD_LS: "SMUAD.LS",
SMUAD_GE: "SMUAD.GE",
SMUAD_LT: "SMUAD.LT",
SMUAD_GT: "SMUAD.GT",
SMUAD_LE: "SMUAD.LE",
SMUAD: "SMUAD",
SMUAD_ZZ: "SMUAD.ZZ",
SMUAD_X_EQ: "SMUAD.X.EQ",
SMUAD_X_NE: "SMUAD.X.NE",
SMUAD_X_CS: "SMUAD.X.CS",
SMUAD_X_CC: "SMUAD.X.CC",
SMUAD_X_MI: "SMUAD.X.MI",
SMUAD_X_PL: "SMUAD.X.PL",
SMUAD_X_VS: "SMUAD.X.VS",
SMUAD_X_VC: "SMUAD.X.VC",
SMUAD_X_HI: "SMUAD.X.HI",
SMUAD_X_LS: "SMUAD.X.LS",
SMUAD_X_GE: "SMUAD.X.GE",
SMUAD_X_LT: "SMUAD.X.LT",
SMUAD_X_GT: "SMUAD.X.GT",
SMUAD_X_LE: "SMUAD.X.LE",
SMUAD_X: "SMUAD.X",
SMUAD_X_ZZ: "SMUAD.X.ZZ",
SMULBB_EQ: "SMULBB.EQ",
SMULBB_NE: "SMULBB.NE",
SMULBB_CS: "SMULBB.CS",
SMULBB_CC: "SMULBB.CC",
SMULBB_MI: "SMULBB.MI",
SMULBB_PL: "SMULBB.PL",
SMULBB_VS: "SMULBB.VS",
SMULBB_VC: "SMULBB.VC",
SMULBB_HI: "SMULBB.HI",
SMULBB_LS: "SMULBB.LS",
SMULBB_GE: "SMULBB.GE",
SMULBB_LT: "SMULBB.LT",
SMULBB_GT: "SMULBB.GT",
SMULBB_LE: "SMULBB.LE",
SMULBB: "SMULBB",
SMULBB_ZZ: "SMULBB.ZZ",
SMULBT_EQ: "SMULBT.EQ",
SMULBT_NE: "SMULBT.NE",
SMULBT_CS: "SMULBT.CS",
SMULBT_CC: "SMULBT.CC",
SMULBT_MI: "SMULBT.MI",
SMULBT_PL: "SMULBT.PL",
SMULBT_VS: "SMULBT.VS",
SMULBT_VC: "SMULBT.VC",
SMULBT_HI: "SMULBT.HI",
SMULBT_LS: "SMULBT.LS",
SMULBT_GE: "SMULBT.GE",
SMULBT_LT: "SMULBT.LT",
SMULBT_GT: "SMULBT.GT",
SMULBT_LE: "SMULBT.LE",
SMULBT: "SMULBT",
SMULBT_ZZ: "SMULBT.ZZ",
SMULTB_EQ: "SMULTB.EQ",
SMULTB_NE: "SMULTB.NE",
SMULTB_CS: "SMULTB.CS",
SMULTB_CC: "SMULTB.CC",
SMULTB_MI: "SMULTB.MI",
SMULTB_PL: "SMULTB.PL",
SMULTB_VS: "SMULTB.VS",
SMULTB_VC: "SMULTB.VC",
SMULTB_HI: "SMULTB.HI",
SMULTB_LS: "SMULTB.LS",
SMULTB_GE: "SMULTB.GE",
SMULTB_LT: "SMULTB.LT",
SMULTB_GT: "SMULTB.GT",
SMULTB_LE: "SMULTB.LE",
SMULTB: "SMULTB",
SMULTB_ZZ: "SMULTB.ZZ",
SMULTT_EQ: "SMULTT.EQ",
SMULTT_NE: "SMULTT.NE",
SMULTT_CS: "SMULTT.CS",
SMULTT_CC: "SMULTT.CC",
SMULTT_MI: "SMULTT.MI",
SMULTT_PL: "SMULTT.PL",
SMULTT_VS: "SMULTT.VS",
SMULTT_VC: "SMULTT.VC",
SMULTT_HI: "SMULTT.HI",
SMULTT_LS: "SMULTT.LS",
SMULTT_GE: "SMULTT.GE",
SMULTT_LT: "SMULTT.LT",
SMULTT_GT: "SMULTT.GT",
SMULTT_LE: "SMULTT.LE",
SMULTT: "SMULTT",
SMULTT_ZZ: "SMULTT.ZZ",
SMULL_EQ: "SMULL.EQ",
SMULL_NE: "SMULL.NE",
SMULL_CS: "SMULL.CS",
SMULL_CC: "SMULL.CC",
SMULL_MI: "SMULL.MI",
SMULL_PL: "SMULL.PL",
SMULL_VS: "SMULL.VS",
SMULL_VC: "SMULL.VC",
SMULL_HI: "SMULL.HI",
SMULL_LS: "SMULL.LS",
SMULL_GE: "SMULL.GE",
SMULL_LT: "SMULL.LT",
SMULL_GT: "SMULL.GT",
SMULL_LE: "SMULL.LE",
SMULL: "SMULL",
SMULL_ZZ: "SMULL.ZZ",
SMULL_S_EQ: "SMULL.S.EQ",
SMULL_S_NE: "SMULL.S.NE",
SMULL_S_CS: "SMULL.S.CS",
SMULL_S_CC: "SMULL.S.CC",
SMULL_S_MI: "SMULL.S.MI",
SMULL_S_PL: "SMULL.S.PL",
SMULL_S_VS: "SMULL.S.VS",
SMULL_S_VC: "SMULL.S.VC",
SMULL_S_HI: "SMULL.S.HI",
SMULL_S_LS: "SMULL.S.LS",
SMULL_S_GE: "SMULL.S.GE",
SMULL_S_LT: "SMULL.S.LT",
SMULL_S_GT: "SMULL.S.GT",
SMULL_S_LE: "SMULL.S.LE",
SMULL_S: "SMULL.S",
SMULL_S_ZZ: "SMULL.S.ZZ",
SMULWB_EQ: "SMULWB.EQ",
SMULWB_NE: "SMULWB.NE",
SMULWB_CS: "SMULWB.CS",
SMULWB_CC: "SMULWB.CC",
SMULWB_MI: "SMULWB.MI",
SMULWB_PL: "SMULWB.PL",
SMULWB_VS: "SMULWB.VS",
SMULWB_VC: "SMULWB.VC",
SMULWB_HI: "SMULWB.HI",
SMULWB_LS: "SMULWB.LS",
SMULWB_GE: "SMULWB.GE",
SMULWB_LT: "SMULWB.LT",
SMULWB_GT: "SMULWB.GT",
SMULWB_LE: "SMULWB.LE",
SMULWB: "SMULWB",
SMULWB_ZZ: "SMULWB.ZZ",
SMULWT_EQ: "SMULWT.EQ",
SMULWT_NE: "SMULWT.NE",
SMULWT_CS: "SMULWT.CS",
SMULWT_CC: "SMULWT.CC",
SMULWT_MI: "SMULWT.MI",
SMULWT_PL: "SMULWT.PL",
SMULWT_VS: "SMULWT.VS",
SMULWT_VC: "SMULWT.VC",
SMULWT_HI: "SMULWT.HI",
SMULWT_LS: "SMULWT.LS",
SMULWT_GE: "SMULWT.GE",
SMULWT_LT: "SMULWT.LT",
SMULWT_GT: "SMULWT.GT",
SMULWT_LE: "SMULWT.LE",
SMULWT: "SMULWT",
SMULWT_ZZ: "SMULWT.ZZ",
SMUSD_EQ: "SMUSD.EQ",
SMUSD_NE: "SMUSD.NE",
SMUSD_CS: "SMUSD.CS",
SMUSD_CC: "SMUSD.CC",
SMUSD_MI: "SMUSD.MI",
SMUSD_PL: "SMUSD.PL",
SMUSD_VS: "SMUSD.VS",
SMUSD_VC: "SMUSD.VC",
SMUSD_HI: "SMUSD.HI",
SMUSD_LS: "SMUSD.LS",
SMUSD_GE: "SMUSD.GE",
SMUSD_LT: "SMUSD.LT",
SMUSD_GT: "SMUSD.GT",
SMUSD_LE: "SMUSD.LE",
SMUSD: "SMUSD",
SMUSD_ZZ: "SMUSD.ZZ",
SMUSD_X_EQ: "SMUSD.X.EQ",
SMUSD_X_NE: "SMUSD.X.NE",
SMUSD_X_CS: "SMUSD.X.CS",
SMUSD_X_CC: "SMUSD.X.CC",
SMUSD_X_MI: "SMUSD.X.MI",
SMUSD_X_PL: "SMUSD.X.PL",
SMUSD_X_VS: "SMUSD.X.VS",
SMUSD_X_VC: "SMUSD.X.VC",
SMUSD_X_HI: "SMUSD.X.HI",
SMUSD_X_LS: "SMUSD.X.LS",
SMUSD_X_GE: "SMUSD.X.GE",
SMUSD_X_LT: "SMUSD.X.LT",
SMUSD_X_GT: "SMUSD.X.GT",
SMUSD_X_LE: "SMUSD.X.LE",
SMUSD_X: "SMUSD.X",
SMUSD_X_ZZ: "SMUSD.X.ZZ",
SSAT_EQ: "SSAT.EQ",
SSAT_NE: "SSAT.NE",
SSAT_CS: "SSAT.CS",
SSAT_CC: "SSAT.CC",
SSAT_MI: "SSAT.MI",
SSAT_PL: "SSAT.PL",
SSAT_VS: "SSAT.VS",
SSAT_VC: "SSAT.VC",
SSAT_HI: "SSAT.HI",
SSAT_LS: "SSAT.LS",
SSAT_GE: "SSAT.GE",
SSAT_LT: "SSAT.LT",
SSAT_GT: "SSAT.GT",
SSAT_LE: "SSAT.LE",
SSAT: "SSAT",
SSAT_ZZ: "SSAT.ZZ",
SSAT16_EQ: "SSAT16.EQ",
SSAT16_NE: "SSAT16.NE",
SSAT16_CS: "SSAT16.CS",
SSAT16_CC: "SSAT16.CC",
SSAT16_MI: "SSAT16.MI",
SSAT16_PL: "SSAT16.PL",
SSAT16_VS: "SSAT16.VS",
SSAT16_VC: "SSAT16.VC",
SSAT16_HI: "SSAT16.HI",
SSAT16_LS: "SSAT16.LS",
SSAT16_GE: "SSAT16.GE",
SSAT16_LT: "SSAT16.LT",
SSAT16_GT: "SSAT16.GT",
SSAT16_LE: "SSAT16.LE",
SSAT16: "SSAT16",
SSAT16_ZZ: "SSAT16.ZZ",
SSAX_EQ: "SSAX.EQ",
SSAX_NE: "SSAX.NE",
SSAX_CS: "SSAX.CS",
SSAX_CC: "SSAX.CC",
SSAX_MI: "SSAX.MI",
SSAX_PL: "SSAX.PL",
SSAX_VS: "SSAX.VS",
SSAX_VC: "SSAX.VC",
SSAX_HI: "SSAX.HI",
SSAX_LS: "SSAX.LS",
SSAX_GE: "SSAX.GE",
SSAX_LT: "SSAX.LT",
SSAX_GT: "SSAX.GT",
SSAX_LE: "SSAX.LE",
SSAX: "SSAX",
SSAX_ZZ: "SSAX.ZZ",
SSUB16_EQ: "SSUB16.EQ",
SSUB16_NE: "SSUB16.NE",
SSUB16_CS: "SSUB16.CS",
SSUB16_CC: "SSUB16.CC",
SSUB16_MI: "SSUB16.MI",
SSUB16_PL: "SSUB16.PL",
SSUB16_VS: "SSUB16.VS",
SSUB16_VC: "SSUB16.VC",
SSUB16_HI: "SSUB16.HI",
SSUB16_LS: "SSUB16.LS",
SSUB16_GE: "SSUB16.GE",
SSUB16_LT: "SSUB16.LT",
SSUB16_GT: "SSUB16.GT",
SSUB16_LE: "SSUB16.LE",
SSUB16: "SSUB16",
SSUB16_ZZ: "SSUB16.ZZ",
SSUB8_EQ: "SSUB8.EQ",
SSUB8_NE: "SSUB8.NE",
SSUB8_CS: "SSUB8.CS",
SSUB8_CC: "SSUB8.CC",
SSUB8_MI: "SSUB8.MI",
SSUB8_PL: "SSUB8.PL",
SSUB8_VS: "SSUB8.VS",
SSUB8_VC: "SSUB8.VC",
SSUB8_HI: "SSUB8.HI",
SSUB8_LS: "SSUB8.LS",
SSUB8_GE: "SSUB8.GE",
SSUB8_LT: "SSUB8.LT",
SSUB8_GT: "SSUB8.GT",
SSUB8_LE: "SSUB8.LE",
SSUB8: "SSUB8",
SSUB8_ZZ: "SSUB8.ZZ",
STM_EQ: "STM.EQ",
STM_NE: "STM.NE",
STM_CS: "STM.CS",
STM_CC: "STM.CC",
STM_MI: "STM.MI",
STM_PL: "STM.PL",
STM_VS: "STM.VS",
STM_VC: "STM.VC",
STM_HI: "STM.HI",
STM_LS: "STM.LS",
STM_GE: "STM.GE",
STM_LT: "STM.LT",
STM_GT: "STM.GT",
STM_LE: "STM.LE",
STM: "STM",
STM_ZZ: "STM.ZZ",
STMDA_EQ: "STMDA.EQ",
STMDA_NE: "STMDA.NE",
STMDA_CS: "STMDA.CS",
STMDA_CC: "STMDA.CC",
STMDA_MI: "STMDA.MI",
STMDA_PL: "STMDA.PL",
STMDA_VS: "STMDA.VS",
STMDA_VC: "STMDA.VC",
STMDA_HI: "STMDA.HI",
STMDA_LS: "STMDA.LS",
STMDA_GE: "STMDA.GE",
STMDA_LT: "STMDA.LT",
STMDA_GT: "STMDA.GT",
STMDA_LE: "STMDA.LE",
STMDA: "STMDA",
STMDA_ZZ: "STMDA.ZZ",
STMDB_EQ: "STMDB.EQ",
STMDB_NE: "STMDB.NE",
STMDB_CS: "STMDB.CS",
STMDB_CC: "STMDB.CC",
STMDB_MI: "STMDB.MI",
STMDB_PL: "STMDB.PL",
STMDB_VS: "STMDB.VS",
STMDB_VC: "STMDB.VC",
STMDB_HI: "STMDB.HI",
STMDB_LS: "STMDB.LS",
STMDB_GE: "STMDB.GE",
STMDB_LT: "STMDB.LT",
STMDB_GT: "STMDB.GT",
STMDB_LE: "STMDB.LE",
STMDB: "STMDB",
STMDB_ZZ: "STMDB.ZZ",
STMIB_EQ: "STMIB.EQ",
STMIB_NE: "STMIB.NE",
STMIB_CS: "STMIB.CS",
STMIB_CC: "STMIB.CC",
STMIB_MI: "STMIB.MI",
STMIB_PL: "STMIB.PL",
STMIB_VS: "STMIB.VS",
STMIB_VC: "STMIB.VC",
STMIB_HI: "STMIB.HI",
STMIB_LS: "STMIB.LS",
STMIB_GE: "STMIB.GE",
STMIB_LT: "STMIB.LT",
STMIB_GT: "STMIB.GT",
STMIB_LE: "STMIB.LE",
STMIB: "STMIB",
STMIB_ZZ: "STMIB.ZZ",
STR_EQ: "STR.EQ",
STR_NE: "STR.NE",
STR_CS: "STR.CS",
STR_CC: "STR.CC",
STR_MI: "STR.MI",
STR_PL: "STR.PL",
STR_VS: "STR.VS",
STR_VC: "STR.VC",
STR_HI: "STR.HI",
STR_LS: "STR.LS",
STR_GE: "STR.GE",
STR_LT: "STR.LT",
STR_GT: "STR.GT",
STR_LE: "STR.LE",
STR: "STR",
STR_ZZ: "STR.ZZ",
STRB_EQ: "STRB.EQ",
STRB_NE: "STRB.NE",
STRB_CS: "STRB.CS",
STRB_CC: "STRB.CC",
STRB_MI: "STRB.MI",
STRB_PL: "STRB.PL",
STRB_VS: "STRB.VS",
STRB_VC: "STRB.VC",
STRB_HI: "STRB.HI",
STRB_LS: "STRB.LS",
STRB_GE: "STRB.GE",
STRB_LT: "STRB.LT",
STRB_GT: "STRB.GT",
STRB_LE: "STRB.LE",
STRB: "STRB",
STRB_ZZ: "STRB.ZZ",
STRBT_EQ: "STRBT.EQ",
STRBT_NE: "STRBT.NE",
STRBT_CS: "STRBT.CS",
STRBT_CC: "STRBT.CC",
STRBT_MI: "STRBT.MI",
STRBT_PL: "STRBT.PL",
STRBT_VS: "STRBT.VS",
STRBT_VC: "STRBT.VC",
STRBT_HI: "STRBT.HI",
STRBT_LS: "STRBT.LS",
STRBT_GE: "STRBT.GE",
STRBT_LT: "STRBT.LT",
STRBT_GT: "STRBT.GT",
STRBT_LE: "STRBT.LE",
STRBT: "STRBT",
STRBT_ZZ: "STRBT.ZZ",
STRD_EQ: "STRD.EQ",
STRD_NE: "STRD.NE",
STRD_CS: "STRD.CS",
STRD_CC: "STRD.CC",
STRD_MI: "STRD.MI",
STRD_PL: "STRD.PL",
STRD_VS: "STRD.VS",
STRD_VC: "STRD.VC",
STRD_HI: "STRD.HI",
STRD_LS: "STRD.LS",
STRD_GE: "STRD.GE",
STRD_LT: "STRD.LT",
STRD_GT: "STRD.GT",
STRD_LE: "STRD.LE",
STRD: "STRD",
STRD_ZZ: "STRD.ZZ",
STREX_EQ: "STREX.EQ",
STREX_NE: "STREX.NE",
STREX_CS: "STREX.CS",
STREX_CC: "STREX.CC",
STREX_MI: "STREX.MI",
STREX_PL: "STREX.PL",
STREX_VS: "STREX.VS",
STREX_VC: "STREX.VC",
STREX_HI: "STREX.HI",
STREX_LS: "STREX.LS",
STREX_GE: "STREX.GE",
STREX_LT: "STREX.LT",
STREX_GT: "STREX.GT",
STREX_LE: "STREX.LE",
STREX: "STREX",
STREX_ZZ: "STREX.ZZ",
STREXB_EQ: "STREXB.EQ",
STREXB_NE: "STREXB.NE",
STREXB_CS: "STREXB.CS",
STREXB_CC: "STREXB.CC",
STREXB_MI: "STREXB.MI",
STREXB_PL: "STREXB.PL",
STREXB_VS: "STREXB.VS",
STREXB_VC: "STREXB.VC",
STREXB_HI: "STREXB.HI",
STREXB_LS: "STREXB.LS",
STREXB_GE: "STREXB.GE",
STREXB_LT: "STREXB.LT",
STREXB_GT: "STREXB.GT",
STREXB_LE: "STREXB.LE",
STREXB: "STREXB",
STREXB_ZZ: "STREXB.ZZ",
STREXD_EQ: "STREXD.EQ",
STREXD_NE: "STREXD.NE",
STREXD_CS: "STREXD.CS",
STREXD_CC: "STREXD.CC",
STREXD_MI: "STREXD.MI",
STREXD_PL: "STREXD.PL",
STREXD_VS: "STREXD.VS",
STREXD_VC: "STREXD.VC",
STREXD_HI: "STREXD.HI",
STREXD_LS: "STREXD.LS",
STREXD_GE: "STREXD.GE",
STREXD_LT: "STREXD.LT",
STREXD_GT: "STREXD.GT",
STREXD_LE: "STREXD.LE",
STREXD: "STREXD",
STREXD_ZZ: "STREXD.ZZ",
STREXH_EQ: "STREXH.EQ",
STREXH_NE: "STREXH.NE",
STREXH_CS: "STREXH.CS",
STREXH_CC: "STREXH.CC",
STREXH_MI: "STREXH.MI",
STREXH_PL: "STREXH.PL",
STREXH_VS: "STREXH.VS",
STREXH_VC: "STREXH.VC",
STREXH_HI: "STREXH.HI",
STREXH_LS: "STREXH.LS",
STREXH_GE: "STREXH.GE",
STREXH_LT: "STREXH.LT",
STREXH_GT: "STREXH.GT",
STREXH_LE: "STREXH.LE",
STREXH: "STREXH",
STREXH_ZZ: "STREXH.ZZ",
STRH_EQ: "STRH.EQ",
STRH_NE: "STRH.NE",
STRH_CS: "STRH.CS",
STRH_CC: "STRH.CC",
STRH_MI: "STRH.MI",
STRH_PL: "STRH.PL",
STRH_VS: "STRH.VS",
STRH_VC: "STRH.VC",
STRH_HI: "STRH.HI",
STRH_LS: "STRH.LS",
STRH_GE: "STRH.GE",
STRH_LT: "STRH.LT",
STRH_GT: "STRH.GT",
STRH_LE: "STRH.LE",
STRH: "STRH",
STRH_ZZ: "STRH.ZZ",
STRHT_EQ: "STRHT.EQ",
STRHT_NE: "STRHT.NE",
STRHT_CS: "STRHT.CS",
STRHT_CC: "STRHT.CC",
STRHT_MI: "STRHT.MI",
STRHT_PL: "STRHT.PL",
STRHT_VS: "STRHT.VS",
STRHT_VC: "STRHT.VC",
STRHT_HI: "STRHT.HI",
STRHT_LS: "STRHT.LS",
STRHT_GE: "STRHT.GE",
STRHT_LT: "STRHT.LT",
STRHT_GT: "STRHT.GT",
STRHT_LE: "STRHT.LE",
STRHT: "STRHT",
STRHT_ZZ: "STRHT.ZZ",
STRT_EQ: "STRT.EQ",
STRT_NE: "STRT.NE",
STRT_CS: "STRT.CS",
STRT_CC: "STRT.CC",
STRT_MI: "STRT.MI",
STRT_PL: "STRT.PL",
STRT_VS: "STRT.VS",
STRT_VC: "STRT.VC",
STRT_HI: "STRT.HI",
STRT_LS: "STRT.LS",
STRT_GE: "STRT.GE",
STRT_LT: "STRT.LT",
STRT_GT: "STRT.GT",
STRT_LE: "STRT.LE",
STRT: "STRT",
STRT_ZZ: "STRT.ZZ",
SUB_EQ: "SUB.EQ",
SUB_NE: "SUB.NE",
SUB_CS: "SUB.CS",
SUB_CC: "SUB.CC",
SUB_MI: "SUB.MI",
SUB_PL: "SUB.PL",
SUB_VS: "SUB.VS",
SUB_VC: "SUB.VC",
SUB_HI: "SUB.HI",
SUB_LS: "SUB.LS",
SUB_GE: "SUB.GE",
SUB_LT: "SUB.LT",
SUB_GT: "SUB.GT",
SUB_LE: "SUB.LE",
SUB: "SUB",
SUB_ZZ: "SUB.ZZ",
SUB_S_EQ: "SUB.S.EQ",
SUB_S_NE: "SUB.S.NE",
SUB_S_CS: "SUB.S.CS",
SUB_S_CC: "SUB.S.CC",
SUB_S_MI: "SUB.S.MI",
SUB_S_PL: "SUB.S.PL",
SUB_S_VS: "SUB.S.VS",
SUB_S_VC: "SUB.S.VC",
SUB_S_HI: "SUB.S.HI",
SUB_S_LS: "SUB.S.LS",
SUB_S_GE: "SUB.S.GE",
SUB_S_LT: "SUB.S.LT",
SUB_S_GT: "SUB.S.GT",
SUB_S_LE: "SUB.S.LE",
SUB_S: "SUB.S",
SUB_S_ZZ: "SUB.S.ZZ",
SVC_EQ: "SVC.EQ",
SVC_NE: "SVC.NE",
SVC_CS: "SVC.CS",
SVC_CC: "SVC.CC",
SVC_MI: "SVC.MI",
SVC_PL: "SVC.PL",
SVC_VS: "SVC.VS",
SVC_VC: "SVC.VC",
SVC_HI: "SVC.HI",
SVC_LS: "SVC.LS",
SVC_GE: "SVC.GE",
SVC_LT: "SVC.LT",
SVC_GT: "SVC.GT",
SVC_LE: "SVC.LE",
SVC: "SVC",
SVC_ZZ: "SVC.ZZ",
SWP_EQ: "SWP.EQ",
SWP_NE: "SWP.NE",
SWP_CS: "SWP.CS",
SWP_CC: "SWP.CC",
SWP_MI: "SWP.MI",
SWP_PL: "SWP.PL",
SWP_VS: "SWP.VS",
SWP_VC: "SWP.VC",
SWP_HI: "SWP.HI",
SWP_LS: "SWP.LS",
SWP_GE: "SWP.GE",
SWP_LT: "SWP.LT",
SWP_GT: "SWP.GT",
SWP_LE: "SWP.LE",
SWP: "SWP",
SWP_ZZ: "SWP.ZZ",
SWP_B_EQ: "SWP.B.EQ",
SWP_B_NE: "SWP.B.NE",
SWP_B_CS: "SWP.B.CS",
SWP_B_CC: "SWP.B.CC",
SWP_B_MI: "SWP.B.MI",
SWP_B_PL: "SWP.B.PL",
SWP_B_VS: "SWP.B.VS",
SWP_B_VC: "SWP.B.VC",
SWP_B_HI: "SWP.B.HI",
SWP_B_LS: "SWP.B.LS",
SWP_B_GE: "SWP.B.GE",
SWP_B_LT: "SWP.B.LT",
SWP_B_GT: "SWP.B.GT",
SWP_B_LE: "SWP.B.LE",
SWP_B: "SWP.B",
SWP_B_ZZ: "SWP.B.ZZ",
SXTAB_EQ: "SXTAB.EQ",
SXTAB_NE: "SXTAB.NE",
SXTAB_CS: "SXTAB.CS",
SXTAB_CC: "SXTAB.CC",
SXTAB_MI: "SXTAB.MI",
SXTAB_PL: "SXTAB.PL",
SXTAB_VS: "SXTAB.VS",
SXTAB_VC: "SXTAB.VC",
SXTAB_HI: "SXTAB.HI",
SXTAB_LS: "SXTAB.LS",
SXTAB_GE: "SXTAB.GE",
SXTAB_LT: "SXTAB.LT",
SXTAB_GT: "SXTAB.GT",
SXTAB_LE: "SXTAB.LE",
SXTAB: "SXTAB",
SXTAB_ZZ: "SXTAB.ZZ",
SXTAB16_EQ: "SXTAB16.EQ",
SXTAB16_NE: "SXTAB16.NE",
SXTAB16_CS: "SXTAB16.CS",
SXTAB16_CC: "SXTAB16.CC",
SXTAB16_MI: "SXTAB16.MI",
SXTAB16_PL: "SXTAB16.PL",
SXTAB16_VS: "SXTAB16.VS",
SXTAB16_VC: "SXTAB16.VC",
SXTAB16_HI: "SXTAB16.HI",
SXTAB16_LS: "SXTAB16.LS",
SXTAB16_GE: "SXTAB16.GE",
SXTAB16_LT: "SXTAB16.LT",
SXTAB16_GT: "SXTAB16.GT",
SXTAB16_LE: "SXTAB16.LE",
SXTAB16: "SXTAB16",
SXTAB16_ZZ: "SXTAB16.ZZ",
SXTAH_EQ: "SXTAH.EQ",
SXTAH_NE: "SXTAH.NE",
SXTAH_CS: "SXTAH.CS",
SXTAH_CC: "SXTAH.CC",
SXTAH_MI: "SXTAH.MI",
SXTAH_PL: "SXTAH.PL",
SXTAH_VS: "SXTAH.VS",
SXTAH_VC: "SXTAH.VC",
SXTAH_HI: "SXTAH.HI",
SXTAH_LS: "SXTAH.LS",
SXTAH_GE: "SXTAH.GE",
SXTAH_LT: "SXTAH.LT",
SXTAH_GT: "SXTAH.GT",
SXTAH_LE: "SXTAH.LE",
SXTAH: "SXTAH",
SXTAH_ZZ: "SXTAH.ZZ",
SXTB_EQ: "SXTB.EQ",
SXTB_NE: "SXTB.NE",
SXTB_CS: "SXTB.CS",
SXTB_CC: "SXTB.CC",
SXTB_MI: "SXTB.MI",
SXTB_PL: "SXTB.PL",
SXTB_VS: "SXTB.VS",
SXTB_VC: "SXTB.VC",
SXTB_HI: "SXTB.HI",
SXTB_LS: "SXTB.LS",
SXTB_GE: "SXTB.GE",
SXTB_LT: "SXTB.LT",
SXTB_GT: "SXTB.GT",
SXTB_LE: "SXTB.LE",
SXTB: "SXTB",
SXTB_ZZ: "SXTB.ZZ",
SXTB16_EQ: "SXTB16.EQ",
SXTB16_NE: "SXTB16.NE",
SXTB16_CS: "SXTB16.CS",
SXTB16_CC: "SXTB16.CC",
SXTB16_MI: "SXTB16.MI",
SXTB16_PL: "SXTB16.PL",
SXTB16_VS: "SXTB16.VS",
SXTB16_VC: "SXTB16.VC",
SXTB16_HI: "SXTB16.HI",
SXTB16_LS: "SXTB16.LS",
SXTB16_GE: "SXTB16.GE",
SXTB16_LT: "SXTB16.LT",
SXTB16_GT: "SXTB16.GT",
SXTB16_LE: "SXTB16.LE",
SXTB16: "SXTB16",
SXTB16_ZZ: "SXTB16.ZZ",
SXTH_EQ: "SXTH.EQ",
SXTH_NE: "SXTH.NE",
SXTH_CS: "SXTH.CS",
SXTH_CC: "SXTH.CC",
SXTH_MI: "SXTH.MI",
SXTH_PL: "SXTH.PL",
SXTH_VS: "SXTH.VS",
SXTH_VC: "SXTH.VC",
SXTH_HI: "SXTH.HI",
SXTH_LS: "SXTH.LS",
SXTH_GE: "SXTH.GE",
SXTH_LT: "SXTH.LT",
SXTH_GT: "SXTH.GT",
SXTH_LE: "SXTH.LE",
SXTH: "SXTH",
SXTH_ZZ: "SXTH.ZZ",
TEQ_EQ: "TEQ.EQ",
TEQ_NE: "TEQ.NE",
TEQ_CS: "TEQ.CS",
TEQ_CC: "TEQ.CC",
TEQ_MI: "TEQ.MI",
TEQ_PL: "TEQ.PL",
TEQ_VS: "TEQ.VS",
TEQ_VC: "TEQ.VC",
TEQ_HI: "TEQ.HI",
TEQ_LS: "TEQ.LS",
TEQ_GE: "TEQ.GE",
TEQ_LT: "TEQ.LT",
TEQ_GT: "TEQ.GT",
TEQ_LE: "TEQ.LE",
TEQ: "TEQ",
TEQ_ZZ: "TEQ.ZZ",
TST_EQ: "TST.EQ",
TST_NE: "TST.NE",
TST_CS: "TST.CS",
TST_CC: "TST.CC",
TST_MI: "TST.MI",
TST_PL: "TST.PL",
TST_VS: "TST.VS",
TST_VC: "TST.VC",
TST_HI: "TST.HI",
TST_LS: "TST.LS",
TST_GE: "TST.GE",
TST_LT: "TST.LT",
TST_GT: "TST.GT",
TST_LE: "TST.LE",
TST: "TST",
TST_ZZ: "TST.ZZ",
UADD16_EQ: "UADD16.EQ",
UADD16_NE: "UADD16.NE",
UADD16_CS: "UADD16.CS",
UADD16_CC: "UADD16.CC",
UADD16_MI: "UADD16.MI",
UADD16_PL: "UADD16.PL",
UADD16_VS: "UADD16.VS",
UADD16_VC: "UADD16.VC",
UADD16_HI: "UADD16.HI",
UADD16_LS: "UADD16.LS",
UADD16_GE: "UADD16.GE",
UADD16_LT: "UADD16.LT",
UADD16_GT: "UADD16.GT",
UADD16_LE: "UADD16.LE",
UADD16: "UADD16",
UADD16_ZZ: "UADD16.ZZ",
UADD8_EQ: "UADD8.EQ",
UADD8_NE: "UADD8.NE",
UADD8_CS: "UADD8.CS",
UADD8_CC: "UADD8.CC",
UADD8_MI: "UADD8.MI",
UADD8_PL: "UADD8.PL",
UADD8_VS: "UADD8.VS",
UADD8_VC: "UADD8.VC",
UADD8_HI: "UADD8.HI",
UADD8_LS: "UADD8.LS",
UADD8_GE: "UADD8.GE",
UADD8_LT: "UADD8.LT",
UADD8_GT: "UADD8.GT",
UADD8_LE: "UADD8.LE",
UADD8: "UADD8",
UADD8_ZZ: "UADD8.ZZ",
UASX_EQ: "UASX.EQ",
UASX_NE: "UASX.NE",
UASX_CS: "UASX.CS",
UASX_CC: "UASX.CC",
UASX_MI: "UASX.MI",
UASX_PL: "UASX.PL",
UASX_VS: "UASX.VS",
UASX_VC: "UASX.VC",
UASX_HI: "UASX.HI",
UASX_LS: "UASX.LS",
UASX_GE: "UASX.GE",
UASX_LT: "UASX.LT",
UASX_GT: "UASX.GT",
UASX_LE: "UASX.LE",
UASX: "UASX",
UASX_ZZ: "UASX.ZZ",
UBFX_EQ: "UBFX.EQ",
UBFX_NE: "UBFX.NE",
UBFX_CS: "UBFX.CS",
UBFX_CC: "UBFX.CC",
UBFX_MI: "UBFX.MI",
UBFX_PL: "UBFX.PL",
UBFX_VS: "UBFX.VS",
UBFX_VC: "UBFX.VC",
UBFX_HI: "UBFX.HI",
UBFX_LS: "UBFX.LS",
UBFX_GE: "UBFX.GE",
UBFX_LT: "UBFX.LT",
UBFX_GT: "UBFX.GT",
UBFX_LE: "UBFX.LE",
UBFX: "UBFX",
UBFX_ZZ: "UBFX.ZZ",
UHADD16_EQ: "UHADD16.EQ",
UHADD16_NE: "UHADD16.NE",
UHADD16_CS: "UHADD16.CS",
UHADD16_CC: "UHADD16.CC",
UHADD16_MI: "UHADD16.MI",
UHADD16_PL: "UHADD16.PL",
UHADD16_VS: "UHADD16.VS",
UHADD16_VC: "UHADD16.VC",
UHADD16_HI: "UHADD16.HI",
UHADD16_LS: "UHADD16.LS",
UHADD16_GE: "UHADD16.GE",
UHADD16_LT: "UHADD16.LT",
UHADD16_GT: "UHADD16.GT",
UHADD16_LE: "UHADD16.LE",
UHADD16: "UHADD16",
UHADD16_ZZ: "UHADD16.ZZ",
UHADD8_EQ: "UHADD8.EQ",
UHADD8_NE: "UHADD8.NE",
UHADD8_CS: "UHADD8.CS",
UHADD8_CC: "UHADD8.CC",
UHADD8_MI: "UHADD8.MI",
UHADD8_PL: "UHADD8.PL",
UHADD8_VS: "UHADD8.VS",
UHADD8_VC: "UHADD8.VC",
UHADD8_HI: "UHADD8.HI",
UHADD8_LS: "UHADD8.LS",
UHADD8_GE: "UHADD8.GE",
UHADD8_LT: "UHADD8.LT",
UHADD8_GT: "UHADD8.GT",
UHADD8_LE: "UHADD8.LE",
UHADD8: "UHADD8",
UHADD8_ZZ: "UHADD8.ZZ",
UHASX_EQ: "UHASX.EQ",
UHASX_NE: "UHASX.NE",
UHASX_CS: "UHASX.CS",
UHASX_CC: "UHASX.CC",
UHASX_MI: "UHASX.MI",
UHASX_PL: "UHASX.PL",
UHASX_VS: "UHASX.VS",
UHASX_VC: "UHASX.VC",
UHASX_HI: "UHASX.HI",
UHASX_LS: "UHASX.LS",
UHASX_GE: "UHASX.GE",
UHASX_LT: "UHASX.LT",
UHASX_GT: "UHASX.GT",
UHASX_LE: "UHASX.LE",
UHASX: "UHASX",
UHASX_ZZ: "UHASX.ZZ",
UHSAX_EQ: "UHSAX.EQ",
UHSAX_NE: "UHSAX.NE",
UHSAX_CS: "UHSAX.CS",
UHSAX_CC: "UHSAX.CC",
UHSAX_MI: "UHSAX.MI",
UHSAX_PL: "UHSAX.PL",
UHSAX_VS: "UHSAX.VS",
UHSAX_VC: "UHSAX.VC",
UHSAX_HI: "UHSAX.HI",
UHSAX_LS: "UHSAX.LS",
UHSAX_GE: "UHSAX.GE",
UHSAX_LT: "UHSAX.LT",
UHSAX_GT: "UHSAX.GT",
UHSAX_LE: "UHSAX.LE",
UHSAX: "UHSAX",
UHSAX_ZZ: "UHSAX.ZZ",
UHSUB16_EQ: "UHSUB16.EQ",
UHSUB16_NE: "UHSUB16.NE",
UHSUB16_CS: "UHSUB16.CS",
UHSUB16_CC: "UHSUB16.CC",
UHSUB16_MI: "UHSUB16.MI",
UHSUB16_PL: "UHSUB16.PL",
UHSUB16_VS: "UHSUB16.VS",
UHSUB16_VC: "UHSUB16.VC",
UHSUB16_HI: "UHSUB16.HI",
UHSUB16_LS: "UHSUB16.LS",
UHSUB16_GE: "UHSUB16.GE",
UHSUB16_LT: "UHSUB16.LT",
UHSUB16_GT: "UHSUB16.GT",
UHSUB16_LE: "UHSUB16.LE",
UHSUB16: "UHSUB16",
UHSUB16_ZZ: "UHSUB16.ZZ",
UHSUB8_EQ: "UHSUB8.EQ",
UHSUB8_NE: "UHSUB8.NE",
UHSUB8_CS: "UHSUB8.CS",
UHSUB8_CC: "UHSUB8.CC",
UHSUB8_MI: "UHSUB8.MI",
UHSUB8_PL: "UHSUB8.PL",
UHSUB8_VS: "UHSUB8.VS",
UHSUB8_VC: "UHSUB8.VC",
UHSUB8_HI: "UHSUB8.HI",
UHSUB8_LS: "UHSUB8.LS",
UHSUB8_GE: "UHSUB8.GE",
UHSUB8_LT: "UHSUB8.LT",
UHSUB8_GT: "UHSUB8.GT",
UHSUB8_LE: "UHSUB8.LE",
UHSUB8: "UHSUB8",
UHSUB8_ZZ: "UHSUB8.ZZ",
UMAAL_EQ: "UMAAL.EQ",
UMAAL_NE: "UMAAL.NE",
UMAAL_CS: "UMAAL.CS",
UMAAL_CC: "UMAAL.CC",
UMAAL_MI: "UMAAL.MI",
UMAAL_PL: "UMAAL.PL",
UMAAL_VS: "UMAAL.VS",
UMAAL_VC: "UMAAL.VC",
UMAAL_HI: "UMAAL.HI",
UMAAL_LS: "UMAAL.LS",
UMAAL_GE: "UMAAL.GE",
UMAAL_LT: "UMAAL.LT",
UMAAL_GT: "UMAAL.GT",
UMAAL_LE: "UMAAL.LE",
UMAAL: "UMAAL",
UMAAL_ZZ: "UMAAL.ZZ",
UMLAL_EQ: "UMLAL.EQ",
UMLAL_NE: "UMLAL.NE",
UMLAL_CS: "UMLAL.CS",
UMLAL_CC: "UMLAL.CC",
UMLAL_MI: "UMLAL.MI",
UMLAL_PL: "UMLAL.PL",
UMLAL_VS: "UMLAL.VS",
UMLAL_VC: "UMLAL.VC",
UMLAL_HI: "UMLAL.HI",
UMLAL_LS: "UMLAL.LS",
UMLAL_GE: "UMLAL.GE",
UMLAL_LT: "UMLAL.LT",
UMLAL_GT: "UMLAL.GT",
UMLAL_LE: "UMLAL.LE",
UMLAL: "UMLAL",
UMLAL_ZZ: "UMLAL.ZZ",
UMLAL_S_EQ: "UMLAL.S.EQ",
UMLAL_S_NE: "UMLAL.S.NE",
UMLAL_S_CS: "UMLAL.S.CS",
UMLAL_S_CC: "UMLAL.S.CC",
UMLAL_S_MI: "UMLAL.S.MI",
UMLAL_S_PL: "UMLAL.S.PL",
UMLAL_S_VS: "UMLAL.S.VS",
UMLAL_S_VC: "UMLAL.S.VC",
UMLAL_S_HI: "UMLAL.S.HI",
UMLAL_S_LS: "UMLAL.S.LS",
UMLAL_S_GE: "UMLAL.S.GE",
UMLAL_S_LT: "UMLAL.S.LT",
UMLAL_S_GT: "UMLAL.S.GT",
UMLAL_S_LE: "UMLAL.S.LE",
UMLAL_S: "UMLAL.S",
UMLAL_S_ZZ: "UMLAL.S.ZZ",
UMULL_EQ: "UMULL.EQ",
UMULL_NE: "UMULL.NE",
UMULL_CS: "UMULL.CS",
UMULL_CC: "UMULL.CC",
UMULL_MI: "UMULL.MI",
UMULL_PL: "UMULL.PL",
UMULL_VS: "UMULL.VS",
UMULL_VC: "UMULL.VC",
UMULL_HI: "UMULL.HI",
UMULL_LS: "UMULL.LS",
UMULL_GE: "UMULL.GE",
UMULL_LT: "UMULL.LT",
UMULL_GT: "UMULL.GT",
UMULL_LE: "UMULL.LE",
UMULL: "UMULL",
UMULL_ZZ: "UMULL.ZZ",
UMULL_S_EQ: "UMULL.S.EQ",
UMULL_S_NE: "UMULL.S.NE",
UMULL_S_CS: "UMULL.S.CS",
UMULL_S_CC: "UMULL.S.CC",
UMULL_S_MI: "UMULL.S.MI",
UMULL_S_PL: "UMULL.S.PL",
UMULL_S_VS: "UMULL.S.VS",
UMULL_S_VC: "UMULL.S.VC",
UMULL_S_HI: "UMULL.S.HI",
UMULL_S_LS: "UMULL.S.LS",
UMULL_S_GE: "UMULL.S.GE",
UMULL_S_LT: "UMULL.S.LT",
UMULL_S_GT: "UMULL.S.GT",
UMULL_S_LE: "UMULL.S.LE",
UMULL_S: "UMULL.S",
UMULL_S_ZZ: "UMULL.S.ZZ",
UNDEF: "UNDEF",
UQADD16_EQ: "UQADD16.EQ",
UQADD16_NE: "UQADD16.NE",
UQADD16_CS: "UQADD16.CS",
UQADD16_CC: "UQADD16.CC",
UQADD16_MI: "UQADD16.MI",
UQADD16_PL: "UQADD16.PL",
UQADD16_VS: "UQADD16.VS",
UQADD16_VC: "UQADD16.VC",
UQADD16_HI: "UQADD16.HI",
UQADD16_LS: "UQADD16.LS",
UQADD16_GE: "UQADD16.GE",
UQADD16_LT: "UQADD16.LT",
UQADD16_GT: "UQADD16.GT",
UQADD16_LE: "UQADD16.LE",
UQADD16: "UQADD16",
UQADD16_ZZ: "UQADD16.ZZ",
UQADD8_EQ: "UQADD8.EQ",
UQADD8_NE: "UQADD8.NE",
UQADD8_CS: "UQADD8.CS",
UQADD8_CC: "UQADD8.CC",
UQADD8_MI: "UQADD8.MI",
UQADD8_PL: "UQADD8.PL",
UQADD8_VS: "UQADD8.VS",
UQADD8_VC: "UQADD8.VC",
UQADD8_HI: "UQADD8.HI",
UQADD8_LS: "UQADD8.LS",
UQADD8_GE: "UQADD8.GE",
UQADD8_LT: "UQADD8.LT",
UQADD8_GT: "UQADD8.GT",
UQADD8_LE: "UQADD8.LE",
UQADD8: "UQADD8",
UQADD8_ZZ: "UQADD8.ZZ",
UQASX_EQ: "UQASX.EQ",
UQASX_NE: "UQASX.NE",
UQASX_CS: "UQASX.CS",
UQASX_CC: "UQASX.CC",
UQASX_MI: "UQASX.MI",
UQASX_PL: "UQASX.PL",
UQASX_VS: "UQASX.VS",
UQASX_VC: "UQASX.VC",
UQASX_HI: "UQASX.HI",
UQASX_LS: "UQASX.LS",
UQASX_GE: "UQASX.GE",
UQASX_LT: "UQASX.LT",
UQASX_GT: "UQASX.GT",
UQASX_LE: "UQASX.LE",
UQASX: "UQASX",
UQASX_ZZ: "UQASX.ZZ",
UQSAX_EQ: "UQSAX.EQ",
UQSAX_NE: "UQSAX.NE",
UQSAX_CS: "UQSAX.CS",
UQSAX_CC: "UQSAX.CC",
UQSAX_MI: "UQSAX.MI",
UQSAX_PL: "UQSAX.PL",
UQSAX_VS: "UQSAX.VS",
UQSAX_VC: "UQSAX.VC",
UQSAX_HI: "UQSAX.HI",
UQSAX_LS: "UQSAX.LS",
UQSAX_GE: "UQSAX.GE",
UQSAX_LT: "UQSAX.LT",
UQSAX_GT: "UQSAX.GT",
UQSAX_LE: "UQSAX.LE",
UQSAX: "UQSAX",
UQSAX_ZZ: "UQSAX.ZZ",
UQSUB16_EQ: "UQSUB16.EQ",
UQSUB16_NE: "UQSUB16.NE",
UQSUB16_CS: "UQSUB16.CS",
UQSUB16_CC: "UQSUB16.CC",
UQSUB16_MI: "UQSUB16.MI",
UQSUB16_PL: "UQSUB16.PL",
UQSUB16_VS: "UQSUB16.VS",
UQSUB16_VC: "UQSUB16.VC",
UQSUB16_HI: "UQSUB16.HI",
UQSUB16_LS: "UQSUB16.LS",
UQSUB16_GE: "UQSUB16.GE",
UQSUB16_LT: "UQSUB16.LT",
UQSUB16_GT: "UQSUB16.GT",
UQSUB16_LE: "UQSUB16.LE",
UQSUB16: "UQSUB16",
UQSUB16_ZZ: "UQSUB16.ZZ",
UQSUB8_EQ: "UQSUB8.EQ",
UQSUB8_NE: "UQSUB8.NE",
UQSUB8_CS: "UQSUB8.CS",
UQSUB8_CC: "UQSUB8.CC",
UQSUB8_MI: "UQSUB8.MI",
UQSUB8_PL: "UQSUB8.PL",
UQSUB8_VS: "UQSUB8.VS",
UQSUB8_VC: "UQSUB8.VC",
UQSUB8_HI: "UQSUB8.HI",
UQSUB8_LS: "UQSUB8.LS",
UQSUB8_GE: "UQSUB8.GE",
UQSUB8_LT: "UQSUB8.LT",
UQSUB8_GT: "UQSUB8.GT",
UQSUB8_LE: "UQSUB8.LE",
UQSUB8: "UQSUB8",
UQSUB8_ZZ: "UQSUB8.ZZ",
USAD8_EQ: "USAD8.EQ",
USAD8_NE: "USAD8.NE",
USAD8_CS: "USAD8.CS",
USAD8_CC: "USAD8.CC",
USAD8_MI: "USAD8.MI",
USAD8_PL: "USAD8.PL",
USAD8_VS: "USAD8.VS",
USAD8_VC: "USAD8.VC",
USAD8_HI: "USAD8.HI",
USAD8_LS: "USAD8.LS",
USAD8_GE: "USAD8.GE",
USAD8_LT: "USAD8.LT",
USAD8_GT: "USAD8.GT",
USAD8_LE: "USAD8.LE",
USAD8: "USAD8",
USAD8_ZZ: "USAD8.ZZ",
USADA8_EQ: "USADA8.EQ",
USADA8_NE: "USADA8.NE",
USADA8_CS: "USADA8.CS",
USADA8_CC: "USADA8.CC",
USADA8_MI: "USADA8.MI",
USADA8_PL: "USADA8.PL",
USADA8_VS: "USADA8.VS",
USADA8_VC: "USADA8.VC",
USADA8_HI: "USADA8.HI",
USADA8_LS: "USADA8.LS",
USADA8_GE: "USADA8.GE",
USADA8_LT: "USADA8.LT",
USADA8_GT: "USADA8.GT",
USADA8_LE: "USADA8.LE",
USADA8: "USADA8",
USADA8_ZZ: "USADA8.ZZ",
USAT_EQ: "USAT.EQ",
USAT_NE: "USAT.NE",
USAT_CS: "USAT.CS",
USAT_CC: "USAT.CC",
USAT_MI: "USAT.MI",
USAT_PL: "USAT.PL",
USAT_VS: "USAT.VS",
USAT_VC: "USAT.VC",
USAT_HI: "USAT.HI",
USAT_LS: "USAT.LS",
USAT_GE: "USAT.GE",
USAT_LT: "USAT.LT",
USAT_GT: "USAT.GT",
USAT_LE: "USAT.LE",
USAT: "USAT",
USAT_ZZ: "USAT.ZZ",
USAT16_EQ: "USAT16.EQ",
USAT16_NE: "USAT16.NE",
USAT16_CS: "USAT16.CS",
USAT16_CC: "USAT16.CC",
USAT16_MI: "USAT16.MI",
USAT16_PL: "USAT16.PL",
USAT16_VS: "USAT16.VS",
USAT16_VC: "USAT16.VC",
USAT16_HI: "USAT16.HI",
USAT16_LS: "USAT16.LS",
USAT16_GE: "USAT16.GE",
USAT16_LT: "USAT16.LT",
USAT16_GT: "USAT16.GT",
USAT16_LE: "USAT16.LE",
USAT16: "USAT16",
USAT16_ZZ: "USAT16.ZZ",
USAX_EQ: "USAX.EQ",
USAX_NE: "USAX.NE",
USAX_CS: "USAX.CS",
USAX_CC: "USAX.CC",
USAX_MI: "USAX.MI",
USAX_PL: "USAX.PL",
USAX_VS: "USAX.VS",
USAX_VC: "USAX.VC",
USAX_HI: "USAX.HI",
USAX_LS: "USAX.LS",
USAX_GE: "USAX.GE",
USAX_LT: "USAX.LT",
USAX_GT: "USAX.GT",
USAX_LE: "USAX.LE",
USAX: "USAX",
USAX_ZZ: "USAX.ZZ",
USUB16_EQ: "USUB16.EQ",
USUB16_NE: "USUB16.NE",
USUB16_CS: "USUB16.CS",
USUB16_CC: "USUB16.CC",
USUB16_MI: "USUB16.MI",
USUB16_PL: "USUB16.PL",
USUB16_VS: "USUB16.VS",
USUB16_VC: "USUB16.VC",
USUB16_HI: "USUB16.HI",
USUB16_LS: "USUB16.LS",
USUB16_GE: "USUB16.GE",
USUB16_LT: "USUB16.LT",
USUB16_GT: "USUB16.GT",
USUB16_LE: "USUB16.LE",
USUB16: "USUB16",
USUB16_ZZ: "USUB16.ZZ",
USUB8_EQ: "USUB8.EQ",
USUB8_NE: "USUB8.NE",
USUB8_CS: "USUB8.CS",
USUB8_CC: "USUB8.CC",
USUB8_MI: "USUB8.MI",
USUB8_PL: "USUB8.PL",
USUB8_VS: "USUB8.VS",
USUB8_VC: "USUB8.VC",
USUB8_HI: "USUB8.HI",
USUB8_LS: "USUB8.LS",
USUB8_GE: "USUB8.GE",
USUB8_LT: "USUB8.LT",
USUB8_GT: "USUB8.GT",
USUB8_LE: "USUB8.LE",
USUB8: "USUB8",
USUB8_ZZ: "USUB8.ZZ",
UXTAB_EQ: "UXTAB.EQ",
UXTAB_NE: "UXTAB.NE",
UXTAB_CS: "UXTAB.CS",
UXTAB_CC: "UXTAB.CC",
UXTAB_MI: "UXTAB.MI",
UXTAB_PL: "UXTAB.PL",
UXTAB_VS: "UXTAB.VS",
UXTAB_VC: "UXTAB.VC",
UXTAB_HI: "UXTAB.HI",
UXTAB_LS: "UXTAB.LS",
UXTAB_GE: "UXTAB.GE",
UXTAB_LT: "UXTAB.LT",
UXTAB_GT: "UXTAB.GT",
UXTAB_LE: "UXTAB.LE",
UXTAB: "UXTAB",
UXTAB_ZZ: "UXTAB.ZZ",
UXTAB16_EQ: "UXTAB16.EQ",
UXTAB16_NE: "UXTAB16.NE",
UXTAB16_CS: "UXTAB16.CS",
UXTAB16_CC: "UXTAB16.CC",
UXTAB16_MI: "UXTAB16.MI",
UXTAB16_PL: "UXTAB16.PL",
UXTAB16_VS: "UXTAB16.VS",
UXTAB16_VC: "UXTAB16.VC",
UXTAB16_HI: "UXTAB16.HI",
UXTAB16_LS: "UXTAB16.LS",
UXTAB16_GE: "UXTAB16.GE",
UXTAB16_LT: "UXTAB16.LT",
UXTAB16_GT: "UXTAB16.GT",
UXTAB16_LE: "UXTAB16.LE",
UXTAB16: "UXTAB16",
UXTAB16_ZZ: "UXTAB16.ZZ",
UXTAH_EQ: "UXTAH.EQ",
UXTAH_NE: "UXTAH.NE",
UXTAH_CS: "UXTAH.CS",
UXTAH_CC: "UXTAH.CC",
UXTAH_MI: "UXTAH.MI",
UXTAH_PL: "UXTAH.PL",
UXTAH_VS: "UXTAH.VS",
UXTAH_VC: "UXTAH.VC",
UXTAH_HI: "UXTAH.HI",
UXTAH_LS: "UXTAH.LS",
UXTAH_GE: "UXTAH.GE",
UXTAH_LT: "UXTAH.LT",
UXTAH_GT: "UXTAH.GT",
UXTAH_LE: "UXTAH.LE",
UXTAH: "UXTAH",
UXTAH_ZZ: "UXTAH.ZZ",
UXTB_EQ: "UXTB.EQ",
UXTB_NE: "UXTB.NE",
UXTB_CS: "UXTB.CS",
UXTB_CC: "UXTB.CC",
UXTB_MI: "UXTB.MI",
UXTB_PL: "UXTB.PL",
UXTB_VS: "UXTB.VS",
UXTB_VC: "UXTB.VC",
UXTB_HI: "UXTB.HI",
UXTB_LS: "UXTB.LS",
UXTB_GE: "UXTB.GE",
UXTB_LT: "UXTB.LT",
UXTB_GT: "UXTB.GT",
UXTB_LE: "UXTB.LE",
UXTB: "UXTB",
UXTB_ZZ: "UXTB.ZZ",
UXTB16_EQ: "UXTB16.EQ",
UXTB16_NE: "UXTB16.NE",
UXTB16_CS: "UXTB16.CS",
UXTB16_CC: "UXTB16.CC",
UXTB16_MI: "UXTB16.MI",
UXTB16_PL: "UXTB16.PL",
UXTB16_VS: "UXTB16.VS",
UXTB16_VC: "UXTB16.VC",
UXTB16_HI: "UXTB16.HI",
UXTB16_LS: "UXTB16.LS",
UXTB16_GE: "UXTB16.GE",
UXTB16_LT: "UXTB16.LT",
UXTB16_GT: "UXTB16.GT",
UXTB16_LE: "UXTB16.LE",
UXTB16: "UXTB16",
UXTB16_ZZ: "UXTB16.ZZ",
UXTH_EQ: "UXTH.EQ",
UXTH_NE: "UXTH.NE",
UXTH_CS: "UXTH.CS",
UXTH_CC: "UXTH.CC",
UXTH_MI: "UXTH.MI",
UXTH_PL: "UXTH.PL",
UXTH_VS: "UXTH.VS",
UXTH_VC: "UXTH.VC",
UXTH_HI: "UXTH.HI",
UXTH_LS: "UXTH.LS",
UXTH_GE: "UXTH.GE",
UXTH_LT: "UXTH.LT",
UXTH_GT: "UXTH.GT",
UXTH_LE: "UXTH.LE",
UXTH: "UXTH",
UXTH_ZZ: "UXTH.ZZ",
VABS_EQ_F32: "VABS.EQ.F32",
VABS_NE_F32: "VABS.NE.F32",
VABS_CS_F32: "VABS.CS.F32",
VABS_CC_F32: "VABS.CC.F32",
VABS_MI_F32: "VABS.MI.F32",
VABS_PL_F32: "VABS.PL.F32",
VABS_VS_F32: "VABS.VS.F32",
VABS_VC_F32: "VABS.VC.F32",
VABS_HI_F32: "VABS.HI.F32",
VABS_LS_F32: "VABS.LS.F32",
VABS_GE_F32: "VABS.GE.F32",
VABS_LT_F32: "VABS.LT.F32",
VABS_GT_F32: "VABS.GT.F32",
VABS_LE_F32: "VABS.LE.F32",
VABS_F32: "VABS.F32",
VABS_ZZ_F32: "VABS.ZZ.F32",
VABS_EQ_F64: "VABS.EQ.F64",
VABS_NE_F64: "VABS.NE.F64",
VABS_CS_F64: "VABS.CS.F64",
VABS_CC_F64: "VABS.CC.F64",
VABS_MI_F64: "VABS.MI.F64",
VABS_PL_F64: "VABS.PL.F64",
VABS_VS_F64: "VABS.VS.F64",
VABS_VC_F64: "VABS.VC.F64",
VABS_HI_F64: "VABS.HI.F64",
VABS_LS_F64: "VABS.LS.F64",
VABS_GE_F64: "VABS.GE.F64",
VABS_LT_F64: "VABS.LT.F64",
VABS_GT_F64: "VABS.GT.F64",
VABS_LE_F64: "VABS.LE.F64",
VABS_F64: "VABS.F64",
VABS_ZZ_F64: "VABS.ZZ.F64",
VADD_EQ_F32: "VADD.EQ.F32",
VADD_NE_F32: "VADD.NE.F32",
VADD_CS_F32: "VADD.CS.F32",
VADD_CC_F32: "VADD.CC.F32",
VADD_MI_F32: "VADD.MI.F32",
VADD_PL_F32: "VADD.PL.F32",
VADD_VS_F32: "VADD.VS.F32",
VADD_VC_F32: "VADD.VC.F32",
VADD_HI_F32: "VADD.HI.F32",
VADD_LS_F32: "VADD.LS.F32",
VADD_GE_F32: "VADD.GE.F32",
VADD_LT_F32: "VADD.LT.F32",
VADD_GT_F32: "VADD.GT.F32",
VADD_LE_F32: "VADD.LE.F32",
VADD_F32: "VADD.F32",
VADD_ZZ_F32: "VADD.ZZ.F32",
VADD_EQ_F64: "VADD.EQ.F64",
VADD_NE_F64: "VADD.NE.F64",
VADD_CS_F64: "VADD.CS.F64",
VADD_CC_F64: "VADD.CC.F64",
VADD_MI_F64: "VADD.MI.F64",
VADD_PL_F64: "VADD.PL.F64",
VADD_VS_F64: "VADD.VS.F64",
VADD_VC_F64: "VADD.VC.F64",
VADD_HI_F64: "VADD.HI.F64",
VADD_LS_F64: "VADD.LS.F64",
VADD_GE_F64: "VADD.GE.F64",
VADD_LT_F64: "VADD.LT.F64",
VADD_GT_F64: "VADD.GT.F64",
VADD_LE_F64: "VADD.LE.F64",
VADD_F64: "VADD.F64",
VADD_ZZ_F64: "VADD.ZZ.F64",
VCMP_EQ_F32: "VCMP.EQ.F32",
VCMP_NE_F32: "VCMP.NE.F32",
VCMP_CS_F32: "VCMP.CS.F32",
VCMP_CC_F32: "VCMP.CC.F32",
VCMP_MI_F32: "VCMP.MI.F32",
VCMP_PL_F32: "VCMP.PL.F32",
VCMP_VS_F32: "VCMP.VS.F32",
VCMP_VC_F32: "VCMP.VC.F32",
VCMP_HI_F32: "VCMP.HI.F32",
VCMP_LS_F32: "VCMP.LS.F32",
VCMP_GE_F32: "VCMP.GE.F32",
VCMP_LT_F32: "VCMP.LT.F32",
VCMP_GT_F32: "VCMP.GT.F32",
VCMP_LE_F32: "VCMP.LE.F32",
VCMP_F32: "VCMP.F32",
VCMP_ZZ_F32: "VCMP.ZZ.F32",
VCMP_EQ_F64: "VCMP.EQ.F64",
VCMP_NE_F64: "VCMP.NE.F64",
VCMP_CS_F64: "VCMP.CS.F64",
VCMP_CC_F64: "VCMP.CC.F64",
VCMP_MI_F64: "VCMP.MI.F64",
VCMP_PL_F64: "VCMP.PL.F64",
VCMP_VS_F64: "VCMP.VS.F64",
VCMP_VC_F64: "VCMP.VC.F64",
VCMP_HI_F64: "VCMP.HI.F64",
VCMP_LS_F64: "VCMP.LS.F64",
VCMP_GE_F64: "VCMP.GE.F64",
VCMP_LT_F64: "VCMP.LT.F64",
VCMP_GT_F64: "VCMP.GT.F64",
VCMP_LE_F64: "VCMP.LE.F64",
VCMP_F64: "VCMP.F64",
VCMP_ZZ_F64: "VCMP.ZZ.F64",
VCMP_E_EQ_F32: "VCMP.E.EQ.F32",
VCMP_E_NE_F32: "VCMP.E.NE.F32",
VCMP_E_CS_F32: "VCMP.E.CS.F32",
VCMP_E_CC_F32: "VCMP.E.CC.F32",
VCMP_E_MI_F32: "VCMP.E.MI.F32",
VCMP_E_PL_F32: "VCMP.E.PL.F32",
VCMP_E_VS_F32: "VCMP.E.VS.F32",
VCMP_E_VC_F32: "VCMP.E.VC.F32",
VCMP_E_HI_F32: "VCMP.E.HI.F32",
VCMP_E_LS_F32: "VCMP.E.LS.F32",
VCMP_E_GE_F32: "VCMP.E.GE.F32",
VCMP_E_LT_F32: "VCMP.E.LT.F32",
VCMP_E_GT_F32: "VCMP.E.GT.F32",
VCMP_E_LE_F32: "VCMP.E.LE.F32",
VCMP_E_F32: "VCMP.E.F32",
VCMP_E_ZZ_F32: "VCMP.E.ZZ.F32",
VCMP_E_EQ_F64: "VCMP.E.EQ.F64",
VCMP_E_NE_F64: "VCMP.E.NE.F64",
VCMP_E_CS_F64: "VCMP.E.CS.F64",
VCMP_E_CC_F64: "VCMP.E.CC.F64",
VCMP_E_MI_F64: "VCMP.E.MI.F64",
VCMP_E_PL_F64: "VCMP.E.PL.F64",
VCMP_E_VS_F64: "VCMP.E.VS.F64",
VCMP_E_VC_F64: "VCMP.E.VC.F64",
VCMP_E_HI_F64: "VCMP.E.HI.F64",
VCMP_E_LS_F64: "VCMP.E.LS.F64",
VCMP_E_GE_F64: "VCMP.E.GE.F64",
VCMP_E_LT_F64: "VCMP.E.LT.F64",
VCMP_E_GT_F64: "VCMP.E.GT.F64",
VCMP_E_LE_F64: "VCMP.E.LE.F64",
VCMP_E_F64: "VCMP.E.F64",
VCMP_E_ZZ_F64: "VCMP.E.ZZ.F64",
VCVT_EQ_F32_FXS16: "VCVT.EQ.F32.FXS16",
VCVT_NE_F32_FXS16: "VCVT.NE.F32.FXS16",
VCVT_CS_F32_FXS16: "VCVT.CS.F32.FXS16",
VCVT_CC_F32_FXS16: "VCVT.CC.F32.FXS16",
VCVT_MI_F32_FXS16: "VCVT.MI.F32.FXS16",
VCVT_PL_F32_FXS16: "VCVT.PL.F32.FXS16",
VCVT_VS_F32_FXS16: "VCVT.VS.F32.FXS16",
VCVT_VC_F32_FXS16: "VCVT.VC.F32.FXS16",
VCVT_HI_F32_FXS16: "VCVT.HI.F32.FXS16",
VCVT_LS_F32_FXS16: "VCVT.LS.F32.FXS16",
VCVT_GE_F32_FXS16: "VCVT.GE.F32.FXS16",
VCVT_LT_F32_FXS16: "VCVT.LT.F32.FXS16",
VCVT_GT_F32_FXS16: "VCVT.GT.F32.FXS16",
VCVT_LE_F32_FXS16: "VCVT.LE.F32.FXS16",
VCVT_F32_FXS16: "VCVT.F32.FXS16",
VCVT_ZZ_F32_FXS16: "VCVT.ZZ.F32.FXS16",
VCVT_EQ_F32_FXS32: "VCVT.EQ.F32.FXS32",
VCVT_NE_F32_FXS32: "VCVT.NE.F32.FXS32",
VCVT_CS_F32_FXS32: "VCVT.CS.F32.FXS32",
VCVT_CC_F32_FXS32: "VCVT.CC.F32.FXS32",
VCVT_MI_F32_FXS32: "VCVT.MI.F32.FXS32",
VCVT_PL_F32_FXS32: "VCVT.PL.F32.FXS32",
VCVT_VS_F32_FXS32: "VCVT.VS.F32.FXS32",
VCVT_VC_F32_FXS32: "VCVT.VC.F32.FXS32",
VCVT_HI_F32_FXS32: "VCVT.HI.F32.FXS32",
VCVT_LS_F32_FXS32: "VCVT.LS.F32.FXS32",
VCVT_GE_F32_FXS32: "VCVT.GE.F32.FXS32",
VCVT_LT_F32_FXS32: "VCVT.LT.F32.FXS32",
VCVT_GT_F32_FXS32: "VCVT.GT.F32.FXS32",
VCVT_LE_F32_FXS32: "VCVT.LE.F32.FXS32",
VCVT_F32_FXS32: "VCVT.F32.FXS32",
VCVT_ZZ_F32_FXS32: "VCVT.ZZ.F32.FXS32",
VCVT_EQ_F32_FXU16: "VCVT.EQ.F32.FXU16",
VCVT_NE_F32_FXU16: "VCVT.NE.F32.FXU16",
VCVT_CS_F32_FXU16: "VCVT.CS.F32.FXU16",
VCVT_CC_F32_FXU16: "VCVT.CC.F32.FXU16",
VCVT_MI_F32_FXU16: "VCVT.MI.F32.FXU16",
VCVT_PL_F32_FXU16: "VCVT.PL.F32.FXU16",
VCVT_VS_F32_FXU16: "VCVT.VS.F32.FXU16",
VCVT_VC_F32_FXU16: "VCVT.VC.F32.FXU16",
VCVT_HI_F32_FXU16: "VCVT.HI.F32.FXU16",
VCVT_LS_F32_FXU16: "VCVT.LS.F32.FXU16",
VCVT_GE_F32_FXU16: "VCVT.GE.F32.FXU16",
VCVT_LT_F32_FXU16: "VCVT.LT.F32.FXU16",
VCVT_GT_F32_FXU16: "VCVT.GT.F32.FXU16",
VCVT_LE_F32_FXU16: "VCVT.LE.F32.FXU16",
VCVT_F32_FXU16: "VCVT.F32.FXU16",
VCVT_ZZ_F32_FXU16: "VCVT.ZZ.F32.FXU16",
VCVT_EQ_F32_FXU32: "VCVT.EQ.F32.FXU32",
VCVT_NE_F32_FXU32: "VCVT.NE.F32.FXU32",
VCVT_CS_F32_FXU32: "VCVT.CS.F32.FXU32",
VCVT_CC_F32_FXU32: "VCVT.CC.F32.FXU32",
VCVT_MI_F32_FXU32: "VCVT.MI.F32.FXU32",
VCVT_PL_F32_FXU32: "VCVT.PL.F32.FXU32",
VCVT_VS_F32_FXU32: "VCVT.VS.F32.FXU32",
VCVT_VC_F32_FXU32: "VCVT.VC.F32.FXU32",
VCVT_HI_F32_FXU32: "VCVT.HI.F32.FXU32",
VCVT_LS_F32_FXU32: "VCVT.LS.F32.FXU32",
VCVT_GE_F32_FXU32: "VCVT.GE.F32.FXU32",
VCVT_LT_F32_FXU32: "VCVT.LT.F32.FXU32",
VCVT_GT_F32_FXU32: "VCVT.GT.F32.FXU32",
VCVT_LE_F32_FXU32: "VCVT.LE.F32.FXU32",
VCVT_F32_FXU32: "VCVT.F32.FXU32",
VCVT_ZZ_F32_FXU32: "VCVT.ZZ.F32.FXU32",
VCVT_EQ_F64_FXS16: "VCVT.EQ.F64.FXS16",
VCVT_NE_F64_FXS16: "VCVT.NE.F64.FXS16",
VCVT_CS_F64_FXS16: "VCVT.CS.F64.FXS16",
VCVT_CC_F64_FXS16: "VCVT.CC.F64.FXS16",
VCVT_MI_F64_FXS16: "VCVT.MI.F64.FXS16",
VCVT_PL_F64_FXS16: "VCVT.PL.F64.FXS16",
VCVT_VS_F64_FXS16: "VCVT.VS.F64.FXS16",
VCVT_VC_F64_FXS16: "VCVT.VC.F64.FXS16",
VCVT_HI_F64_FXS16: "VCVT.HI.F64.FXS16",
VCVT_LS_F64_FXS16: "VCVT.LS.F64.FXS16",
VCVT_GE_F64_FXS16: "VCVT.GE.F64.FXS16",
VCVT_LT_F64_FXS16: "VCVT.LT.F64.FXS16",
VCVT_GT_F64_FXS16: "VCVT.GT.F64.FXS16",
VCVT_LE_F64_FXS16: "VCVT.LE.F64.FXS16",
VCVT_F64_FXS16: "VCVT.F64.FXS16",
VCVT_ZZ_F64_FXS16: "VCVT.ZZ.F64.FXS16",
VCVT_EQ_F64_FXS32: "VCVT.EQ.F64.FXS32",
VCVT_NE_F64_FXS32: "VCVT.NE.F64.FXS32",
VCVT_CS_F64_FXS32: "VCVT.CS.F64.FXS32",
VCVT_CC_F64_FXS32: "VCVT.CC.F64.FXS32",
VCVT_MI_F64_FXS32: "VCVT.MI.F64.FXS32",
VCVT_PL_F64_FXS32: "VCVT.PL.F64.FXS32",
VCVT_VS_F64_FXS32: "VCVT.VS.F64.FXS32",
VCVT_VC_F64_FXS32: "VCVT.VC.F64.FXS32",
VCVT_HI_F64_FXS32: "VCVT.HI.F64.FXS32",
VCVT_LS_F64_FXS32: "VCVT.LS.F64.FXS32",
VCVT_GE_F64_FXS32: "VCVT.GE.F64.FXS32",
VCVT_LT_F64_FXS32: "VCVT.LT.F64.FXS32",
VCVT_GT_F64_FXS32: "VCVT.GT.F64.FXS32",
VCVT_LE_F64_FXS32: "VCVT.LE.F64.FXS32",
VCVT_F64_FXS32: "VCVT.F64.FXS32",
VCVT_ZZ_F64_FXS32: "VCVT.ZZ.F64.FXS32",
VCVT_EQ_F64_FXU16: "VCVT.EQ.F64.FXU16",
VCVT_NE_F64_FXU16: "VCVT.NE.F64.FXU16",
VCVT_CS_F64_FXU16: "VCVT.CS.F64.FXU16",
VCVT_CC_F64_FXU16: "VCVT.CC.F64.FXU16",
VCVT_MI_F64_FXU16: "VCVT.MI.F64.FXU16",
VCVT_PL_F64_FXU16: "VCVT.PL.F64.FXU16",
VCVT_VS_F64_FXU16: "VCVT.VS.F64.FXU16",
VCVT_VC_F64_FXU16: "VCVT.VC.F64.FXU16",
VCVT_HI_F64_FXU16: "VCVT.HI.F64.FXU16",
VCVT_LS_F64_FXU16: "VCVT.LS.F64.FXU16",
VCVT_GE_F64_FXU16: "VCVT.GE.F64.FXU16",
VCVT_LT_F64_FXU16: "VCVT.LT.F64.FXU16",
VCVT_GT_F64_FXU16: "VCVT.GT.F64.FXU16",
VCVT_LE_F64_FXU16: "VCVT.LE.F64.FXU16",
VCVT_F64_FXU16: "VCVT.F64.FXU16",
VCVT_ZZ_F64_FXU16: "VCVT.ZZ.F64.FXU16",
VCVT_EQ_F64_FXU32: "VCVT.EQ.F64.FXU32",
VCVT_NE_F64_FXU32: "VCVT.NE.F64.FXU32",
VCVT_CS_F64_FXU32: "VCVT.CS.F64.FXU32",
VCVT_CC_F64_FXU32: "VCVT.CC.F64.FXU32",
VCVT_MI_F64_FXU32: "VCVT.MI.F64.FXU32",
VCVT_PL_F64_FXU32: "VCVT.PL.F64.FXU32",
VCVT_VS_F64_FXU32: "VCVT.VS.F64.FXU32",
VCVT_VC_F64_FXU32: "VCVT.VC.F64.FXU32",
VCVT_HI_F64_FXU32: "VCVT.HI.F64.FXU32",
VCVT_LS_F64_FXU32: "VCVT.LS.F64.FXU32",
VCVT_GE_F64_FXU32: "VCVT.GE.F64.FXU32",
VCVT_LT_F64_FXU32: "VCVT.LT.F64.FXU32",
VCVT_GT_F64_FXU32: "VCVT.GT.F64.FXU32",
VCVT_LE_F64_FXU32: "VCVT.LE.F64.FXU32",
VCVT_F64_FXU32: "VCVT.F64.FXU32",
VCVT_ZZ_F64_FXU32: "VCVT.ZZ.F64.FXU32",
VCVT_EQ_F32_U32: "VCVT.EQ.F32.U32",
VCVT_NE_F32_U32: "VCVT.NE.F32.U32",
VCVT_CS_F32_U32: "VCVT.CS.F32.U32",
VCVT_CC_F32_U32: "VCVT.CC.F32.U32",
VCVT_MI_F32_U32: "VCVT.MI.F32.U32",
VCVT_PL_F32_U32: "VCVT.PL.F32.U32",
VCVT_VS_F32_U32: "VCVT.VS.F32.U32",
VCVT_VC_F32_U32: "VCVT.VC.F32.U32",
VCVT_HI_F32_U32: "VCVT.HI.F32.U32",
VCVT_LS_F32_U32: "VCVT.LS.F32.U32",
VCVT_GE_F32_U32: "VCVT.GE.F32.U32",
VCVT_LT_F32_U32: "VCVT.LT.F32.U32",
VCVT_GT_F32_U32: "VCVT.GT.F32.U32",
VCVT_LE_F32_U32: "VCVT.LE.F32.U32",
VCVT_F32_U32: "VCVT.F32.U32",
VCVT_ZZ_F32_U32: "VCVT.ZZ.F32.U32",
VCVT_EQ_F32_S32: "VCVT.EQ.F32.S32",
VCVT_NE_F32_S32: "VCVT.NE.F32.S32",
VCVT_CS_F32_S32: "VCVT.CS.F32.S32",
VCVT_CC_F32_S32: "VCVT.CC.F32.S32",
VCVT_MI_F32_S32: "VCVT.MI.F32.S32",
VCVT_PL_F32_S32: "VCVT.PL.F32.S32",
VCVT_VS_F32_S32: "VCVT.VS.F32.S32",
VCVT_VC_F32_S32: "VCVT.VC.F32.S32",
VCVT_HI_F32_S32: "VCVT.HI.F32.S32",
VCVT_LS_F32_S32: "VCVT.LS.F32.S32",
VCVT_GE_F32_S32: "VCVT.GE.F32.S32",
VCVT_LT_F32_S32: "VCVT.LT.F32.S32",
VCVT_GT_F32_S32: "VCVT.GT.F32.S32",
VCVT_LE_F32_S32: "VCVT.LE.F32.S32",
VCVT_F32_S32: "VCVT.F32.S32",
VCVT_ZZ_F32_S32: "VCVT.ZZ.F32.S32",
VCVT_EQ_F64_U32: "VCVT.EQ.F64.U32",
VCVT_NE_F64_U32: "VCVT.NE.F64.U32",
VCVT_CS_F64_U32: "VCVT.CS.F64.U32",
VCVT_CC_F64_U32: "VCVT.CC.F64.U32",
VCVT_MI_F64_U32: "VCVT.MI.F64.U32",
VCVT_PL_F64_U32: "VCVT.PL.F64.U32",
VCVT_VS_F64_U32: "VCVT.VS.F64.U32",
VCVT_VC_F64_U32: "VCVT.VC.F64.U32",
VCVT_HI_F64_U32: "VCVT.HI.F64.U32",
VCVT_LS_F64_U32: "VCVT.LS.F64.U32",
VCVT_GE_F64_U32: "VCVT.GE.F64.U32",
VCVT_LT_F64_U32: "VCVT.LT.F64.U32",
VCVT_GT_F64_U32: "VCVT.GT.F64.U32",
VCVT_LE_F64_U32: "VCVT.LE.F64.U32",
VCVT_F64_U32: "VCVT.F64.U32",
VCVT_ZZ_F64_U32: "VCVT.ZZ.F64.U32",
VCVT_EQ_F64_S32: "VCVT.EQ.F64.S32",
VCVT_NE_F64_S32: "VCVT.NE.F64.S32",
VCVT_CS_F64_S32: "VCVT.CS.F64.S32",
VCVT_CC_F64_S32: "VCVT.CC.F64.S32",
VCVT_MI_F64_S32: "VCVT.MI.F64.S32",
VCVT_PL_F64_S32: "VCVT.PL.F64.S32",
VCVT_VS_F64_S32: "VCVT.VS.F64.S32",
VCVT_VC_F64_S32: "VCVT.VC.F64.S32",
VCVT_HI_F64_S32: "VCVT.HI.F64.S32",
VCVT_LS_F64_S32: "VCVT.LS.F64.S32",
VCVT_GE_F64_S32: "VCVT.GE.F64.S32",
VCVT_LT_F64_S32: "VCVT.LT.F64.S32",
VCVT_GT_F64_S32: "VCVT.GT.F64.S32",
VCVT_LE_F64_S32: "VCVT.LE.F64.S32",
VCVT_F64_S32: "VCVT.F64.S32",
VCVT_ZZ_F64_S32: "VCVT.ZZ.F64.S32",
VCVT_EQ_F64_F32: "VCVT.EQ.F64.F32",
VCVT_NE_F64_F32: "VCVT.NE.F64.F32",
VCVT_CS_F64_F32: "VCVT.CS.F64.F32",
VCVT_CC_F64_F32: "VCVT.CC.F64.F32",
VCVT_MI_F64_F32: "VCVT.MI.F64.F32",
VCVT_PL_F64_F32: "VCVT.PL.F64.F32",
VCVT_VS_F64_F32: "VCVT.VS.F64.F32",
VCVT_VC_F64_F32: "VCVT.VC.F64.F32",
VCVT_HI_F64_F32: "VCVT.HI.F64.F32",
VCVT_LS_F64_F32: "VCVT.LS.F64.F32",
VCVT_GE_F64_F32: "VCVT.GE.F64.F32",
VCVT_LT_F64_F32: "VCVT.LT.F64.F32",
VCVT_GT_F64_F32: "VCVT.GT.F64.F32",
VCVT_LE_F64_F32: "VCVT.LE.F64.F32",
VCVT_F64_F32: "VCVT.F64.F32",
VCVT_ZZ_F64_F32: "VCVT.ZZ.F64.F32",
VCVT_EQ_F32_F64: "VCVT.EQ.F32.F64",
VCVT_NE_F32_F64: "VCVT.NE.F32.F64",
VCVT_CS_F32_F64: "VCVT.CS.F32.F64",
VCVT_CC_F32_F64: "VCVT.CC.F32.F64",
VCVT_MI_F32_F64: "VCVT.MI.F32.F64",
VCVT_PL_F32_F64: "VCVT.PL.F32.F64",
VCVT_VS_F32_F64: "VCVT.VS.F32.F64",
VCVT_VC_F32_F64: "VCVT.VC.F32.F64",
VCVT_HI_F32_F64: "VCVT.HI.F32.F64",
VCVT_LS_F32_F64: "VCVT.LS.F32.F64",
VCVT_GE_F32_F64: "VCVT.GE.F32.F64",
VCVT_LT_F32_F64: "VCVT.LT.F32.F64",
VCVT_GT_F32_F64: "VCVT.GT.F32.F64",
VCVT_LE_F32_F64: "VCVT.LE.F32.F64",
VCVT_F32_F64: "VCVT.F32.F64",
VCVT_ZZ_F32_F64: "VCVT.ZZ.F32.F64",
VCVT_EQ_FXS16_F32: "VCVT.EQ.FXS16.F32",
VCVT_NE_FXS16_F32: "VCVT.NE.FXS16.F32",
VCVT_CS_FXS16_F32: "VCVT.CS.FXS16.F32",
VCVT_CC_FXS16_F32: "VCVT.CC.FXS16.F32",
VCVT_MI_FXS16_F32: "VCVT.MI.FXS16.F32",
VCVT_PL_FXS16_F32: "VCVT.PL.FXS16.F32",
VCVT_VS_FXS16_F32: "VCVT.VS.FXS16.F32",
VCVT_VC_FXS16_F32: "VCVT.VC.FXS16.F32",
VCVT_HI_FXS16_F32: "VCVT.HI.FXS16.F32",
VCVT_LS_FXS16_F32: "VCVT.LS.FXS16.F32",
VCVT_GE_FXS16_F32: "VCVT.GE.FXS16.F32",
VCVT_LT_FXS16_F32: "VCVT.LT.FXS16.F32",
VCVT_GT_FXS16_F32: "VCVT.GT.FXS16.F32",
VCVT_LE_FXS16_F32: "VCVT.LE.FXS16.F32",
VCVT_FXS16_F32: "VCVT.FXS16.F32",
VCVT_ZZ_FXS16_F32: "VCVT.ZZ.FXS16.F32",
VCVT_EQ_FXS16_F64: "VCVT.EQ.FXS16.F64",
VCVT_NE_FXS16_F64: "VCVT.NE.FXS16.F64",
VCVT_CS_FXS16_F64: "VCVT.CS.FXS16.F64",
VCVT_CC_FXS16_F64: "VCVT.CC.FXS16.F64",
VCVT_MI_FXS16_F64: "VCVT.MI.FXS16.F64",
VCVT_PL_FXS16_F64: "VCVT.PL.FXS16.F64",
VCVT_VS_FXS16_F64: "VCVT.VS.FXS16.F64",
VCVT_VC_FXS16_F64: "VCVT.VC.FXS16.F64",
VCVT_HI_FXS16_F64: "VCVT.HI.FXS16.F64",
VCVT_LS_FXS16_F64: "VCVT.LS.FXS16.F64",
VCVT_GE_FXS16_F64: "VCVT.GE.FXS16.F64",
VCVT_LT_FXS16_F64: "VCVT.LT.FXS16.F64",
VCVT_GT_FXS16_F64: "VCVT.GT.FXS16.F64",
VCVT_LE_FXS16_F64: "VCVT.LE.FXS16.F64",
VCVT_FXS16_F64: "VCVT.FXS16.F64",
VCVT_ZZ_FXS16_F64: "VCVT.ZZ.FXS16.F64",
VCVT_EQ_FXS32_F32: "VCVT.EQ.FXS32.F32",
VCVT_NE_FXS32_F32: "VCVT.NE.FXS32.F32",
VCVT_CS_FXS32_F32: "VCVT.CS.FXS32.F32",
VCVT_CC_FXS32_F32: "VCVT.CC.FXS32.F32",
VCVT_MI_FXS32_F32: "VCVT.MI.FXS32.F32",
VCVT_PL_FXS32_F32: "VCVT.PL.FXS32.F32",
VCVT_VS_FXS32_F32: "VCVT.VS.FXS32.F32",
VCVT_VC_FXS32_F32: "VCVT.VC.FXS32.F32",
VCVT_HI_FXS32_F32: "VCVT.HI.FXS32.F32",
VCVT_LS_FXS32_F32: "VCVT.LS.FXS32.F32",
VCVT_GE_FXS32_F32: "VCVT.GE.FXS32.F32",
VCVT_LT_FXS32_F32: "VCVT.LT.FXS32.F32",
VCVT_GT_FXS32_F32: "VCVT.GT.FXS32.F32",
VCVT_LE_FXS32_F32: "VCVT.LE.FXS32.F32",
VCVT_FXS32_F32: "VCVT.FXS32.F32",
VCVT_ZZ_FXS32_F32: "VCVT.ZZ.FXS32.F32",
VCVT_EQ_FXS32_F64: "VCVT.EQ.FXS32.F64",
VCVT_NE_FXS32_F64: "VCVT.NE.FXS32.F64",
VCVT_CS_FXS32_F64: "VCVT.CS.FXS32.F64",
VCVT_CC_FXS32_F64: "VCVT.CC.FXS32.F64",
VCVT_MI_FXS32_F64: "VCVT.MI.FXS32.F64",
VCVT_PL_FXS32_F64: "VCVT.PL.FXS32.F64",
VCVT_VS_FXS32_F64: "VCVT.VS.FXS32.F64",
VCVT_VC_FXS32_F64: "VCVT.VC.FXS32.F64",
VCVT_HI_FXS32_F64: "VCVT.HI.FXS32.F64",
VCVT_LS_FXS32_F64: "VCVT.LS.FXS32.F64",
VCVT_GE_FXS32_F64: "VCVT.GE.FXS32.F64",
VCVT_LT_FXS32_F64: "VCVT.LT.FXS32.F64",
VCVT_GT_FXS32_F64: "VCVT.GT.FXS32.F64",
VCVT_LE_FXS32_F64: "VCVT.LE.FXS32.F64",
VCVT_FXS32_F64: "VCVT.FXS32.F64",
VCVT_ZZ_FXS32_F64: "VCVT.ZZ.FXS32.F64",
VCVT_EQ_FXU16_F32: "VCVT.EQ.FXU16.F32",
VCVT_NE_FXU16_F32: "VCVT.NE.FXU16.F32",
VCVT_CS_FXU16_F32: "VCVT.CS.FXU16.F32",
VCVT_CC_FXU16_F32: "VCVT.CC.FXU16.F32",
VCVT_MI_FXU16_F32: "VCVT.MI.FXU16.F32",
VCVT_PL_FXU16_F32: "VCVT.PL.FXU16.F32",
VCVT_VS_FXU16_F32: "VCVT.VS.FXU16.F32",
VCVT_VC_FXU16_F32: "VCVT.VC.FXU16.F32",
VCVT_HI_FXU16_F32: "VCVT.HI.FXU16.F32",
VCVT_LS_FXU16_F32: "VCVT.LS.FXU16.F32",
VCVT_GE_FXU16_F32: "VCVT.GE.FXU16.F32",
VCVT_LT_FXU16_F32: "VCVT.LT.FXU16.F32",
VCVT_GT_FXU16_F32: "VCVT.GT.FXU16.F32",
VCVT_LE_FXU16_F32: "VCVT.LE.FXU16.F32",
VCVT_FXU16_F32: "VCVT.FXU16.F32",
VCVT_ZZ_FXU16_F32: "VCVT.ZZ.FXU16.F32",
VCVT_EQ_FXU16_F64: "VCVT.EQ.FXU16.F64",
VCVT_NE_FXU16_F64: "VCVT.NE.FXU16.F64",
VCVT_CS_FXU16_F64: "VCVT.CS.FXU16.F64",
VCVT_CC_FXU16_F64: "VCVT.CC.FXU16.F64",
VCVT_MI_FXU16_F64: "VCVT.MI.FXU16.F64",
VCVT_PL_FXU16_F64: "VCVT.PL.FXU16.F64",
VCVT_VS_FXU16_F64: "VCVT.VS.FXU16.F64",
VCVT_VC_FXU16_F64: "VCVT.VC.FXU16.F64",
VCVT_HI_FXU16_F64: "VCVT.HI.FXU16.F64",
VCVT_LS_FXU16_F64: "VCVT.LS.FXU16.F64",
VCVT_GE_FXU16_F64: "VCVT.GE.FXU16.F64",
VCVT_LT_FXU16_F64: "VCVT.LT.FXU16.F64",
VCVT_GT_FXU16_F64: "VCVT.GT.FXU16.F64",
VCVT_LE_FXU16_F64: "VCVT.LE.FXU16.F64",
VCVT_FXU16_F64: "VCVT.FXU16.F64",
VCVT_ZZ_FXU16_F64: "VCVT.ZZ.FXU16.F64",
VCVT_EQ_FXU32_F32: "VCVT.EQ.FXU32.F32",
VCVT_NE_FXU32_F32: "VCVT.NE.FXU32.F32",
VCVT_CS_FXU32_F32: "VCVT.CS.FXU32.F32",
VCVT_CC_FXU32_F32: "VCVT.CC.FXU32.F32",
VCVT_MI_FXU32_F32: "VCVT.MI.FXU32.F32",
VCVT_PL_FXU32_F32: "VCVT.PL.FXU32.F32",
VCVT_VS_FXU32_F32: "VCVT.VS.FXU32.F32",
VCVT_VC_FXU32_F32: "VCVT.VC.FXU32.F32",
VCVT_HI_FXU32_F32: "VCVT.HI.FXU32.F32",
VCVT_LS_FXU32_F32: "VCVT.LS.FXU32.F32",
VCVT_GE_FXU32_F32: "VCVT.GE.FXU32.F32",
VCVT_LT_FXU32_F32: "VCVT.LT.FXU32.F32",
VCVT_GT_FXU32_F32: "VCVT.GT.FXU32.F32",
VCVT_LE_FXU32_F32: "VCVT.LE.FXU32.F32",
VCVT_FXU32_F32: "VCVT.FXU32.F32",
VCVT_ZZ_FXU32_F32: "VCVT.ZZ.FXU32.F32",
VCVT_EQ_FXU32_F64: "VCVT.EQ.FXU32.F64",
VCVT_NE_FXU32_F64: "VCVT.NE.FXU32.F64",
VCVT_CS_FXU32_F64: "VCVT.CS.FXU32.F64",
VCVT_CC_FXU32_F64: "VCVT.CC.FXU32.F64",
VCVT_MI_FXU32_F64: "VCVT.MI.FXU32.F64",
VCVT_PL_FXU32_F64: "VCVT.PL.FXU32.F64",
VCVT_VS_FXU32_F64: "VCVT.VS.FXU32.F64",
VCVT_VC_FXU32_F64: "VCVT.VC.FXU32.F64",
VCVT_HI_FXU32_F64: "VCVT.HI.FXU32.F64",
VCVT_LS_FXU32_F64: "VCVT.LS.FXU32.F64",
VCVT_GE_FXU32_F64: "VCVT.GE.FXU32.F64",
VCVT_LT_FXU32_F64: "VCVT.LT.FXU32.F64",
VCVT_GT_FXU32_F64: "VCVT.GT.FXU32.F64",
VCVT_LE_FXU32_F64: "VCVT.LE.FXU32.F64",
VCVT_FXU32_F64: "VCVT.FXU32.F64",
VCVT_ZZ_FXU32_F64: "VCVT.ZZ.FXU32.F64",
VCVTB_EQ_F32_F16: "VCVTB.EQ.F32.F16",
VCVTB_NE_F32_F16: "VCVTB.NE.F32.F16",
VCVTB_CS_F32_F16: "VCVTB.CS.F32.F16",
VCVTB_CC_F32_F16: "VCVTB.CC.F32.F16",
VCVTB_MI_F32_F16: "VCVTB.MI.F32.F16",
VCVTB_PL_F32_F16: "VCVTB.PL.F32.F16",
VCVTB_VS_F32_F16: "VCVTB.VS.F32.F16",
VCVTB_VC_F32_F16: "VCVTB.VC.F32.F16",
VCVTB_HI_F32_F16: "VCVTB.HI.F32.F16",
VCVTB_LS_F32_F16: "VCVTB.LS.F32.F16",
VCVTB_GE_F32_F16: "VCVTB.GE.F32.F16",
VCVTB_LT_F32_F16: "VCVTB.LT.F32.F16",
VCVTB_GT_F32_F16: "VCVTB.GT.F32.F16",
VCVTB_LE_F32_F16: "VCVTB.LE.F32.F16",
VCVTB_F32_F16: "VCVTB.F32.F16",
VCVTB_ZZ_F32_F16: "VCVTB.ZZ.F32.F16",
VCVTB_EQ_F16_F32: "VCVTB.EQ.F16.F32",
VCVTB_NE_F16_F32: "VCVTB.NE.F16.F32",
VCVTB_CS_F16_F32: "VCVTB.CS.F16.F32",
VCVTB_CC_F16_F32: "VCVTB.CC.F16.F32",
VCVTB_MI_F16_F32: "VCVTB.MI.F16.F32",
VCVTB_PL_F16_F32: "VCVTB.PL.F16.F32",
VCVTB_VS_F16_F32: "VCVTB.VS.F16.F32",
VCVTB_VC_F16_F32: "VCVTB.VC.F16.F32",
VCVTB_HI_F16_F32: "VCVTB.HI.F16.F32",
VCVTB_LS_F16_F32: "VCVTB.LS.F16.F32",
VCVTB_GE_F16_F32: "VCVTB.GE.F16.F32",
VCVTB_LT_F16_F32: "VCVTB.LT.F16.F32",
VCVTB_GT_F16_F32: "VCVTB.GT.F16.F32",
VCVTB_LE_F16_F32: "VCVTB.LE.F16.F32",
VCVTB_F16_F32: "VCVTB.F16.F32",
VCVTB_ZZ_F16_F32: "VCVTB.ZZ.F16.F32",
VCVTT_EQ_F32_F16: "VCVTT.EQ.F32.F16",
VCVTT_NE_F32_F16: "VCVTT.NE.F32.F16",
VCVTT_CS_F32_F16: "VCVTT.CS.F32.F16",
VCVTT_CC_F32_F16: "VCVTT.CC.F32.F16",
VCVTT_MI_F32_F16: "VCVTT.MI.F32.F16",
VCVTT_PL_F32_F16: "VCVTT.PL.F32.F16",
VCVTT_VS_F32_F16: "VCVTT.VS.F32.F16",
VCVTT_VC_F32_F16: "VCVTT.VC.F32.F16",
VCVTT_HI_F32_F16: "VCVTT.HI.F32.F16",
VCVTT_LS_F32_F16: "VCVTT.LS.F32.F16",
VCVTT_GE_F32_F16: "VCVTT.GE.F32.F16",
VCVTT_LT_F32_F16: "VCVTT.LT.F32.F16",
VCVTT_GT_F32_F16: "VCVTT.GT.F32.F16",
VCVTT_LE_F32_F16: "VCVTT.LE.F32.F16",
VCVTT_F32_F16: "VCVTT.F32.F16",
VCVTT_ZZ_F32_F16: "VCVTT.ZZ.F32.F16",
VCVTT_EQ_F16_F32: "VCVTT.EQ.F16.F32",
VCVTT_NE_F16_F32: "VCVTT.NE.F16.F32",
VCVTT_CS_F16_F32: "VCVTT.CS.F16.F32",
VCVTT_CC_F16_F32: "VCVTT.CC.F16.F32",
VCVTT_MI_F16_F32: "VCVTT.MI.F16.F32",
VCVTT_PL_F16_F32: "VCVTT.PL.F16.F32",
VCVTT_VS_F16_F32: "VCVTT.VS.F16.F32",
VCVTT_VC_F16_F32: "VCVTT.VC.F16.F32",
VCVTT_HI_F16_F32: "VCVTT.HI.F16.F32",
VCVTT_LS_F16_F32: "VCVTT.LS.F16.F32",
VCVTT_GE_F16_F32: "VCVTT.GE.F16.F32",
VCVTT_LT_F16_F32: "VCVTT.LT.F16.F32",
VCVTT_GT_F16_F32: "VCVTT.GT.F16.F32",
VCVTT_LE_F16_F32: "VCVTT.LE.F16.F32",
VCVTT_F16_F32: "VCVTT.F16.F32",
VCVTT_ZZ_F16_F32: "VCVTT.ZZ.F16.F32",
VCVTR_EQ_U32_F32: "VCVTR.EQ.U32.F32",
VCVTR_NE_U32_F32: "VCVTR.NE.U32.F32",
VCVTR_CS_U32_F32: "VCVTR.CS.U32.F32",
VCVTR_CC_U32_F32: "VCVTR.CC.U32.F32",
VCVTR_MI_U32_F32: "VCVTR.MI.U32.F32",
VCVTR_PL_U32_F32: "VCVTR.PL.U32.F32",
VCVTR_VS_U32_F32: "VCVTR.VS.U32.F32",
VCVTR_VC_U32_F32: "VCVTR.VC.U32.F32",
VCVTR_HI_U32_F32: "VCVTR.HI.U32.F32",
VCVTR_LS_U32_F32: "VCVTR.LS.U32.F32",
VCVTR_GE_U32_F32: "VCVTR.GE.U32.F32",
VCVTR_LT_U32_F32: "VCVTR.LT.U32.F32",
VCVTR_GT_U32_F32: "VCVTR.GT.U32.F32",
VCVTR_LE_U32_F32: "VCVTR.LE.U32.F32",
VCVTR_U32_F32: "VCVTR.U32.F32",
VCVTR_ZZ_U32_F32: "VCVTR.ZZ.U32.F32",
VCVTR_EQ_U32_F64: "VCVTR.EQ.U32.F64",
VCVTR_NE_U32_F64: "VCVTR.NE.U32.F64",
VCVTR_CS_U32_F64: "VCVTR.CS.U32.F64",
VCVTR_CC_U32_F64: "VCVTR.CC.U32.F64",
VCVTR_MI_U32_F64: "VCVTR.MI.U32.F64",
VCVTR_PL_U32_F64: "VCVTR.PL.U32.F64",
VCVTR_VS_U32_F64: "VCVTR.VS.U32.F64",
VCVTR_VC_U32_F64: "VCVTR.VC.U32.F64",
VCVTR_HI_U32_F64: "VCVTR.HI.U32.F64",
VCVTR_LS_U32_F64: "VCVTR.LS.U32.F64",
VCVTR_GE_U32_F64: "VCVTR.GE.U32.F64",
VCVTR_LT_U32_F64: "VCVTR.LT.U32.F64",
VCVTR_GT_U32_F64: "VCVTR.GT.U32.F64",
VCVTR_LE_U32_F64: "VCVTR.LE.U32.F64",
VCVTR_U32_F64: "VCVTR.U32.F64",
VCVTR_ZZ_U32_F64: "VCVTR.ZZ.U32.F64",
VCVTR_EQ_S32_F32: "VCVTR.EQ.S32.F32",
VCVTR_NE_S32_F32: "VCVTR.NE.S32.F32",
VCVTR_CS_S32_F32: "VCVTR.CS.S32.F32",
VCVTR_CC_S32_F32: "VCVTR.CC.S32.F32",
VCVTR_MI_S32_F32: "VCVTR.MI.S32.F32",
VCVTR_PL_S32_F32: "VCVTR.PL.S32.F32",
VCVTR_VS_S32_F32: "VCVTR.VS.S32.F32",
VCVTR_VC_S32_F32: "VCVTR.VC.S32.F32",
VCVTR_HI_S32_F32: "VCVTR.HI.S32.F32",
VCVTR_LS_S32_F32: "VCVTR.LS.S32.F32",
VCVTR_GE_S32_F32: "VCVTR.GE.S32.F32",
VCVTR_LT_S32_F32: "VCVTR.LT.S32.F32",
VCVTR_GT_S32_F32: "VCVTR.GT.S32.F32",
VCVTR_LE_S32_F32: "VCVTR.LE.S32.F32",
VCVTR_S32_F32: "VCVTR.S32.F32",
VCVTR_ZZ_S32_F32: "VCVTR.ZZ.S32.F32",
VCVTR_EQ_S32_F64: "VCVTR.EQ.S32.F64",
VCVTR_NE_S32_F64: "VCVTR.NE.S32.F64",
VCVTR_CS_S32_F64: "VCVTR.CS.S32.F64",
VCVTR_CC_S32_F64: "VCVTR.CC.S32.F64",
VCVTR_MI_S32_F64: "VCVTR.MI.S32.F64",
VCVTR_PL_S32_F64: "VCVTR.PL.S32.F64",
VCVTR_VS_S32_F64: "VCVTR.VS.S32.F64",
VCVTR_VC_S32_F64: "VCVTR.VC.S32.F64",
VCVTR_HI_S32_F64: "VCVTR.HI.S32.F64",
VCVTR_LS_S32_F64: "VCVTR.LS.S32.F64",
VCVTR_GE_S32_F64: "VCVTR.GE.S32.F64",
VCVTR_LT_S32_F64: "VCVTR.LT.S32.F64",
VCVTR_GT_S32_F64: "VCVTR.GT.S32.F64",
VCVTR_LE_S32_F64: "VCVTR.LE.S32.F64",
VCVTR_S32_F64: "VCVTR.S32.F64",
VCVTR_ZZ_S32_F64: "VCVTR.ZZ.S32.F64",
VCVT_EQ_U32_F32: "VCVT.EQ.U32.F32",
VCVT_NE_U32_F32: "VCVT.NE.U32.F32",
VCVT_CS_U32_F32: "VCVT.CS.U32.F32",
VCVT_CC_U32_F32: "VCVT.CC.U32.F32",
VCVT_MI_U32_F32: "VCVT.MI.U32.F32",
VCVT_PL_U32_F32: "VCVT.PL.U32.F32",
VCVT_VS_U32_F32: "VCVT.VS.U32.F32",
VCVT_VC_U32_F32: "VCVT.VC.U32.F32",
VCVT_HI_U32_F32: "VCVT.HI.U32.F32",
VCVT_LS_U32_F32: "VCVT.LS.U32.F32",
VCVT_GE_U32_F32: "VCVT.GE.U32.F32",
VCVT_LT_U32_F32: "VCVT.LT.U32.F32",
VCVT_GT_U32_F32: "VCVT.GT.U32.F32",
VCVT_LE_U32_F32: "VCVT.LE.U32.F32",
VCVT_U32_F32: "VCVT.U32.F32",
VCVT_ZZ_U32_F32: "VCVT.ZZ.U32.F32",
VCVT_EQ_U32_F64: "VCVT.EQ.U32.F64",
VCVT_NE_U32_F64: "VCVT.NE.U32.F64",
VCVT_CS_U32_F64: "VCVT.CS.U32.F64",
VCVT_CC_U32_F64: "VCVT.CC.U32.F64",
VCVT_MI_U32_F64: "VCVT.MI.U32.F64",
VCVT_PL_U32_F64: "VCVT.PL.U32.F64",
VCVT_VS_U32_F64: "VCVT.VS.U32.F64",
VCVT_VC_U32_F64: "VCVT.VC.U32.F64",
VCVT_HI_U32_F64: "VCVT.HI.U32.F64",
VCVT_LS_U32_F64: "VCVT.LS.U32.F64",
VCVT_GE_U32_F64: "VCVT.GE.U32.F64",
VCVT_LT_U32_F64: "VCVT.LT.U32.F64",
VCVT_GT_U32_F64: "VCVT.GT.U32.F64",
VCVT_LE_U32_F64: "VCVT.LE.U32.F64",
VCVT_U32_F64: "VCVT.U32.F64",
VCVT_ZZ_U32_F64: "VCVT.ZZ.U32.F64",
VCVT_EQ_S32_F32: "VCVT.EQ.S32.F32",
VCVT_NE_S32_F32: "VCVT.NE.S32.F32",
VCVT_CS_S32_F32: "VCVT.CS.S32.F32",
VCVT_CC_S32_F32: "VCVT.CC.S32.F32",
VCVT_MI_S32_F32: "VCVT.MI.S32.F32",
VCVT_PL_S32_F32: "VCVT.PL.S32.F32",
VCVT_VS_S32_F32: "VCVT.VS.S32.F32",
VCVT_VC_S32_F32: "VCVT.VC.S32.F32",
VCVT_HI_S32_F32: "VCVT.HI.S32.F32",
VCVT_LS_S32_F32: "VCVT.LS.S32.F32",
VCVT_GE_S32_F32: "VCVT.GE.S32.F32",
VCVT_LT_S32_F32: "VCVT.LT.S32.F32",
VCVT_GT_S32_F32: "VCVT.GT.S32.F32",
VCVT_LE_S32_F32: "VCVT.LE.S32.F32",
VCVT_S32_F32: "VCVT.S32.F32",
VCVT_ZZ_S32_F32: "VCVT.ZZ.S32.F32",
VCVT_EQ_S32_F64: "VCVT.EQ.S32.F64",
VCVT_NE_S32_F64: "VCVT.NE.S32.F64",
VCVT_CS_S32_F64: "VCVT.CS.S32.F64",
VCVT_CC_S32_F64: "VCVT.CC.S32.F64",
VCVT_MI_S32_F64: "VCVT.MI.S32.F64",
VCVT_PL_S32_F64: "VCVT.PL.S32.F64",
VCVT_VS_S32_F64: "VCVT.VS.S32.F64",
VCVT_VC_S32_F64: "VCVT.VC.S32.F64",
VCVT_HI_S32_F64: "VCVT.HI.S32.F64",
VCVT_LS_S32_F64: "VCVT.LS.S32.F64",
VCVT_GE_S32_F64: "VCVT.GE.S32.F64",
VCVT_LT_S32_F64: "VCVT.LT.S32.F64",
VCVT_GT_S32_F64: "VCVT.GT.S32.F64",
VCVT_LE_S32_F64: "VCVT.LE.S32.F64",
VCVT_S32_F64: "VCVT.S32.F64",
VCVT_ZZ_S32_F64: "VCVT.ZZ.S32.F64",
VDIV_EQ_F32: "VDIV.EQ.F32",
VDIV_NE_F32: "VDIV.NE.F32",
VDIV_CS_F32: "VDIV.CS.F32",
VDIV_CC_F32: "VDIV.CC.F32",
VDIV_MI_F32: "VDIV.MI.F32",
VDIV_PL_F32: "VDIV.PL.F32",
VDIV_VS_F32: "VDIV.VS.F32",
VDIV_VC_F32: "VDIV.VC.F32",
VDIV_HI_F32: "VDIV.HI.F32",
VDIV_LS_F32: "VDIV.LS.F32",
VDIV_GE_F32: "VDIV.GE.F32",
VDIV_LT_F32: "VDIV.LT.F32",
VDIV_GT_F32: "VDIV.GT.F32",
VDIV_LE_F32: "VDIV.LE.F32",
VDIV_F32: "VDIV.F32",
VDIV_ZZ_F32: "VDIV.ZZ.F32",
VDIV_EQ_F64: "VDIV.EQ.F64",
VDIV_NE_F64: "VDIV.NE.F64",
VDIV_CS_F64: "VDIV.CS.F64",
VDIV_CC_F64: "VDIV.CC.F64",
VDIV_MI_F64: "VDIV.MI.F64",
VDIV_PL_F64: "VDIV.PL.F64",
VDIV_VS_F64: "VDIV.VS.F64",
VDIV_VC_F64: "VDIV.VC.F64",
VDIV_HI_F64: "VDIV.HI.F64",
VDIV_LS_F64: "VDIV.LS.F64",
VDIV_GE_F64: "VDIV.GE.F64",
VDIV_LT_F64: "VDIV.LT.F64",
VDIV_GT_F64: "VDIV.GT.F64",
VDIV_LE_F64: "VDIV.LE.F64",
VDIV_F64: "VDIV.F64",
VDIV_ZZ_F64: "VDIV.ZZ.F64",
VLDR_EQ: "VLDR.EQ",
VLDR_NE: "VLDR.NE",
VLDR_CS: "VLDR.CS",
VLDR_CC: "VLDR.CC",
VLDR_MI: "VLDR.MI",
VLDR_PL: "VLDR.PL",
VLDR_VS: "VLDR.VS",
VLDR_VC: "VLDR.VC",
VLDR_HI: "VLDR.HI",
VLDR_LS: "VLDR.LS",
VLDR_GE: "VLDR.GE",
VLDR_LT: "VLDR.LT",
VLDR_GT: "VLDR.GT",
VLDR_LE: "VLDR.LE",
VLDR: "VLDR",
VLDR_ZZ: "VLDR.ZZ",
VMLA_EQ_F32: "VMLA.EQ.F32",
VMLA_NE_F32: "VMLA.NE.F32",
VMLA_CS_F32: "VMLA.CS.F32",
VMLA_CC_F32: "VMLA.CC.F32",
VMLA_MI_F32: "VMLA.MI.F32",
VMLA_PL_F32: "VMLA.PL.F32",
VMLA_VS_F32: "VMLA.VS.F32",
VMLA_VC_F32: "VMLA.VC.F32",
VMLA_HI_F32: "VMLA.HI.F32",
VMLA_LS_F32: "VMLA.LS.F32",
VMLA_GE_F32: "VMLA.GE.F32",
VMLA_LT_F32: "VMLA.LT.F32",
VMLA_GT_F32: "VMLA.GT.F32",
VMLA_LE_F32: "VMLA.LE.F32",
VMLA_F32: "VMLA.F32",
VMLA_ZZ_F32: "VMLA.ZZ.F32",
VMLA_EQ_F64: "VMLA.EQ.F64",
VMLA_NE_F64: "VMLA.NE.F64",
VMLA_CS_F64: "VMLA.CS.F64",
VMLA_CC_F64: "VMLA.CC.F64",
VMLA_MI_F64: "VMLA.MI.F64",
VMLA_PL_F64: "VMLA.PL.F64",
VMLA_VS_F64: "VMLA.VS.F64",
VMLA_VC_F64: "VMLA.VC.F64",
VMLA_HI_F64: "VMLA.HI.F64",
VMLA_LS_F64: "VMLA.LS.F64",
VMLA_GE_F64: "VMLA.GE.F64",
VMLA_LT_F64: "VMLA.LT.F64",
VMLA_GT_F64: "VMLA.GT.F64",
VMLA_LE_F64: "VMLA.LE.F64",
VMLA_F64: "VMLA.F64",
VMLA_ZZ_F64: "VMLA.ZZ.F64",
VMLS_EQ_F32: "VMLS.EQ.F32",
VMLS_NE_F32: "VMLS.NE.F32",
VMLS_CS_F32: "VMLS.CS.F32",
VMLS_CC_F32: "VMLS.CC.F32",
VMLS_MI_F32: "VMLS.MI.F32",
VMLS_PL_F32: "VMLS.PL.F32",
VMLS_VS_F32: "VMLS.VS.F32",
VMLS_VC_F32: "VMLS.VC.F32",
VMLS_HI_F32: "VMLS.HI.F32",
VMLS_LS_F32: "VMLS.LS.F32",
VMLS_GE_F32: "VMLS.GE.F32",
VMLS_LT_F32: "VMLS.LT.F32",
VMLS_GT_F32: "VMLS.GT.F32",
VMLS_LE_F32: "VMLS.LE.F32",
VMLS_F32: "VMLS.F32",
VMLS_ZZ_F32: "VMLS.ZZ.F32",
VMLS_EQ_F64: "VMLS.EQ.F64",
VMLS_NE_F64: "VMLS.NE.F64",
VMLS_CS_F64: "VMLS.CS.F64",
VMLS_CC_F64: "VMLS.CC.F64",
VMLS_MI_F64: "VMLS.MI.F64",
VMLS_PL_F64: "VMLS.PL.F64",
VMLS_VS_F64: "VMLS.VS.F64",
VMLS_VC_F64: "VMLS.VC.F64",
VMLS_HI_F64: "VMLS.HI.F64",
VMLS_LS_F64: "VMLS.LS.F64",
VMLS_GE_F64: "VMLS.GE.F64",
VMLS_LT_F64: "VMLS.LT.F64",
VMLS_GT_F64: "VMLS.GT.F64",
VMLS_LE_F64: "VMLS.LE.F64",
VMLS_F64: "VMLS.F64",
VMLS_ZZ_F64: "VMLS.ZZ.F64",
VMOV_EQ: "VMOV.EQ",
VMOV_NE: "VMOV.NE",
VMOV_CS: "VMOV.CS",
VMOV_CC: "VMOV.CC",
VMOV_MI: "VMOV.MI",
VMOV_PL: "VMOV.PL",
VMOV_VS: "VMOV.VS",
VMOV_VC: "VMOV.VC",
VMOV_HI: "VMOV.HI",
VMOV_LS: "VMOV.LS",
VMOV_GE: "VMOV.GE",
VMOV_LT: "VMOV.LT",
VMOV_GT: "VMOV.GT",
VMOV_LE: "VMOV.LE",
VMOV: "VMOV",
VMOV_ZZ: "VMOV.ZZ",
VMOV_EQ_32: "VMOV.EQ.32",
VMOV_NE_32: "VMOV.NE.32",
VMOV_CS_32: "VMOV.CS.32",
VMOV_CC_32: "VMOV.CC.32",
VMOV_MI_32: "VMOV.MI.32",
VMOV_PL_32: "VMOV.PL.32",
VMOV_VS_32: "VMOV.VS.32",
VMOV_VC_32: "VMOV.VC.32",
VMOV_HI_32: "VMOV.HI.32",
VMOV_LS_32: "VMOV.LS.32",
VMOV_GE_32: "VMOV.GE.32",
VMOV_LT_32: "VMOV.LT.32",
VMOV_GT_32: "VMOV.GT.32",
VMOV_LE_32: "VMOV.LE.32",
VMOV_32: "VMOV.32",
VMOV_ZZ_32: "VMOV.ZZ.32",
VMOV_EQ_F32: "VMOV.EQ.F32",
VMOV_NE_F32: "VMOV.NE.F32",
VMOV_CS_F32: "VMOV.CS.F32",
VMOV_CC_F32: "VMOV.CC.F32",
VMOV_MI_F32: "VMOV.MI.F32",
VMOV_PL_F32: "VMOV.PL.F32",
VMOV_VS_F32: "VMOV.VS.F32",
VMOV_VC_F32: "VMOV.VC.F32",
VMOV_HI_F32: "VMOV.HI.F32",
VMOV_LS_F32: "VMOV.LS.F32",
VMOV_GE_F32: "VMOV.GE.F32",
VMOV_LT_F32: "VMOV.LT.F32",
VMOV_GT_F32: "VMOV.GT.F32",
VMOV_LE_F32: "VMOV.LE.F32",
VMOV_F32: "VMOV.F32",
VMOV_ZZ_F32: "VMOV.ZZ.F32",
VMOV_EQ_F64: "VMOV.EQ.F64",
VMOV_NE_F64: "VMOV.NE.F64",
VMOV_CS_F64: "VMOV.CS.F64",
VMOV_CC_F64: "VMOV.CC.F64",
VMOV_MI_F64: "VMOV.MI.F64",
VMOV_PL_F64: "VMOV.PL.F64",
VMOV_VS_F64: "VMOV.VS.F64",
VMOV_VC_F64: "VMOV.VC.F64",
VMOV_HI_F64: "VMOV.HI.F64",
VMOV_LS_F64: "VMOV.LS.F64",
VMOV_GE_F64: "VMOV.GE.F64",
VMOV_LT_F64: "VMOV.LT.F64",
VMOV_GT_F64: "VMOV.GT.F64",
VMOV_LE_F64: "VMOV.LE.F64",
VMOV_F64: "VMOV.F64",
VMOV_ZZ_F64: "VMOV.ZZ.F64",
VMRS_EQ: "VMRS.EQ",
VMRS_NE: "VMRS.NE",
VMRS_CS: "VMRS.CS",
VMRS_CC: "VMRS.CC",
VMRS_MI: "VMRS.MI",
VMRS_PL: "VMRS.PL",
VMRS_VS: "VMRS.VS",
VMRS_VC: "VMRS.VC",
VMRS_HI: "VMRS.HI",
VMRS_LS: "VMRS.LS",
VMRS_GE: "VMRS.GE",
VMRS_LT: "VMRS.LT",
VMRS_GT: "VMRS.GT",
VMRS_LE: "VMRS.LE",
VMRS: "VMRS",
VMRS_ZZ: "VMRS.ZZ",
VMSR_EQ: "VMSR.EQ",
VMSR_NE: "VMSR.NE",
VMSR_CS: "VMSR.CS",
VMSR_CC: "VMSR.CC",
VMSR_MI: "VMSR.MI",
VMSR_PL: "VMSR.PL",
VMSR_VS: "VMSR.VS",
VMSR_VC: "VMSR.VC",
VMSR_HI: "VMSR.HI",
VMSR_LS: "VMSR.LS",
VMSR_GE: "VMSR.GE",
VMSR_LT: "VMSR.LT",
VMSR_GT: "VMSR.GT",
VMSR_LE: "VMSR.LE",
VMSR: "VMSR",
VMSR_ZZ: "VMSR.ZZ",
VMUL_EQ_F32: "VMUL.EQ.F32",
VMUL_NE_F32: "VMUL.NE.F32",
VMUL_CS_F32: "VMUL.CS.F32",
VMUL_CC_F32: "VMUL.CC.F32",
VMUL_MI_F32: "VMUL.MI.F32",
VMUL_PL_F32: "VMUL.PL.F32",
VMUL_VS_F32: "VMUL.VS.F32",
VMUL_VC_F32: "VMUL.VC.F32",
VMUL_HI_F32: "VMUL.HI.F32",
VMUL_LS_F32: "VMUL.LS.F32",
VMUL_GE_F32: "VMUL.GE.F32",
VMUL_LT_F32: "VMUL.LT.F32",
VMUL_GT_F32: "VMUL.GT.F32",
VMUL_LE_F32: "VMUL.LE.F32",
VMUL_F32: "VMUL.F32",
VMUL_ZZ_F32: "VMUL.ZZ.F32",
VMUL_EQ_F64: "VMUL.EQ.F64",
VMUL_NE_F64: "VMUL.NE.F64",
VMUL_CS_F64: "VMUL.CS.F64",
VMUL_CC_F64: "VMUL.CC.F64",
VMUL_MI_F64: "VMUL.MI.F64",
VMUL_PL_F64: "VMUL.PL.F64",
VMUL_VS_F64: "VMUL.VS.F64",
VMUL_VC_F64: "VMUL.VC.F64",
VMUL_HI_F64: "VMUL.HI.F64",
VMUL_LS_F64: "VMUL.LS.F64",
VMUL_GE_F64: "VMUL.GE.F64",
VMUL_LT_F64: "VMUL.LT.F64",
VMUL_GT_F64: "VMUL.GT.F64",
VMUL_LE_F64: "VMUL.LE.F64",
VMUL_F64: "VMUL.F64",
VMUL_ZZ_F64: "VMUL.ZZ.F64",
VNEG_EQ_F32: "VNEG.EQ.F32",
VNEG_NE_F32: "VNEG.NE.F32",
VNEG_CS_F32: "VNEG.CS.F32",
VNEG_CC_F32: "VNEG.CC.F32",
VNEG_MI_F32: "VNEG.MI.F32",
VNEG_PL_F32: "VNEG.PL.F32",
VNEG_VS_F32: "VNEG.VS.F32",
VNEG_VC_F32: "VNEG.VC.F32",
VNEG_HI_F32: "VNEG.HI.F32",
VNEG_LS_F32: "VNEG.LS.F32",
VNEG_GE_F32: "VNEG.GE.F32",
VNEG_LT_F32: "VNEG.LT.F32",
VNEG_GT_F32: "VNEG.GT.F32",
VNEG_LE_F32: "VNEG.LE.F32",
VNEG_F32: "VNEG.F32",
VNEG_ZZ_F32: "VNEG.ZZ.F32",
VNEG_EQ_F64: "VNEG.EQ.F64",
VNEG_NE_F64: "VNEG.NE.F64",
VNEG_CS_F64: "VNEG.CS.F64",
VNEG_CC_F64: "VNEG.CC.F64",
VNEG_MI_F64: "VNEG.MI.F64",
VNEG_PL_F64: "VNEG.PL.F64",
VNEG_VS_F64: "VNEG.VS.F64",
VNEG_VC_F64: "VNEG.VC.F64",
VNEG_HI_F64: "VNEG.HI.F64",
VNEG_LS_F64: "VNEG.LS.F64",
VNEG_GE_F64: "VNEG.GE.F64",
VNEG_LT_F64: "VNEG.LT.F64",
VNEG_GT_F64: "VNEG.GT.F64",
VNEG_LE_F64: "VNEG.LE.F64",
VNEG_F64: "VNEG.F64",
VNEG_ZZ_F64: "VNEG.ZZ.F64",
VNMLS_EQ_F32: "VNMLS.EQ.F32",
VNMLS_NE_F32: "VNMLS.NE.F32",
VNMLS_CS_F32: "VNMLS.CS.F32",
VNMLS_CC_F32: "VNMLS.CC.F32",
VNMLS_MI_F32: "VNMLS.MI.F32",
VNMLS_PL_F32: "VNMLS.PL.F32",
VNMLS_VS_F32: "VNMLS.VS.F32",
VNMLS_VC_F32: "VNMLS.VC.F32",
VNMLS_HI_F32: "VNMLS.HI.F32",
VNMLS_LS_F32: "VNMLS.LS.F32",
VNMLS_GE_F32: "VNMLS.GE.F32",
VNMLS_LT_F32: "VNMLS.LT.F32",
VNMLS_GT_F32: "VNMLS.GT.F32",
VNMLS_LE_F32: "VNMLS.LE.F32",
VNMLS_F32: "VNMLS.F32",
VNMLS_ZZ_F32: "VNMLS.ZZ.F32",
VNMLS_EQ_F64: "VNMLS.EQ.F64",
VNMLS_NE_F64: "VNMLS.NE.F64",
VNMLS_CS_F64: "VNMLS.CS.F64",
VNMLS_CC_F64: "VNMLS.CC.F64",
VNMLS_MI_F64: "VNMLS.MI.F64",
VNMLS_PL_F64: "VNMLS.PL.F64",
VNMLS_VS_F64: "VNMLS.VS.F64",
VNMLS_VC_F64: "VNMLS.VC.F64",
VNMLS_HI_F64: "VNMLS.HI.F64",
VNMLS_LS_F64: "VNMLS.LS.F64",
VNMLS_GE_F64: "VNMLS.GE.F64",
VNMLS_LT_F64: "VNMLS.LT.F64",
VNMLS_GT_F64: "VNMLS.GT.F64",
VNMLS_LE_F64: "VNMLS.LE.F64",
VNMLS_F64: "VNMLS.F64",
VNMLS_ZZ_F64: "VNMLS.ZZ.F64",
VNMLA_EQ_F32: "VNMLA.EQ.F32",
VNMLA_NE_F32: "VNMLA.NE.F32",
VNMLA_CS_F32: "VNMLA.CS.F32",
VNMLA_CC_F32: "VNMLA.CC.F32",
VNMLA_MI_F32: "VNMLA.MI.F32",
VNMLA_PL_F32: "VNMLA.PL.F32",
VNMLA_VS_F32: "VNMLA.VS.F32",
VNMLA_VC_F32: "VNMLA.VC.F32",
VNMLA_HI_F32: "VNMLA.HI.F32",
VNMLA_LS_F32: "VNMLA.LS.F32",
VNMLA_GE_F32: "VNMLA.GE.F32",
VNMLA_LT_F32: "VNMLA.LT.F32",
VNMLA_GT_F32: "VNMLA.GT.F32",
VNMLA_LE_F32: "VNMLA.LE.F32",
VNMLA_F32: "VNMLA.F32",
VNMLA_ZZ_F32: "VNMLA.ZZ.F32",
VNMLA_EQ_F64: "VNMLA.EQ.F64",
VNMLA_NE_F64: "VNMLA.NE.F64",
VNMLA_CS_F64: "VNMLA.CS.F64",
VNMLA_CC_F64: "VNMLA.CC.F64",
VNMLA_MI_F64: "VNMLA.MI.F64",
VNMLA_PL_F64: "VNMLA.PL.F64",
VNMLA_VS_F64: "VNMLA.VS.F64",
VNMLA_VC_F64: "VNMLA.VC.F64",
VNMLA_HI_F64: "VNMLA.HI.F64",
VNMLA_LS_F64: "VNMLA.LS.F64",
VNMLA_GE_F64: "VNMLA.GE.F64",
VNMLA_LT_F64: "VNMLA.LT.F64",
VNMLA_GT_F64: "VNMLA.GT.F64",
VNMLA_LE_F64: "VNMLA.LE.F64",
VNMLA_F64: "VNMLA.F64",
VNMLA_ZZ_F64: "VNMLA.ZZ.F64",
VNMUL_EQ_F32: "VNMUL.EQ.F32",
VNMUL_NE_F32: "VNMUL.NE.F32",
VNMUL_CS_F32: "VNMUL.CS.F32",
VNMUL_CC_F32: "VNMUL.CC.F32",
VNMUL_MI_F32: "VNMUL.MI.F32",
VNMUL_PL_F32: "VNMUL.PL.F32",
VNMUL_VS_F32: "VNMUL.VS.F32",
VNMUL_VC_F32: "VNMUL.VC.F32",
VNMUL_HI_F32: "VNMUL.HI.F32",
VNMUL_LS_F32: "VNMUL.LS.F32",
VNMUL_GE_F32: "VNMUL.GE.F32",
VNMUL_LT_F32: "VNMUL.LT.F32",
VNMUL_GT_F32: "VNMUL.GT.F32",
VNMUL_LE_F32: "VNMUL.LE.F32",
VNMUL_F32: "VNMUL.F32",
VNMUL_ZZ_F32: "VNMUL.ZZ.F32",
VNMUL_EQ_F64: "VNMUL.EQ.F64",
VNMUL_NE_F64: "VNMUL.NE.F64",
VNMUL_CS_F64: "VNMUL.CS.F64",
VNMUL_CC_F64: "VNMUL.CC.F64",
VNMUL_MI_F64: "VNMUL.MI.F64",
VNMUL_PL_F64: "VNMUL.PL.F64",
VNMUL_VS_F64: "VNMUL.VS.F64",
VNMUL_VC_F64: "VNMUL.VC.F64",
VNMUL_HI_F64: "VNMUL.HI.F64",
VNMUL_LS_F64: "VNMUL.LS.F64",
VNMUL_GE_F64: "VNMUL.GE.F64",
VNMUL_LT_F64: "VNMUL.LT.F64",
VNMUL_GT_F64: "VNMUL.GT.F64",
VNMUL_LE_F64: "VNMUL.LE.F64",
VNMUL_F64: "VNMUL.F64",
VNMUL_ZZ_F64: "VNMUL.ZZ.F64",
VSQRT_EQ_F32: "VSQRT.EQ.F32",
VSQRT_NE_F32: "VSQRT.NE.F32",
VSQRT_CS_F32: "VSQRT.CS.F32",
VSQRT_CC_F32: "VSQRT.CC.F32",
VSQRT_MI_F32: "VSQRT.MI.F32",
VSQRT_PL_F32: "VSQRT.PL.F32",
VSQRT_VS_F32: "VSQRT.VS.F32",
VSQRT_VC_F32: "VSQRT.VC.F32",
VSQRT_HI_F32: "VSQRT.HI.F32",
VSQRT_LS_F32: "VSQRT.LS.F32",
VSQRT_GE_F32: "VSQRT.GE.F32",
VSQRT_LT_F32: "VSQRT.LT.F32",
VSQRT_GT_F32: "VSQRT.GT.F32",
VSQRT_LE_F32: "VSQRT.LE.F32",
VSQRT_F32: "VSQRT.F32",
VSQRT_ZZ_F32: "VSQRT.ZZ.F32",
VSQRT_EQ_F64: "VSQRT.EQ.F64",
VSQRT_NE_F64: "VSQRT.NE.F64",
VSQRT_CS_F64: "VSQRT.CS.F64",
VSQRT_CC_F64: "VSQRT.CC.F64",
VSQRT_MI_F64: "VSQRT.MI.F64",
VSQRT_PL_F64: "VSQRT.PL.F64",
VSQRT_VS_F64: "VSQRT.VS.F64",
VSQRT_VC_F64: "VSQRT.VC.F64",
VSQRT_HI_F64: "VSQRT.HI.F64",
VSQRT_LS_F64: "VSQRT.LS.F64",
VSQRT_GE_F64: "VSQRT.GE.F64",
VSQRT_LT_F64: "VSQRT.LT.F64",
VSQRT_GT_F64: "VSQRT.GT.F64",
VSQRT_LE_F64: "VSQRT.LE.F64",
VSQRT_F64: "VSQRT.F64",
VSQRT_ZZ_F64: "VSQRT.ZZ.F64",
VSTR_EQ: "VSTR.EQ",
VSTR_NE: "VSTR.NE",
VSTR_CS: "VSTR.CS",
VSTR_CC: "VSTR.CC",
VSTR_MI: "VSTR.MI",
VSTR_PL: "VSTR.PL",
VSTR_VS: "VSTR.VS",
VSTR_VC: "VSTR.VC",
VSTR_HI: "VSTR.HI",
VSTR_LS: "VSTR.LS",
VSTR_GE: "VSTR.GE",
VSTR_LT: "VSTR.LT",
VSTR_GT: "VSTR.GT",
VSTR_LE: "VSTR.LE",
VSTR: "VSTR",
VSTR_ZZ: "VSTR.ZZ",
VSUB_EQ_F32: "VSUB.EQ.F32",
VSUB_NE_F32: "VSUB.NE.F32",
VSUB_CS_F32: "VSUB.CS.F32",
VSUB_CC_F32: "VSUB.CC.F32",
VSUB_MI_F32: "VSUB.MI.F32",
VSUB_PL_F32: "VSUB.PL.F32",
VSUB_VS_F32: "VSUB.VS.F32",
VSUB_VC_F32: "VSUB.VC.F32",
VSUB_HI_F32: "VSUB.HI.F32",
VSUB_LS_F32: "VSUB.LS.F32",
VSUB_GE_F32: "VSUB.GE.F32",
VSUB_LT_F32: "VSUB.LT.F32",
VSUB_GT_F32: "VSUB.GT.F32",
VSUB_LE_F32: "VSUB.LE.F32",
VSUB_F32: "VSUB.F32",
VSUB_ZZ_F32: "VSUB.ZZ.F32",
VSUB_EQ_F64: "VSUB.EQ.F64",
VSUB_NE_F64: "VSUB.NE.F64",
VSUB_CS_F64: "VSUB.CS.F64",
VSUB_CC_F64: "VSUB.CC.F64",
VSUB_MI_F64: "VSUB.MI.F64",
VSUB_PL_F64: "VSUB.PL.F64",
VSUB_VS_F64: "VSUB.VS.F64",
VSUB_VC_F64: "VSUB.VC.F64",
VSUB_HI_F64: "VSUB.HI.F64",
VSUB_LS_F64: "VSUB.LS.F64",
VSUB_GE_F64: "VSUB.GE.F64",
VSUB_LT_F64: "VSUB.LT.F64",
VSUB_GT_F64: "VSUB.GT.F64",
VSUB_LE_F64: "VSUB.LE.F64",
VSUB_F64: "VSUB.F64",
VSUB_ZZ_F64: "VSUB.ZZ.F64",
WFE_EQ: "WFE.EQ",
WFE_NE: "WFE.NE",
WFE_CS: "WFE.CS",
WFE_CC: "WFE.CC",
WFE_MI: "WFE.MI",
WFE_PL: "WFE.PL",
WFE_VS: "WFE.VS",
WFE_VC: "WFE.VC",
WFE_HI: "WFE.HI",
WFE_LS: "WFE.LS",
WFE_GE: "WFE.GE",
WFE_LT: "WFE.LT",
WFE_GT: "WFE.GT",
WFE_LE: "WFE.LE",
WFE: "WFE",
WFE_ZZ: "WFE.ZZ",
WFI_EQ: "WFI.EQ",
WFI_NE: "WFI.NE",
WFI_CS: "WFI.CS",
WFI_CC: "WFI.CC",
WFI_MI: "WFI.MI",
WFI_PL: "WFI.PL",
WFI_VS: "WFI.VS",
WFI_VC: "WFI.VC",
WFI_HI: "WFI.HI",
WFI_LS: "WFI.LS",
WFI_GE: "WFI.GE",
WFI_LT: "WFI.LT",
WFI_GT: "WFI.GT",
WFI_LE: "WFI.LE",
WFI: "WFI",
WFI_ZZ: "WFI.ZZ",
YIELD_EQ: "YIELD.EQ",
YIELD_NE: "YIELD.NE",
YIELD_CS: "YIELD.CS",
YIELD_CC: "YIELD.CC",
YIELD_MI: "YIELD.MI",
YIELD_PL: "YIELD.PL",
YIELD_VS: "YIELD.VS",
YIELD_VC: "YIELD.VC",
YIELD_HI: "YIELD.HI",
YIELD_LS: "YIELD.LS",
YIELD_GE: "YIELD.GE",
YIELD_LT: "YIELD.LT",
YIELD_GT: "YIELD.GT",
YIELD_LE: "YIELD.LE",
YIELD: "YIELD",
YIELD_ZZ: "YIELD.ZZ",
}
var instFormats = [...]instFormat{
{0x0fe00000, 0x02a00000, 2, ADC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // ADC{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|1|0|1|S|Rn:4|Rd:4|imm12:12
{0x0fe00090, 0x00a00010, 4, ADC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // ADC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|1|0|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4
{0x0fe00010, 0x00a00000, 2, ADC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // ADC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|1|0|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4
{0x0fe00000, 0x02800000, 2, ADD_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // ADD{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|1|0|0|S|Rn:4|Rd:4|imm12:12
{0x0fe00090, 0x00800010, 4, ADD_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // ADD{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|1|0|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4
{0x0fe00010, 0x00800000, 2, ADD_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // ADD{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|1|0|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4
{0x0fef0000, 0x028d0000, 2, ADD_EQ, 0x14011c04, instArgs{arg_R_12, arg_SP, arg_const}}, // ADD{S}<c> <Rd>,SP,#<const> cond:4|0|0|1|0|1|0|0|S|1|1|0|1|Rd:4|imm12:12
{0x0fef0010, 0x008d0000, 2, ADD_EQ, 0x14011c04, instArgs{arg_R_12, arg_SP, arg_R_shift_imm}}, // ADD{S}<c> <Rd>,SP,<Rm>{,<shift>} cond:4|0|0|0|0|1|0|0|S|1|1|0|1|Rd:4|imm5:5|type:2|0|Rm:4
{0x0fe00000, 0x02000000, 2, AND_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // AND{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|0|0|0|S|Rn:4|Rd:4|imm12:12
{0x0fe00090, 0x00000010, 4, AND_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // AND{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|0|0|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4
{0x0fe00010, 0x00000000, 2, AND_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // AND{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|0|0|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4
{0x0fef0070, 0x01a00040, 4, ASR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_imm5_32}}, // ASR{S}<c> <Rd>,<Rm>,#<imm5_32> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|1|0|0|Rm:4
{0x0fef00f0, 0x01a00050, 4, ASR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_R_8}}, // ASR{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|1|0|1|Rn:4
{0x0f000000, 0x0a000000, 4, B_EQ, 0x1c04, instArgs{arg_label24}}, // B<c> <label24> cond:4|1|0|1|0|imm24:24
{0x0fe0007f, 0x07c0001f, 4, BFC_EQ, 0x1c04, instArgs{arg_R_12, arg_imm5, arg_lsb_width}}, // BFC<c> <Rd>,#<lsb>,#<width> cond:4|0|1|1|1|1|1|0|msb:5|Rd:4|lsb:5|0|0|1|1|1|1|1
{0x0fe00070, 0x07c00010, 2, BFI_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_imm5, arg_lsb_width}}, // BFI<c> <Rd>,<Rn>,#<lsb>,#<width> cond:4|0|1|1|1|1|1|0|msb:5|Rd:4|lsb:5|0|0|1|Rn:4
{0x0fe00000, 0x03c00000, 2, BIC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // BIC{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|1|1|1|0|S|Rn:4|Rd:4|imm12:12
{0x0fe00090, 0x01c00010, 4, BIC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // BIC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|1|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4
{0x0fe00010, 0x01c00000, 2, BIC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // BIC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|1|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4
{0x0ff000f0, 0x01200070, 4, BKPT_EQ, 0x1c04, instArgs{arg_imm_12at8_4at0}}, // BKPT<c> #<imm12+4> cond:4|0|0|0|1|0|0|1|0|imm12:12|0|1|1|1|imm4:4
{0x0f000000, 0x0b000000, 4, BL_EQ, 0x1c04, instArgs{arg_label24}}, // BL<c> <label24> cond:4|1|0|1|1|imm24:24
{0xfe000000, 0xfa000000, 4, BLX, 0x0, instArgs{arg_label24H}}, // BLX <label24H> 1|1|1|1|1|0|1|H|imm24:24
{0x0ffffff0, 0x012fff30, 4, BLX_EQ, 0x1c04, instArgs{arg_R_0}}, // BLX<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
{0x0ff000f0, 0x012fff30, 3, BLX_EQ, 0x1c04, instArgs{arg_R_0}}, // BLX<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
{0x0ffffff0, 0x012fff10, 4, BX_EQ, 0x1c04, instArgs{arg_R_0}}, // BX<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
{0x0ff000f0, 0x012fff10, 3, BX_EQ, 0x1c04, instArgs{arg_R_0}}, // BX<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
{0x0ffffff0, 0x012fff20, 4, BXJ_EQ, 0x1c04, instArgs{arg_R_0}}, // BXJ<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|0|Rm:4
{0x0ff000f0, 0x012fff20, 3, BXJ_EQ, 0x1c04, instArgs{arg_R_0}}, // BXJ<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|0|Rm:4
{0xffffffff, 0xf57ff01f, 4, CLREX, 0x0, instArgs{}}, // CLREX 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|1|(1)|(1)|(1)|(1)
{0xfff000f0, 0xf57ff01f, 3, CLREX, 0x0, instArgs{}}, // CLREX 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|1|(1)|(1)|(1)|(1)
{0x0fff0ff0, 0x016f0f10, 4, CLZ_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // CLZ<c> <Rd>,<Rm> cond:4|0|0|0|1|0|1|1|0|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
{0x0ff000f0, 0x016f0f10, 3, CLZ_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // CLZ<c> <Rd>,<Rm> cond:4|0|0|0|1|0|1|1|0|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
{0x0ff0f000, 0x03700000, 4, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // CMN<c> <Rn>,#<const> cond:4|0|0|1|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12
{0x0ff00000, 0x03700000, 3, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // CMN<c> <Rn>,#<const> cond:4|0|0|1|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12
{0x0ff0f090, 0x01700010, 4, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // CMN<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4
{0x0ff00090, 0x01700010, 3, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // CMN<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4
{0x0ff0f010, 0x01700000, 4, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // CMN<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4
{0x0ff00010, 0x01700000, 3, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // CMN<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4
{0x0ff0f000, 0x03500000, 4, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // CMP<c> <Rn>,#<const> cond:4|0|0|1|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12
{0x0ff00000, 0x03500000, 3, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // CMP<c> <Rn>,#<const> cond:4|0|0|1|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12
{0x0ff0f090, 0x01500010, 4, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // CMP<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4
{0x0ff00090, 0x01500010, 3, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // CMP<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4
{0x0ff0f010, 0x01500000, 4, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // CMP<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4
{0x0ff00010, 0x01500000, 3, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // CMP<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4
{0x0ffffff0, 0x0320f0f0, 4, DBG_EQ, 0x1c04, instArgs{arg_option}}, // DBG<c> #<option> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|1|1|1|1|option:4
{0x0fff00f0, 0x0320f0f0, 3, DBG_EQ, 0x1c04, instArgs{arg_option}}, // DBG<c> #<option> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|1|1|1|1|option:4
{0xfffffff0, 0xf57ff050, 4, DMB, 0x0, instArgs{arg_option}}, // DMB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|1|option:4
{0xfff000f0, 0xf57ff050, 3, DMB, 0x0, instArgs{arg_option}}, // DMB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|1|option:4
{0xfffffff0, 0xf57ff040, 4, DSB, 0x0, instArgs{arg_option}}, // DSB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|0|option:4
{0xfff000f0, 0xf57ff040, 3, DSB, 0x0, instArgs{arg_option}}, // DSB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|0|option:4
{0x0fe00000, 0x02200000, 2, EOR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // EOR{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|0|0|1|S|Rn:4|Rd:4|imm12:12
{0x0fe00090, 0x00200010, 4, EOR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // EOR{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|0|0|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4
{0x0fe00010, 0x00200000, 2, EOR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // EOR{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|0|0|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4
{0xfffffff0, 0xf57ff060, 4, ISB, 0x0, instArgs{arg_option}}, // ISB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|1|0|option:4
{0xfff000f0, 0xf57ff060, 3, ISB, 0x0, instArgs{arg_option}}, // ISB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|1|0|option:4
{0x0fd00000, 0x08900000, 2, LDM_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // LDM<c> <Rn>{!},<registers> cond:4|1|0|0|0|1|0|W|1|Rn:4|register_list:16
{0x0fd00000, 0x08100000, 4, LDMDA_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // LDMDA<c> <Rn>{!},<registers> cond:4|1|0|0|0|0|0|W|1|Rn:4|register_list:16
{0x0fd00000, 0x09100000, 4, LDMDB_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // LDMDB<c> <Rn>{!},<registers> cond:4|1|0|0|1|0|0|W|1|Rn:4|register_list:16
{0x0fd00000, 0x09900000, 4, LDMIB_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // LDMIB<c> <Rn>{!},<registers> cond:4|1|0|0|1|1|0|W|1|Rn:4|register_list:16
{0x0f7f0000, 0x051f0000, 4, LDR_EQ, 0x1c04, instArgs{arg_R_12, arg_label_pm_12}}, // LDR<c> <Rt>,<label+/-12> cond:4|0|1|0|(1)|U|0|(0)|1|1|1|1|1|Rt:4|imm12:12
{0x0e5f0000, 0x051f0000, 3, LDR_EQ, 0x1c04, instArgs{arg_R_12, arg_label_pm_12}}, // LDR<c> <Rt>,<label+/-12> cond:4|0|1|0|(1)|U|0|(0)|1|1|1|1|1|Rt:4|imm12:12
{0x0e500010, 0x06100000, 2, LDR_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_W}}, // LDR<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|0|W|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4
{0x0e500000, 0x04100000, 2, LDR_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_W}}, // LDR<c> <Rt>,[<Rn>{,#+/-<imm12>}]{!} cond:4|0|1|0|P|U|0|W|1|Rn:4|Rt:4|imm12:12
{0x0f7f0000, 0x055f0000, 4, LDRB_EQ, 0x1c04, instArgs{arg_R_12, arg_label_pm_12}}, // LDRB<c> <Rt>,<label+/-12> cond:4|0|1|0|(1)|U|1|(0)|1|1|1|1|1|Rt:4|imm12:12
{0x0e5f0000, 0x055f0000, 3, LDRB_EQ, 0x1c04, instArgs{arg_R_12, arg_label_pm_12}}, // LDRB<c> <Rt>,<label+/-12> cond:4|0|1|0|(1)|U|1|(0)|1|1|1|1|1|Rt:4|imm12:12
{0x0e500010, 0x06500000, 2, LDRB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_W}}, // LDRB<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|1|W|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4
{0x0e500000, 0x04500000, 2, LDRB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_W}}, // LDRB<c> <Rt>,[<Rn>{,#+/-<imm12>}]{!} cond:4|0|1|0|P|U|1|W|1|Rn:4|Rt:4|imm12:12
{0x0f700000, 0x04700000, 4, LDRBT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_postindex}}, // LDRBT<c> <Rt>,[<Rn>],#+/-<imm12> cond:4|0|1|0|0|U|1|1|1|Rn:4|Rt:4|imm12:12
{0x0f700010, 0x06700000, 4, LDRBT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_postindex}}, // LDRBT<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>} cond:4|0|1|1|0|U|1|1|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4
{0x0e500ff0, 0x000000d0, 4, LDRD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R_pm_R_W}}, // LDRD<c> <Rt1>,<Rt2>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|0|1|Rm:4
{0x0e5000f0, 0x000000d0, 3, LDRD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R_pm_R_W}}, // LDRD<c> <Rt1>,<Rt2>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|0|1|Rm:4
{0x0e5000f0, 0x004000d0, 2, LDRD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R_pm_imm8_W}}, // LDRD<c> <Rt1>,<Rt2>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|0|Rn:4|Rt:4|imm4H:4|1|1|0|1|imm4L:4
{0x0ff00fff, 0x01900f9f, 4, LDREX_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R}}, // LDREX<c> <Rt>,[<Rn>] cond:4|0|0|0|1|1|0|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1)
{0x0ff000f0, 0x01900f9f, 3, LDREX_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R}}, // LDREX<c> <Rt>,[<Rn>] cond:4|0|0|0|1|1|0|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1)
{0x0ff00fff, 0x01d00f9f, 4, LDREXB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R}}, // LDREXB<c> <Rt>, [<Rn>] cond:4|0|0|0|1|1|1|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1)
{0x0ff000f0, 0x01d00f9f, 3, LDREXB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R}}, // LDREXB<c> <Rt>, [<Rn>] cond:4|0|0|0|1|1|1|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1)
{0x0ff00fff, 0x01b00f9f, 4, LDREXD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R}}, // LDREXD<c> <Rt1>,<Rt2>,[<Rn>] cond:4|0|0|0|1|1|0|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1)
{0x0ff000f0, 0x01b00f9f, 3, LDREXD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R}}, // LDREXD<c> <Rt1>,<Rt2>,[<Rn>] cond:4|0|0|0|1|1|0|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1)
{0x0ff00fff, 0x01f00f9f, 4, LDREXH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R}}, // LDREXH<c> <Rt>, [<Rn>] cond:4|0|0|0|1|1|1|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1)
{0x0ff000f0, 0x01f00f9f, 3, LDREXH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R}}, // LDREXH<c> <Rt>, [<Rn>] cond:4|0|0|0|1|1|1|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1)
{0x0e500ff0, 0x001000b0, 2, LDRH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_W}}, // LDRH<c> <Rt>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|1|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4
{0x0e5000f0, 0x005000b0, 2, LDRH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_W}}, // LDRH<c> <Rt>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|1|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4
{0x0f7000f0, 0x007000b0, 4, LDRHT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_postindex}}, // LDRHT<c> <Rt>, [<Rn>] {,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|1|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4
{0x0f700ff0, 0x003000b0, 4, LDRHT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_postindex}}, // LDRHT<c> <Rt>, [<Rn>], +/-<Rm> cond:4|0|0|0|0|U|0|1|1|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4
{0x0e500ff0, 0x001000d0, 2, LDRSB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_W}}, // LDRSB<c> <Rt>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|1|Rn:4|Rt:4|0|0|0|0|1|1|0|1|Rm:4
{0x0e5000f0, 0x005000d0, 2, LDRSB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_W}}, // LDRSB<c> <Rt>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|1|Rn:4|Rt:4|imm4H:4|1|1|0|1|imm4L:4
{0x0f7000f0, 0x007000d0, 4, LDRSBT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_postindex}}, // LDRSBT<c> <Rt>, [<Rn>] {,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|1|Rn:4|Rt:4|imm4H:4|1|1|0|1|imm4L:4
{0x0f700ff0, 0x003000d0, 4, LDRSBT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_postindex}}, // LDRSBT<c> <Rt>, [<Rn>], +/-<Rm> cond:4|0|0|0|0|U|0|1|1|Rn:4|Rt:4|0|0|0|0|1|1|0|1|Rm:4
{0x0e500ff0, 0x001000f0, 2, LDRSH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_W}}, // LDRSH<c> <Rt>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|1|Rn:4|Rt:4|0|0|0|0|1|1|1|1|Rm:4
{0x0e5000f0, 0x005000f0, 2, LDRSH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_W}}, // LDRSH<c> <Rt>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|1|Rn:4|Rt:4|imm4H:4|1|1|1|1|imm4L:4
{0x0f7000f0, 0x007000f0, 4, LDRSHT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_postindex}}, // LDRSHT<c> <Rt>, [<Rn>] {,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|1|Rn:4|Rt:4|imm4H:4|1|1|1|1|imm4L:4
{0x0f700ff0, 0x003000f0, 4, LDRSHT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_postindex}}, // LDRSHT<c> <Rt>, [<Rn>], +/-<Rm> cond:4|0|0|0|0|U|0|1|1|Rn:4|Rt:4|0|0|0|0|1|1|1|1|Rm:4
{0x0f700000, 0x04300000, 4, LDRT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_postindex}}, // LDRT<c> <Rt>, [<Rn>] {,#+/-<imm12>} cond:4|0|1|0|0|U|0|1|1|Rn:4|Rt:4|imm12:12
{0x0f700010, 0x06300000, 4, LDRT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_postindex}}, // LDRT<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>} cond:4|0|1|1|0|U|0|1|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4
{0x0fef0070, 0x01a00000, 2, LSL_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_imm5_nz}}, // LSL{S}<c> <Rd>,<Rm>,#<imm5_nz> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|0|0|0|Rm:4
{0x0fef00f0, 0x01a00010, 4, LSL_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_R_8}}, // LSL{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|0|0|1|Rn:4
{0x0fef0070, 0x01a00020, 4, LSR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_imm5_32}}, // LSR{S}<c> <Rd>,<Rm>,#<imm5_32> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|0|1|0|Rm:4
{0x0fef00f0, 0x01a00030, 4, LSR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_R_8}}, // LSR{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|0|1|1|Rn:4
{0x0fe000f0, 0x00200090, 4, MLA_EQ, 0x14011c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // MLA{S}<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|0|0|0|0|0|1|S|Rd:4|Ra:4|Rm:4|1|0|0|1|Rn:4
{0x0ff000f0, 0x00600090, 4, MLS_EQ, 0x1c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // MLS<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|0|0|0|0|1|1|0|Rd:4|Ra:4|Rm:4|1|0|0|1|Rn:4
{0x0ff00000, 0x03400000, 4, MOVT_EQ, 0x1c04, instArgs{arg_R_12, arg_imm_4at16_12at0}}, // MOVT<c> <Rd>,#<imm12+4> cond:4|0|0|1|1|0|1|0|0|imm4:4|Rd:4|imm12:12
{0x0ff00000, 0x03000000, 4, MOVW_EQ, 0x1c04, instArgs{arg_R_12, arg_imm_4at16_12at0}}, // MOVW<c> <Rd>,#<imm12+4> cond:4|0|0|1|1|0|0|0|0|imm4:4|Rd:4|imm12:12
{0x0fef0000, 0x03a00000, 2, MOV_EQ, 0x14011c04, instArgs{arg_R_12, arg_const}}, // MOV{S}<c> <Rd>,#<const> cond:4|0|0|1|1|1|0|1|S|0|0|0|0|Rd:4|imm12:12
{0x0fef0ff0, 0x01a00000, 2, MOV_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0}}, // MOV{S}<c> <Rd>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|0|0|0|0|0|0|0|0|Rm:4
{0x0fff0fff, 0x010f0000, 4, MRS_EQ, 0x1c04, instArgs{arg_R_12, arg_APSR}}, // MRS<c> <Rd>,APSR cond:4|0|0|0|1|0|0|0|0|(1)|(1)|(1)|(1)|Rd:4|(0)|(0)|(0)|(0)|0|0|0|0|(0)|(0)|(0)|(0)
{0x0ff000f0, 0x010f0000, 3, MRS_EQ, 0x1c04, instArgs{arg_R_12, arg_APSR}}, // MRS<c> <Rd>,APSR cond:4|0|0|0|1|0|0|0|0|(1)|(1)|(1)|(1)|Rd:4|(0)|(0)|(0)|(0)|0|0|0|0|(0)|(0)|(0)|(0)
{0x0fe0f0f0, 0x00000090, 4, MUL_EQ, 0x14011c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // MUL{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|0|0|0|0|S|Rd:4|(0)|(0)|(0)|(0)|Rm:4|1|0|0|1|Rn:4
{0x0fe000f0, 0x00000090, 3, MUL_EQ, 0x14011c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // MUL{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|0|0|0|0|S|Rd:4|(0)|(0)|(0)|(0)|Rm:4|1|0|0|1|Rn:4
{0x0fef0000, 0x03e00000, 2, MVN_EQ, 0x14011c04, instArgs{arg_R_12, arg_const}}, // MVN{S}<c> <Rd>,#<const> cond:4|0|0|1|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm12:12
{0x0fe00000, 0x03e00000, 1, MVN_EQ, 0x14011c04, instArgs{arg_R_12, arg_const}}, // MVN{S}<c> <Rd>,#<const> cond:4|0|0|1|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm12:12
{0x0fef0090, 0x01e00010, 4, MVN_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_shift_R}}, // MVN{S}<c> <Rd>,<Rm>,<type> <Rs> cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|Rs:4|0|type:2|1|Rm:4
{0x0fe00090, 0x01e00010, 3, MVN_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_shift_R}}, // MVN{S}<c> <Rd>,<Rm>,<type> <Rs> cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|Rs:4|0|type:2|1|Rm:4
{0x0fef0010, 0x01e00000, 2, MVN_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_shift_imm}}, // MVN{S}<c> <Rd>,<Rm>{,<shift>} cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm5:5|type:2|0|Rm:4
{0x0fe00010, 0x01e00000, 1, MVN_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_shift_imm}}, // MVN{S}<c> <Rd>,<Rm>{,<shift>} cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm5:5|type:2|0|Rm:4
{0x0fffffff, 0x0320f000, 4, NOP_EQ, 0x1c04, instArgs{}}, // NOP<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|0
{0x0fff00ff, 0x0320f000, 3, NOP_EQ, 0x1c04, instArgs{}}, // NOP<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|0
{0x0fe00000, 0x03800000, 2, ORR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // ORR{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|1|1|0|0|S|Rn:4|Rd:4|imm12:12
{0x0fe00090, 0x01800010, 4, ORR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // ORR{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|1|0|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4
{0x0fe00010, 0x01800000, 2, ORR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // ORR{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|1|0|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4
{0x0ff00030, 0x06800010, 4, PKHBT_EQ, 0x6011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // PKH<BT,TB><c> <Rd>,<Rn>,<Rm>{,LSL #<imm5>} cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|imm5:5|tb|0|1|Rm:4
{0xff7ff000, 0xf55ff000, 4, PLD, 0x0, instArgs{arg_label_pm_12}}, // PLD <label+/-12> 1|1|1|1|0|1|0|1|U|(1)|0|1|1|1|1|1|(1)|(1)|(1)|(1)|imm12:12
{0xff3f0000, 0xf55ff000, 3, PLD, 0x0, instArgs{arg_label_pm_12}}, // PLD <label+/-12> 1|1|1|1|0|1|0|1|U|(1)|0|1|1|1|1|1|(1)|(1)|(1)|(1)|imm12:12
{0xff30f000, 0xf510f000, 2, PLD_W, 0x1601, instArgs{arg_mem_R_pm_imm12_offset}}, // PLD{W} [<Rn>,#+/-<imm12>] 1|1|1|1|0|1|0|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12
{0xff300000, 0xf510f000, 1, PLD_W, 0x1601, instArgs{arg_mem_R_pm_imm12_offset}}, // PLD{W} [<Rn>,#+/-<imm12>] 1|1|1|1|0|1|0|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12
{0xff30f010, 0xf710f000, 4, PLD_W, 0x1601, instArgs{arg_mem_R_pm_R_shift_imm_offset}}, // PLD{W} [<Rn>,+/-<Rm>{, <shift>}] 1|1|1|1|0|1|1|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4
{0xff300010, 0xf710f000, 3, PLD_W, 0x1601, instArgs{arg_mem_R_pm_R_shift_imm_offset}}, // PLD{W} [<Rn>,+/-<Rm>{, <shift>}] 1|1|1|1|0|1|1|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4
{0xff70f000, 0xf450f000, 4, PLI, 0x0, instArgs{arg_mem_R_pm_imm12_offset}}, // PLI [<Rn>,#+/-<imm12>] 1|1|1|1|0|1|0|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12
{0xff700000, 0xf450f000, 3, PLI, 0x0, instArgs{arg_mem_R_pm_imm12_offset}}, // PLI [<Rn>,#+/-<imm12>] 1|1|1|1|0|1|0|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12
{0xff70f010, 0xf650f000, 4, PLI, 0x0, instArgs{arg_mem_R_pm_R_shift_imm_offset}}, // PLI [<Rn>,+/-<Rm>{, <shift>}] 1|1|1|1|0|1|1|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4
{0xff700010, 0xf650f000, 3, PLI, 0x0, instArgs{arg_mem_R_pm_R_shift_imm_offset}}, // PLI [<Rn>,+/-<Rm>{, <shift>}] 1|1|1|1|0|1|1|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4
{0x0fff0000, 0x08bd0000, 4, POP_EQ, 0x1c04, instArgs{arg_registers2}}, // POP<c> <registers2> cond:4|1|0|0|0|1|0|1|1|1|1|0|1|register_list:16
{0x0fff0fff, 0x049d0004, 4, POP_EQ, 0x1c04, instArgs{arg_registers1}}, // POP<c> <registers1> cond:4|0|1|0|0|1|0|0|1|1|1|0|1|Rt:4|0|0|0|0|0|0|0|0|0|1|0|0
{0x0fff0000, 0x092d0000, 4, PUSH_EQ, 0x1c04, instArgs{arg_registers2}}, // PUSH<c> <registers2> cond:4|1|0|0|1|0|0|1|0|1|1|0|1|register_list:16
{0x0fff0fff, 0x052d0004, 4, PUSH_EQ, 0x1c04, instArgs{arg_registers1}}, // PUSH<c> <registers1> cond:4|0|1|0|1|0|0|1|0|1|1|0|1|Rt:4|0|0|0|0|0|0|0|0|0|1|0|0
{0x0ff00ff0, 0x06200f10, 4, QADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
{0x0ff000f0, 0x06200f10, 3, QADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
{0x0ff00ff0, 0x06200f90, 4, QADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
{0x0ff000f0, 0x06200f90, 3, QADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
{0x0ff00ff0, 0x01000050, 4, QADD_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_R_16}}, // QADD<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|0|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4
{0x0ff000f0, 0x01000050, 3, QADD_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_R_16}}, // QADD<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|0|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4
{0x0ff00ff0, 0x06200f30, 4, QASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
{0x0ff000f0, 0x06200f30, 3, QASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
{0x0ff00ff0, 0x01400050, 4, QDADD_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_R_16}}, // QDADD<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|1|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4
{0x0ff000f0, 0x01400050, 3, QDADD_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_R_16}}, // QDADD<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|1|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4
{0x0ff00ff0, 0x01600050, 4, QDSUB_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_R_16}}, // QDSUB<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|1|1|0|Rn:4|Rd:4|0|0|0|0|0|1|0|1|Rm:4
{0x0ff00ff0, 0x06200f50, 4, QSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
{0x0ff000f0, 0x06200f50, 3, QSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
{0x0ff00ff0, 0x06200f70, 4, QSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
{0x0ff000f0, 0x06200f70, 3, QSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
{0x0ff00ff0, 0x06200ff0, 4, QSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
{0x0ff000f0, 0x06200ff0, 3, QSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
{0x0ff00ff0, 0x01200050, 4, QSUB_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_R_16}}, // QSUB<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|0|1|0|Rn:4|Rd:4|0|0|0|0|0|1|0|1|Rm:4
{0x0fff0ff0, 0x06ff0f30, 4, RBIT_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // RBIT<c> <Rd>,<Rm> cond:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
{0x0ff000f0, 0x06ff0f30, 3, RBIT_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // RBIT<c> <Rd>,<Rm> cond:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
{0x0fff0ff0, 0x06bf0fb0, 4, REV16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // REV16<c> <Rd>,<Rm> cond:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4
{0x0ff000f0, 0x06bf0fb0, 3, REV16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // REV16<c> <Rd>,<Rm> cond:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4
{0x0fff0ff0, 0x06bf0f30, 4, REV_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // REV<c> <Rd>,<Rm> cond:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
{0x0ff000f0, 0x06bf0f30, 3, REV_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // REV<c> <Rd>,<Rm> cond:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
{0x0fff0ff0, 0x06ff0fb0, 4, REVSH_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // REVSH<c> <Rd>,<Rm> cond:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4
{0x0ff000f0, 0x06ff0fb0, 3, REVSH_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // REVSH<c> <Rd>,<Rm> cond:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4
{0x0fef0070, 0x01a00060, 2, ROR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_imm5}}, // ROR{S}<c> <Rd>,<Rm>,#<imm5> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|1|1|0|Rm:4
{0x0fef00f0, 0x01a00070, 4, ROR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_R_8}}, // ROR{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|1|1|1|Rn:4
{0x0fef0ff0, 0x01a00060, 4, RRX_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0}}, // RRX{S}<c> <Rd>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|0|0|0|0|0|1|1|0|Rm:4
{0x0fe00000, 0x02600000, 2, RSB_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // RSB{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|0|1|1|S|Rn:4|Rd:4|imm12:12
{0x0fe00090, 0x00600010, 4, RSB_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // RSB{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|0|1|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4
{0x0fe00010, 0x00600000, 2, RSB_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // RSB{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|0|1|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4
{0x0fe00000, 0x02e00000, 2, RSC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // RSC{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|1|1|1|S|Rn:4|Rd:4|imm12:12
{0x0fe00090, 0x00e00010, 4, RSC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // RSC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|1|1|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4
{0x0fe00010, 0x00e00000, 2, RSC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // RSC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|1|1|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4
{0x0ff00ff0, 0x06100f10, 4, SADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
{0x0ff000f0, 0x06100f10, 3, SADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
{0x0ff00ff0, 0x06100f90, 4, SADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
{0x0ff000f0, 0x06100f90, 3, SADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
{0x0ff00ff0, 0x06100f30, 4, SASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
{0x0ff000f0, 0x06100f30, 3, SASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
{0x0fe00000, 0x02c00000, 2, SBC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // SBC{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|1|1|0|S|Rn:4|Rd:4|imm12:12
{0x0fe00090, 0x00c00010, 4, SBC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // SBC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|1|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4
{0x0fe00010, 0x00c00000, 2, SBC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // SBC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|1|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4
{0x0fe00070, 0x07a00050, 4, SBFX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_imm5, arg_widthm1}}, // SBFX<c> <Rd>,<Rn>,#<lsb>,#<widthm1> cond:4|0|1|1|1|1|0|1|widthm1:5|Rd:4|lsb:5|1|0|1|Rn:4
{0x0ff00ff0, 0x06800fb0, 4, SEL_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SEL<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4
{0x0ff000f0, 0x06800fb0, 3, SEL_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SEL<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4
{0xfffffdff, 0xf1010000, 4, SETEND, 0x0, instArgs{arg_endian}}, // SETEND <endian_specifier> 1|1|1|1|0|0|0|1|0|0|0|0|0|0|0|1|0|0|0|0|0|0|E|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0)
{0xfffffc00, 0xf1010000, 3, SETEND, 0x0, instArgs{arg_endian}}, // SETEND <endian_specifier> 1|1|1|1|0|0|0|1|0|0|0|0|0|0|0|1|0|0|0|0|0|0|E|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0)
{0x0fffffff, 0x0320f004, 4, SEV_EQ, 0x1c04, instArgs{}}, // SEV<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|1|0|0
{0x0fff00ff, 0x0320f004, 3, SEV_EQ, 0x1c04, instArgs{}}, // SEV<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|1|0|0
{0x0ff00ff0, 0x06300f10, 4, SHADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
{0x0ff000f0, 0x06300f10, 3, SHADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
{0x0ff00ff0, 0x06300f90, 4, SHADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
{0x0ff000f0, 0x06300f90, 3, SHADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
{0x0ff00ff0, 0x06300f30, 4, SHASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
{0x0ff000f0, 0x06300f30, 3, SHASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
{0x0ff00ff0, 0x06300f50, 4, SHSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
{0x0ff000f0, 0x06300f50, 3, SHSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
{0x0ff00ff0, 0x06300f70, 4, SHSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
{0x0ff000f0, 0x06300f70, 3, SHSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
{0x0ff00ff0, 0x06300ff0, 4, SHSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
{0x0ff000f0, 0x06300ff0, 3, SHSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
{0x0ff00090, 0x01000080, 4, SMLABB_EQ, 0x50106011c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // SMLA<x><y><c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|0|0|1|0|0|0|0|Rd:4|Ra:4|Rm:4|1|M|N|0|Rn:4
{0x0ff000d0, 0x07000010, 2, SMLAD_EQ, 0x5011c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // SMLAD{X}<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|1|1|1|0|0|0|0|Rd:4|Ra:4|Rm:4|0|0|M|1|Rn:4
{0x0ff00090, 0x01400080, 4, SMLALBB_EQ, 0x50106011c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // SMLAL<x><y><c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|1|0|1|0|0|RdHi:4|RdLo:4|Rm:4|1|M|N|0|Rn:4
{0x0ff000d0, 0x07400010, 4, SMLALD_EQ, 0x5011c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // SMLALD{X}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|1|1|1|0|1|0|0|RdHi:4|RdLo:4|Rm:4|0|0|M|1|Rn:4
{0x0fe000f0, 0x00e00090, 4, SMLAL_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // SMLAL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|1|1|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4
{0x0ff000b0, 0x01200080, 4, SMLAWB_EQ, 0x6011c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // SMLAW<y><c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|0|0|1|0|0|1|0|Rd:4|Ra:4|Rm:4|1|M|0|0|Rn:4
{0x0ff000d0, 0x07000050, 2, SMLSD_EQ, 0x5011c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // SMLSD{X}<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|1|1|1|0|0|0|0|Rd:4|Ra:4|Rm:4|0|1|M|1|Rn:4
{0x0ff000d0, 0x07400050, 4, SMLSLD_EQ, 0x5011c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // SMLSLD{X}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|1|1|1|0|1|0|0|RdHi:4|RdLo:4|Rm:4|0|1|M|1|Rn:4
{0x0ff000d0, 0x07500010, 2, SMMLA_EQ, 0x5011c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // SMMLA{R}<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|1|1|1|0|1|0|1|Rd:4|Ra:4|Rm:4|0|0|R|1|Rn:4
{0x0ff000d0, 0x075000d0, 4, SMMLS_EQ, 0x5011c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // SMMLS{R}<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|1|1|1|0|1|0|1|Rd:4|Ra:4|Rm:4|1|1|R|1|Rn:4
{0x0ff0f0d0, 0x0750f010, 4, SMMUL_EQ, 0x5011c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // SMMUL{R}<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|1|0|1|0|1|Rd:4|1|1|1|1|Rm:4|0|0|R|1|Rn:4
{0x0ff0f0d0, 0x0700f010, 4, SMUAD_EQ, 0x5011c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // SMUAD{X}<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|1|0|0|0|0|Rd:4|1|1|1|1|Rm:4|0|0|M|1|Rn:4
{0x0ff0f090, 0x01600080, 4, SMULBB_EQ, 0x50106011c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // SMUL<x><y><c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|0|1|1|0|Rd:4|0|0|0|0|Rm:4|1|M|N|0|Rn:4
{0x0fe000f0, 0x00c00090, 4, SMULL_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // SMULL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|1|0|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4
{0x0ff0f0b0, 0x012000a0, 4, SMULWB_EQ, 0x6011c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // SMULW<y><c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|0|0|1|0|Rd:4|0|0|0|0|Rm:4|1|M|1|0|Rn:4
{0x0ff0f0d0, 0x0700f050, 4, SMUSD_EQ, 0x5011c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // SMUSD{X}<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|1|0|0|0|0|Rd:4|1|1|1|1|Rm:4|0|1|M|1|Rn:4
{0x0ff00ff0, 0x06a00f30, 4, SSAT16_EQ, 0x1c04, instArgs{arg_R_12, arg_satimm4m1, arg_R_0}}, // SSAT16<c> <Rd>,#<sat_imm4m1>,<Rn> cond:4|0|1|1|0|1|0|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4
{0x0ff000f0, 0x06a00f30, 3, SSAT16_EQ, 0x1c04, instArgs{arg_R_12, arg_satimm4m1, arg_R_0}}, // SSAT16<c> <Rd>,#<sat_imm4m1>,<Rn> cond:4|0|1|1|0|1|0|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4
{0x0fe00030, 0x06a00010, 4, SSAT_EQ, 0x1c04, instArgs{arg_R_12, arg_satimm5m1, arg_R_shift_imm}}, // SSAT<c> <Rd>,#<sat_imm5m1>,<Rn>{,<shift>} cond:4|0|1|1|0|1|0|1|sat_imm:5|Rd:4|imm5:5|sh|0|1|Rn:4
{0x0ff00ff0, 0x06100f50, 4, SSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
{0x0ff000f0, 0x06100f50, 3, SSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
{0x0ff00ff0, 0x06100f70, 4, SSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
{0x0ff000f0, 0x06100f70, 3, SSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
{0x0ff00ff0, 0x06100ff0, 4, SSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
{0x0ff000f0, 0x06100ff0, 3, SSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
{0x0fd00000, 0x08800000, 4, STM_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // STM<c> <Rn>{!},<registers> cond:4|1|0|0|0|1|0|W|0|Rn:4|register_list:16
{0x0fd00000, 0x08000000, 4, STMDA_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // STMDA<c> <Rn>{!},<registers> cond:4|1|0|0|0|0|0|W|0|Rn:4|register_list:16
{0x0fd00000, 0x09000000, 2, STMDB_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // STMDB<c> <Rn>{!},<registers> cond:4|1|0|0|1|0|0|W|0|Rn:4|register_list:16
{0x0fd00000, 0x09800000, 4, STMIB_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // STMIB<c> <Rn>{!},<registers> cond:4|1|0|0|1|1|0|W|0|Rn:4|register_list:16
{0x0e500018, 0x06000000, 2, STR_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_W}}, // STR<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|0|W|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4
{0x0e500000, 0x04000000, 2, STR_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_W}}, // STR<c> <Rt>,[<Rn>{,#+/-<imm12>}]{!} cond:4|0|1|0|P|U|0|W|0|Rn:4|Rt:4|imm12:12
{0x0e500010, 0x06400000, 2, STRB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_W}}, // STRB<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|1|W|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4
{0x0e500000, 0x04400000, 2, STRB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_W}}, // STRB<c> <Rt>,[<Rn>{,#+/-<imm12>}]{!} cond:4|0|1|0|P|U|1|W|0|Rn:4|Rt:4|imm12:12
{0x0f700000, 0x04600000, 4, STRBT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_postindex}}, // STRBT<c> <Rt>,[<Rn>],#+/-<imm12> cond:4|0|1|0|0|U|1|1|0|Rn:4|Rt:4|imm12:12
{0x0f700010, 0x06600000, 4, STRBT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_postindex}}, // STRBT<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>} cond:4|0|1|1|0|U|1|1|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4
{0x0e500ff0, 0x000000f0, 4, STRD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R_pm_R_W}}, // STRD<c> <Rt1>,<Rt2>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|1|1|Rm:4
{0x0e5000f0, 0x000000f0, 3, STRD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R_pm_R_W}}, // STRD<c> <Rt1>,<Rt2>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|1|1|Rm:4
{0x0e5000f0, 0x004000f0, 4, STRD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R_pm_imm8_W}}, // STRD<c> <Rt1>,<Rt2>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|0|Rn:4|Rt:4|imm4H:4|1|1|1|1|imm4L:4
{0x0ff00ff0, 0x01800f90, 4, STREX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_mem_R}}, // STREX<c> <Rd>,<Rt>,[<Rn>] cond:4|0|0|0|1|1|0|0|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4
{0x0ff00ff0, 0x01c00f90, 4, STREXB_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_mem_R}}, // STREXB<c> <Rd>,<Rt>,[<Rn>] cond:4|0|0|0|1|1|1|0|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4
{0x0ff00ff0, 0x01a00f90, 4, STREXD_EQ, 0x1c04, instArgs{arg_R_12, arg_R1_0, arg_R2_0, arg_mem_R}}, // STREXD<c> <Rd>,<Rt1>,<Rt2>,[<Rn>] cond:4|0|0|0|1|1|0|1|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4
{0x0ff00ff0, 0x01e00f90, 4, STREXH_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_mem_R}}, // STREXH<c> <Rd>,<Rt>,[<Rn>] cond:4|0|0|0|1|1|1|1|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4
{0x0e500ff0, 0x000000b0, 2, STRH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_W}}, // STRH<c> <Rt>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4
{0x0e5000f0, 0x004000b0, 2, STRH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_W}}, // STRH<c> <Rt>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|0|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4
{0x0f7000f0, 0x006000b0, 4, STRHT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_postindex}}, // STRHT<c> <Rt>, [<Rn>] {,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|0|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4
{0x0f700ff0, 0x002000b0, 4, STRHT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_postindex}}, // STRHT<c> <Rt>, [<Rn>], +/-<Rm> cond:4|0|0|0|0|U|0|1|0|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4
{0x0f700000, 0x04200000, 4, STRT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_postindex}}, // STRT<c> <Rt>, [<Rn>] {,#+/-<imm12>} cond:4|0|1|0|0|U|0|1|0|Rn:4|Rt:4|imm12:12
{0x0f700010, 0x06200000, 4, STRT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_postindex}}, // STRT<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>} cond:4|0|1|1|0|U|0|1|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4
{0x0fe00000, 0x02400000, 2, SUB_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // SUB{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|0|1|0|S|Rn:4|Rd:4|imm12:12
{0x0fe00090, 0x00400010, 4, SUB_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // SUB{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|0|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4
{0x0fe00010, 0x00400000, 2, SUB_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // SUB{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|0|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4
{0x0fef0000, 0x024d0000, 2, SUB_EQ, 0x14011c04, instArgs{arg_R_12, arg_SP, arg_const}}, // SUB{S}<c> <Rd>,SP,#<const> cond:4|0|0|1|0|0|1|0|S|1|1|0|1|Rd:4|imm12:12
{0x0fef0010, 0x004d0000, 2, SUB_EQ, 0x14011c04, instArgs{arg_R_12, arg_SP, arg_R_shift_imm}}, // SUB{S}<c> <Rd>,SP,<Rm>{,<shift>} cond:4|0|0|0|0|0|1|0|S|1|1|0|1|Rd:4|imm5:5|type:2|0|Rm:4
{0x0f000000, 0x0f000000, 4, SVC_EQ, 0x1c04, instArgs{arg_imm24}}, // SVC<c> #<imm24> cond:4|1|1|1|1|imm24:24
{0x0fb00ff0, 0x01000090, 4, SWP_EQ, 0x16011c04, instArgs{arg_R_12, arg_R_0, arg_mem_R}}, // SWP{B}<c> <Rt>,<Rm>,[<Rn>] cond:4|0|0|0|1|0|B|0|0|Rn:4|Rt:4|0|0|0|0|1|0|0|1|Rm:4
{0x0ff003f0, 0x06800070, 2, SXTAB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_rotate}}, // SXTAB16<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
{0x0ff003f0, 0x06a00070, 2, SXTAB_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_rotate}}, // SXTAB<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|1|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
{0x0ff003f0, 0x06b00070, 2, SXTAH_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_rotate}}, // SXTAH<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|1|1|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
{0x0fff03f0, 0x068f0070, 4, SXTB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_rotate}}, // SXTB16<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|0|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
{0x0fff03f0, 0x06af0070, 4, SXTB_EQ, 0x1c04, instArgs{arg_R_12, arg_R_rotate}}, // SXTB<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|1|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
{0x0fff03f0, 0x06bf0070, 4, SXTH_EQ, 0x1c04, instArgs{arg_R_12, arg_R_rotate}}, // SXTH<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|1|1|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
{0x0ff0f000, 0x03300000, 4, TEQ_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // TEQ<c> <Rn>,#<const> cond:4|0|0|1|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12
{0x0ff00000, 0x03300000, 3, TEQ_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // TEQ<c> <Rn>,#<const> cond:4|0|0|1|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12
{0x0ff0f090, 0x01300010, 4, TEQ_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // TEQ<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4
{0x0ff00090, 0x01300010, 3, TEQ_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // TEQ<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4
{0x0ff0f010, 0x01300000, 4, TEQ_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // TEQ<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4
{0x0ff00010, 0x01300000, 3, TEQ_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // TEQ<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4
{0x0ff0f000, 0x03100000, 4, TST_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // TST<c> <Rn>,#<const> cond:4|0|0|1|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12
{0x0ff00000, 0x03100000, 3, TST_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // TST<c> <Rn>,#<const> cond:4|0|0|1|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12
{0x0ff0f090, 0x01100010, 4, TST_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // TST<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4
{0x0ff00090, 0x01100010, 3, TST_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // TST<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4
{0x0ff0f010, 0x01100000, 4, TST_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // TST<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4
{0x0ff00010, 0x01100000, 3, TST_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // TST<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4
{0x0ff00ff0, 0x06500f10, 4, UADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
{0x0ff000f0, 0x06500f10, 3, UADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
{0x0ff00ff0, 0x06500f90, 4, UADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
{0x0ff000f0, 0x06500f90, 3, UADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
{0x0ff00ff0, 0x06500f30, 4, UASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
{0x0ff000f0, 0x06500f30, 3, UASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
{0x0fe00070, 0x07e00050, 4, UBFX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_imm5, arg_widthm1}}, // UBFX<c> <Rd>,<Rn>,#<lsb>,#<widthm1> cond:4|0|1|1|1|1|1|1|widthm1:5|Rd:4|lsb:5|1|0|1|Rn:4
{0x0ff00ff0, 0x06700f10, 4, UHADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
{0x0ff000f0, 0x06700f10, 3, UHADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
{0x0ff00ff0, 0x06700f90, 4, UHADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
{0x0ff000f0, 0x06700f90, 3, UHADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
{0x0ff00ff0, 0x06700f30, 4, UHASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
{0x0ff000f0, 0x06700f30, 3, UHASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
{0x0ff00ff0, 0x06700f50, 4, UHSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
{0x0ff000f0, 0x06700f50, 3, UHSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
{0x0ff00ff0, 0x06700f70, 4, UHSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
{0x0ff000f0, 0x06700f70, 3, UHSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
{0x0ff00ff0, 0x06700ff0, 4, UHSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
{0x0ff000f0, 0x06700ff0, 3, UHSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
{0x0ff000f0, 0x00400090, 4, UMAAL_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // UMAAL<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|0|1|0|0|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4
{0x0fe000f0, 0x00a00090, 4, UMLAL_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // UMLAL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|0|1|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4
{0x0fe000f0, 0x00800090, 4, UMULL_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // UMULL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|0|0|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4
{0x0ff00ff0, 0x06600f10, 4, UQADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
{0x0ff000f0, 0x06600f10, 3, UQADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
{0x0ff00ff0, 0x06600f90, 4, UQADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
{0x0ff000f0, 0x06600f90, 3, UQADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
{0x0ff00ff0, 0x06600f30, 4, UQASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
{0x0ff000f0, 0x06600f30, 3, UQASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
{0x0ff00ff0, 0x06600f50, 4, UQSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
{0x0ff000f0, 0x06600f50, 3, UQSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
{0x0ff00ff0, 0x06600f70, 4, UQSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
{0x0ff000f0, 0x06600f70, 3, UQSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
{0x0ff00ff0, 0x06600ff0, 4, UQSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
{0x0ff000f0, 0x06600ff0, 3, UQSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
{0x0ff0f0f0, 0x0780f010, 4, USAD8_EQ, 0x1c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // USAD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|1|1|0|0|0|Rd:4|1|1|1|1|Rm:4|0|0|0|1|Rn:4
{0x0ff000f0, 0x07800010, 2, USADA8_EQ, 0x1c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // USADA8<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|1|1|1|1|0|0|0|Rd:4|Ra:4|Rm:4|0|0|0|1|Rn:4
{0x0ff00ff0, 0x06e00f30, 4, USAT16_EQ, 0x1c04, instArgs{arg_R_12, arg_satimm4, arg_R_0}}, // USAT16<c> <Rd>,#<sat_imm4>,<Rn> cond:4|0|1|1|0|1|1|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4
{0x0ff000f0, 0x06e00f30, 3, USAT16_EQ, 0x1c04, instArgs{arg_R_12, arg_satimm4, arg_R_0}}, // USAT16<c> <Rd>,#<sat_imm4>,<Rn> cond:4|0|1|1|0|1|1|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4
{0x0fe00030, 0x06e00010, 4, USAT_EQ, 0x1c04, instArgs{arg_R_12, arg_satimm5, arg_R_shift_imm}}, // USAT<c> <Rd>,#<sat_imm5>,<Rn>{,<shift>} cond:4|0|1|1|0|1|1|1|sat_imm:5|Rd:4|imm5:5|sh|0|1|Rn:4
{0x0ff00ff0, 0x06500f50, 4, USAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // USAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
{0x0ff000f0, 0x06500f50, 3, USAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // USAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
{0x0ff00ff0, 0x06500f70, 4, USUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // USUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
{0x0ff000f0, 0x06500f70, 3, USUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // USUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
{0x0ff00ff0, 0x06500ff0, 4, USUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // USUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
{0x0ff000f0, 0x06500ff0, 3, USUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // USUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
{0x0ff003f0, 0x06c00070, 2, UXTAB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_rotate}}, // UXTAB16<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|0|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
{0x0ff003f0, 0x06e00070, 2, UXTAB_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_rotate}}, // UXTAB<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|1|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
{0x0ff003f0, 0x06f00070, 2, UXTAH_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_rotate}}, // UXTAH<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|1|1|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
{0x0fff03f0, 0x06cf0070, 4, UXTB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_rotate}}, // UXTB16<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|0|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
{0x0fff03f0, 0x06ef0070, 4, UXTB_EQ, 0x1c04, instArgs{arg_R_12, arg_R_rotate}}, // UXTB<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|1|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
{0x0fff03f0, 0x06ff0070, 4, UXTH_EQ, 0x1c04, instArgs{arg_R_12, arg_R_rotate}}, // UXTH<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|1|1|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
{0x0fb00e10, 0x0e000a00, 4, VMLA_EQ_F32, 0x60108011c04, instArgs{arg_Sd_Dd, arg_Sn_Dn, arg_Sm_Dm}}, // V<MLA,MLS><c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|0|0|Vn:4|Vd:4|1|0|1|sz|N|op|M|0|Vm:4
{0x0fbf0ed0, 0x0eb00ac0, 4, VABS_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sm_Dm}}, // VABS<c>.F<32,64> <Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|0|0|0|Vd:4|1|0|1|sz|1|1|M|0|Vm:4
{0x0fb00e50, 0x0e300a00, 4, VADD_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sn_Dn, arg_Sm_Dm}}, // VADD<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|1|1|Vn:4|Vd:4|1|0|1|sz|N|0|M|0|Vm:4
{0x0fbf0e7f, 0x0eb50a40, 4, VCMP_EQ_F32, 0x70108011c04, instArgs{arg_Sd_Dd, arg_fp_0}}, // VCMP{E}<c>.F<32,64> <Sd,Dd>, #0.0 cond:4|1|1|1|0|1|D|1|1|0|1|0|1|Vd:4|1|0|1|sz|E|1|0|0|(0)|(0)|(0)|(0)
{0x0fbf0e70, 0x0eb50a40, 3, VCMP_EQ_F32, 0x70108011c04, instArgs{arg_Sd_Dd, arg_fp_0}}, // VCMP{E}<c>.F<32,64> <Sd,Dd>, #0.0 cond:4|1|1|1|0|1|D|1|1|0|1|0|1|Vd:4|1|0|1|sz|E|1|0|0|(0)|(0)|(0)|(0)
{0x0fbf0e50, 0x0eb40a40, 4, VCMP_EQ_F32, 0x70108011c04, instArgs{arg_Sd_Dd, arg_Sm_Dm}}, // VCMP{E}<c>.F<32,64> <Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|1|0|0|Vd:4|1|0|1|sz|E|1|M|0|Vm:4
{0x0fbe0e50, 0x0eba0a40, 4, VCVT_EQ_F32_FXS16, 0x801100107011c04, instArgs{arg_Sd_Dd, arg_Sd_Dd, arg_fbits}}, // VCVT<c>.F<32,64>.FX<S,U><16,32> <Sd,Dd>, <Sd,Dd>, #<fbits> cond:4|1|1|1|0|1|D|1|1|1|0|1|U|Vd:4|1|0|1|sz|sx|1|i|0|imm4:4
{0x0fbe0e50, 0x0ebe0a40, 4, VCVT_EQ_FXS16_F32, 0x1001070108011c04, instArgs{arg_Sd_Dd, arg_Sd_Dd, arg_fbits}}, // VCVT<c>.FX<S,U><16,32>.F<32,64> <Sd,Dd>, <Sd,Dd>, #<fbits> cond:4|1|1|1|0|1|D|1|1|1|1|1|U|Vd:4|1|0|1|sz|sx|1|i|0|imm4:4
{0x0fbf0ed0, 0x0eb70ac0, 4, VCVT_EQ_F64_F32, 0x8011c04, instArgs{arg_Dd_Sd, arg_Sm_Dm}}, // VCVT<c>.<F64.F32,F32.F64> <Dd,Sd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|1|1|1|Vd:4|1|0|1|sz|1|1|M|0|Vm:4
{0x0fbe0f50, 0x0eb20a40, 4, VCVTB_EQ_F32_F16, 0x70110011c04, instArgs{arg_Sd, arg_Sm}}, // VCVT<B,T><c>.<F32.F16,F16.F32> <Sd>, <Sm> cond:4|1|1|1|0|1|D|1|1|0|0|1|op|Vd:4|1|0|1|0|T|1|M|0|Vm:4
{0x0fbf0e50, 0x0eb80a40, 4, VCVT_EQ_F32_U32, 0x80107011c04, instArgs{arg_Sd_Dd, arg_Sm}}, // VCVT<c>.F<32,64>.<U,S>32 <Sd,Dd>, <Sm> cond:4|1|1|1|0|1|D|1|1|1|0|0|0|Vd:4|1|0|1|sz|op|1|M|0|Vm:4
{0x0fbe0e50, 0x0ebc0a40, 4, VCVTR_EQ_U32_F32, 0x701100108011c04, instArgs{arg_Sd, arg_Sm_Dm}}, // VCVT<R,><c>.<U,S>32.F<32,64> <Sd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|1|1|0|signed|Vd:4|1|0|1|sz|op|1|M|0|Vm:4
{0x0fb00e50, 0x0e800a00, 4, VDIV_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sn_Dn, arg_Sm_Dm}}, // VDIV<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|1|D|0|0|Vn:4|Vd:4|1|0|1|sz|N|0|M|0|Vm:4
{0x0f300e00, 0x0d100a00, 4, VLDR_EQ, 0x1c04, instArgs{arg_Sd_Dd, arg_mem_R_pm_imm8at0_offset}}, // VLDR<c> <Sd,Dd>, [<Rn>{,#+/-<imm8>}] cond:4|1|1|0|1|U|D|0|1|Rn:4|Vd:4|1|0|1|sz|imm8:8
{0x0ff00f7f, 0x0e000a10, 4, VMOV_EQ, 0x1c04, instArgs{arg_Sn, arg_R_12}}, // VMOV<c> <Sn>, <Rt> cond:4|1|1|1|0|0|0|0|0|Vn:4|Rt:4|1|0|1|0|N|0|0|1|0|0|0|0
{0x0ff00f7f, 0x0e100a10, 4, VMOV_EQ, 0x1c04, instArgs{arg_R_12, arg_Sn}}, // VMOV<c> <Rt>, <Sn> cond:4|1|1|1|0|0|0|0|1|Vn:4|Rt:4|1|0|1|0|N|0|0|1|0|0|0|0
{0x0fd00f7f, 0x0e100b10, 4, VMOV_EQ_32, 0x1c04, instArgs{arg_R_12, arg_Dn_half}}, // VMOV<c>.32 <Rt>, <Dn[x]> cond:4|1|1|1|0|0|0|opc1|1|Vn:4|Rt:4|1|0|1|1|N|0|0|1|0|0|0|0
{0x0fd00f7f, 0x0e000b10, 4, VMOV_EQ_32, 0x1c04, instArgs{arg_Dn_half, arg_R_12}}, // VMOV<c>.32 <Dd[x]>, <Rt> cond:4|1|1|1|0|0|0|opc1|0|Vd:4|Rt:4|1|0|1|1|D|0|0|1|0|0|0|0
{0x0fb00ef0, 0x0eb00a00, 4, VMOV_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_imm_vfp}}, // VMOV<c>.F<32,64> <Sd,Dd>, #<imm_vfp> cond:4|1|1|1|0|1|D|1|1|imm4H:4|Vd:4|1|0|1|sz|0|0|0|0|imm4L:4
{0x0fbf0ed0, 0x0eb00a40, 4, VMOV_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sm_Dm}}, // VMOV<c>.F<32,64> <Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|0|0|0|Vd:4|1|0|1|sz|0|1|M|0|Vm:4
{0x0fff0fff, 0x0ef10a10, 4, VMRS_EQ, 0x1c04, instArgs{arg_R_12_nzcv, arg_FPSCR}}, // VMRS<c> <Rt_nzcv>, FPSCR cond:4|1|1|1|0|1|1|1|1|0|0|0|1|Rt:4|1|0|1|0|0|0|0|1|0|0|0|0
{0x0fff0fff, 0x0ee10a10, 4, VMSR_EQ, 0x1c04, instArgs{arg_FPSCR, arg_R_12}}, // VMSR<c> FPSCR, <Rt> cond:4|1|1|1|0|1|1|1|0|0|0|0|1|Rt:4|1|0|1|0|0|0|0|1|0|0|0|0
{0x0fb00e50, 0x0e200a00, 4, VMUL_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sn_Dn, arg_Sm_Dm}}, // VMUL<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|1|0|Vn:4|Vd:4|1|0|1|sz|N|0|M|0|Vm:4
{0x0fbf0ed0, 0x0eb10a40, 4, VNEG_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sm_Dm}}, // VNEG<c>.F<32,64> <Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|0|0|1|Vd:4|1|0|1|sz|0|1|M|0|Vm:4
{0x0fb00e10, 0x0e100a00, 4, VNMLS_EQ_F32, 0x60108011c04, instArgs{arg_Sd_Dd, arg_Sn_Dn, arg_Sm_Dm}}, // VN<MLS,MLA><c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|0|1|Vn:4|Vd:4|1|0|1|sz|N|op|M|0|Vm:4
{0x0fb00e50, 0x0e200a40, 4, VNMUL_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sn_Dn, arg_Sm_Dm}}, // VNMUL<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|1|0|Vn:4|Vd:4|1|0|1|sz|N|1|M|0|Vm:4
{0x0fbf0ed0, 0x0eb10ac0, 4, VSQRT_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sm_Dm}}, // VSQRT<c>.F<32,64> <Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|0|0|1|Vd:4|1|0|1|sz|1|1|M|0|Vm:4
{0x0f300e00, 0x0d000a00, 4, VSTR_EQ, 0x1c04, instArgs{arg_Sd_Dd, arg_mem_R_pm_imm8at0_offset}}, // VSTR<c> <Sd,Dd>, [<Rn>{,#+/-<imm8>}] cond:4|1|1|0|1|U|D|0|0|Rn:4|Vd:4|1|0|1|sz|imm8:8
{0x0fb00e50, 0x0e300a40, 4, VSUB_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sn_Dn, arg_Sm_Dm}}, // VSUB<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|1|1|Vn:4|Vd:4|1|0|1|sz|N|1|M|0|Vm:4
{0x0fffffff, 0x0320f002, 4, WFE_EQ, 0x1c04, instArgs{}}, // WFE<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|0
{0x0fff00ff, 0x0320f002, 3, WFE_EQ, 0x1c04, instArgs{}}, // WFE<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|0
{0x0fffffff, 0x0320f003, 4, WFI_EQ, 0x1c04, instArgs{}}, // WFI<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|1
{0x0fff00ff, 0x0320f003, 3, WFI_EQ, 0x1c04, instArgs{}}, // WFI<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|1
{0x0fffffff, 0x0320f001, 4, YIELD_EQ, 0x1c04, instArgs{}}, // YIELD<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|1
{0x0fff00ff, 0x0320f001, 3, YIELD_EQ, 0x1c04, instArgs{}}, // YIELD<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|1
{0xffffffff, 0xf7fabcfd, 4, UNDEF, 0x0, instArgs{}}, // UNDEF 1|1|1|1|0|1|1|1|1|1|1|1|1|0|1|0|1|0|1|1|1|1|0|0|1|1|1|1|1|1|0|1
}
|
