diff options
Diffstat (limited to 'vendor/golang.org/x/arch')
21 files changed, 31341 insertions, 0 deletions
diff --git a/vendor/golang.org/x/arch/arm/armasm/LICENSE b/vendor/golang.org/x/arch/arm/armasm/LICENSE new file mode 100644 index 00000000..d29b3726 --- /dev/null +++ b/vendor/golang.org/x/arch/arm/armasm/LICENSE @@ -0,0 +1,27 @@ +Copyright (c) 2015 The Go Authors. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met: + + * Redistributions of source code must retain the above copyright +notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above +copyright notice, this list of conditions and the following disclaimer +in the documentation and/or other materials provided with the +distribution. + * Neither the name of Google Inc. nor the names of its +contributors may be used to endorse or promote products derived from +this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/vendor/golang.org/x/arch/arm/armasm/decode.go b/vendor/golang.org/x/arch/arm/armasm/decode.go new file mode 100644 index 00000000..6b4d7384 --- /dev/null +++ b/vendor/golang.org/x/arch/arm/armasm/decode.go @@ -0,0 +1,567 @@ +// Copyright 2014 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package armasm + +import ( + "encoding/binary" + "fmt" +) + +// An instFormat describes the format of an instruction encoding. +// An instruction with 32-bit value x matches the format if x&mask == value +// and the condition matches. +// The condition matches if x>>28 == 0xF && value>>28==0xF +// or if x>>28 != 0xF and value>>28 == 0. +// If x matches the format, then the rest of the fields describe how to interpret x. +// The opBits describe bits that should be extracted from x and added to the opcode. +// For example opBits = 0x1234 means that the value +// (2 bits at offset 1) followed by (4 bits at offset 3) +// should be added to op. +// Finally the args describe how to decode the instruction arguments. +// args is stored as a fixed-size array; if there are fewer than len(args) arguments, +// args[i] == 0 marks the end of the argument list. +type instFormat struct { + mask uint32 + value uint32 + priority int8 + op Op + opBits uint64 + args instArgs +} + +type instArgs [4]instArg + +var ( + errMode = fmt.Errorf("unsupported execution mode") + errShort = fmt.Errorf("truncated instruction") + errUnknown = fmt.Errorf("unknown instruction") +) + +var decoderCover []bool + +// Decode decodes the leading bytes in src as a single instruction. +func Decode(src []byte, mode Mode) (inst Inst, err error) { + if mode != ModeARM { + return Inst{}, errMode + } + if len(src) < 4 { + return Inst{}, errShort + } + + if decoderCover == nil { + decoderCover = make([]bool, len(instFormats)) + } + + x := binary.LittleEndian.Uint32(src) + + // The instFormat table contains both conditional and unconditional instructions. + // Considering only the top 4 bits, the conditional instructions use mask=0, value=0, + // while the unconditional instructions use mask=f, value=f. + // Prepare a version of x with the condition cleared to 0 in conditional instructions + // and then assume mask=f during matching. + const condMask = 0xf0000000 + xNoCond := x + if x&condMask != condMask { + xNoCond &^= condMask + } + var priority int8 +Search: + for i := range instFormats { + f := &instFormats[i] + if xNoCond&(f.mask|condMask) != f.value || f.priority <= priority { + continue + } + delta := uint32(0) + deltaShift := uint(0) + for opBits := f.opBits; opBits != 0; opBits >>= 16 { + n := uint(opBits & 0xFF) + off := uint((opBits >> 8) & 0xFF) + delta |= (x >> off) & (1<<n - 1) << deltaShift + deltaShift += n + } + op := f.op + Op(delta) + + // Special case: BKPT encodes with condition but cannot have one. + if op&^15 == BKPT_EQ && op != BKPT { + continue Search + } + + var args Args + for j, aop := range f.args { + if aop == 0 { + break + } + arg := decodeArg(aop, x) + if arg == nil { // cannot decode argument + continue Search + } + args[j] = arg + } + + decoderCover[i] = true + + inst = Inst{ + Op: op, + Args: args, + Enc: x, + Len: 4, + } + priority = f.priority + continue Search + } + if inst.Op != 0 { + return inst, nil + } + return Inst{}, errUnknown +} + +// An instArg describes the encoding of a single argument. +// In the names used for arguments, _p_ means +, _m_ means -, +// _pm_ means ± (usually keyed by the U bit). +// The _W suffix indicates a general addressing mode based on the P and W bits. +// The _offset and _postindex suffixes force the given addressing mode. +// The rest should be somewhat self-explanatory, at least given +// the decodeArg function. +type instArg uint8 + +const ( + _ instArg = iota + arg_APSR + arg_FPSCR + arg_Dn_half + arg_R1_0 + arg_R1_12 + arg_R2_0 + arg_R2_12 + arg_R_0 + arg_R_12 + arg_R_12_nzcv + arg_R_16 + arg_R_16_WB + arg_R_8 + arg_R_rotate + arg_R_shift_R + arg_R_shift_imm + arg_SP + arg_Sd + arg_Sd_Dd + arg_Dd_Sd + arg_Sm + arg_Sm_Dm + arg_Sn + arg_Sn_Dn + arg_const + arg_endian + arg_fbits + arg_fp_0 + arg_imm24 + arg_imm5 + arg_imm5_32 + arg_imm5_nz + arg_imm_12at8_4at0 + arg_imm_4at16_12at0 + arg_imm_vfp + arg_label24 + arg_label24H + arg_label_m_12 + arg_label_p_12 + arg_label_pm_12 + arg_label_pm_4_4 + arg_lsb_width + arg_mem_R + arg_mem_R_pm_R_W + arg_mem_R_pm_R_postindex + arg_mem_R_pm_R_shift_imm_W + arg_mem_R_pm_R_shift_imm_offset + arg_mem_R_pm_R_shift_imm_postindex + arg_mem_R_pm_imm12_W + arg_mem_R_pm_imm12_offset + arg_mem_R_pm_imm12_postindex + arg_mem_R_pm_imm8_W + arg_mem_R_pm_imm8_postindex + arg_mem_R_pm_imm8at0_offset + arg_option + arg_registers + arg_registers1 + arg_registers2 + arg_satimm4 + arg_satimm5 + arg_satimm4m1 + arg_satimm5m1 + arg_widthm1 +) + +// decodeArg decodes the arg described by aop from the instruction bits x. +// It returns nil if x cannot be decoded according to aop. +func decodeArg(aop instArg, x uint32) Arg { + switch aop { + default: + return nil + + case arg_APSR: + return APSR + case arg_FPSCR: + return FPSCR + + case arg_R_0: + return Reg(x & (1<<4 - 1)) + case arg_R_8: + return Reg((x >> 8) & (1<<4 - 1)) + case arg_R_12: + return Reg((x >> 12) & (1<<4 - 1)) + case arg_R_16: + return Reg((x >> 16) & (1<<4 - 1)) + + case arg_R_12_nzcv: + r := Reg((x >> 12) & (1<<4 - 1)) + if r == R15 { + return APSR_nzcv + } + return r + + case arg_R_16_WB: + mode := AddrLDM + if (x>>21)&1 != 0 { + mode = AddrLDM_WB + } + return Mem{Base: Reg((x >> 16) & (1<<4 - 1)), Mode: mode} + + case arg_R_rotate: + Rm := Reg(x & (1<<4 - 1)) + typ, count := decodeShift(x) + // ROR #0 here means ROR #0, but decodeShift rewrites to RRX #1. + if typ == RotateRightExt { + return Reg(Rm) + } + return RegShift{Rm, typ, uint8(count)} + + case arg_R_shift_R: + Rm := Reg(x & (1<<4 - 1)) + Rs := Reg((x >> 8) & (1<<4 - 1)) + typ := Shift((x >> 5) & (1<<2 - 1)) + return RegShiftReg{Rm, typ, Rs} + + case arg_R_shift_imm: + Rm := Reg(x & (1<<4 - 1)) + typ, count := decodeShift(x) + if typ == ShiftLeft && count == 0 { + return Reg(Rm) + } + return RegShift{Rm, typ, uint8(count)} + + case arg_R1_0: + return Reg((x & (1<<4 - 1))) + case arg_R1_12: + return Reg(((x >> 12) & (1<<4 - 1))) + case arg_R2_0: + return Reg((x & (1<<4 - 1)) | 1) + case arg_R2_12: + return Reg(((x >> 12) & (1<<4 - 1)) | 1) + + case arg_SP: + return SP + + case arg_Sd_Dd: + v := (x >> 12) & (1<<4 - 1) + vx := (x >> 22) & 1 + sz := (x >> 8) & 1 + if sz != 0 { + return D0 + Reg(vx<<4+v) + } else { + return S0 + Reg(v<<1+vx) + } + + case arg_Dd_Sd: + return decodeArg(arg_Sd_Dd, x^(1<<8)) + + case arg_Sd: + v := (x >> 12) & (1<<4 - 1) + vx := (x >> 22) & 1 + return S0 + Reg(v<<1+vx) + + case arg_Sm_Dm: + v := (x >> 0) & (1<<4 - 1) + vx := (x >> 5) & 1 + sz := (x >> 8) & 1 + if sz != 0 { + return D0 + Reg(vx<<4+v) + } else { + return S0 + Reg(v<<1+vx) + } + + case arg_Sm: + v := (x >> 0) & (1<<4 - 1) + vx := (x >> 5) & 1 + return S0 + Reg(v<<1+vx) + + case arg_Dn_half: + v := (x >> 16) & (1<<4 - 1) + vx := (x >> 7) & 1 + return RegX{D0 + Reg(vx<<4+v), int((x >> 21) & 1)} + + case arg_Sn_Dn: + v := (x >> 16) & (1<<4 - 1) + vx := (x >> 7) & 1 + sz := (x >> 8) & 1 + if sz != 0 { + return D0 + Reg(vx<<4+v) + } else { + return S0 + Reg(v<<1+vx) + } + + case arg_Sn: + v := (x >> 16) & (1<<4 - 1) + vx := (x >> 7) & 1 + return S0 + Reg(v<<1+vx) + + case arg_const: + v := x & (1<<8 - 1) + rot := (x >> 8) & (1<<4 - 1) * 2 + if rot > 0 && v&3 == 0 { + // could rotate less + return ImmAlt{uint8(v), uint8(rot)} + } + if rot >= 24 && ((v<<(32-rot))&0xFF)>>(32-rot) == v { + // could wrap around to rot==0. + return ImmAlt{uint8(v), uint8(rot)} + } + return Imm(v>>rot | v<<(32-rot)) + + case arg_endian: + return Endian((x >> 9) & 1) + + case arg_fbits: + return Imm((16 << ((x >> 7) & 1)) - ((x&(1<<4-1))<<1 | (x>>5)&1)) + + case arg_fp_0: + return Imm(0) + + case arg_imm24: + return Imm(x & (1<<24 - 1)) + + case arg_imm5: + return Imm((x >> 7) & (1<<5 - 1)) + + case arg_imm5_32: + x = (x >> 7) & (1<<5 - 1) + if x == 0 { + x = 32 + } + return Imm(x) + + case arg_imm5_nz: + x = (x >> 7) & (1<<5 - 1) + if x == 0 { + return nil + } + return Imm(x) + + case arg_imm_4at16_12at0: + return Imm((x>>16)&(1<<4-1)<<12 | x&(1<<12-1)) + + case arg_imm_12at8_4at0: + return Imm((x>>8)&(1<<12-1)<<4 | x&(1<<4-1)) + + case arg_imm_vfp: + x = (x>>16)&(1<<4-1)<<4 | x&(1<<4-1) + return Imm(x) + + case arg_label24: + imm := (x & (1<<24 - 1)) << 2 + return PCRel(int32(imm<<6) >> 6) + + case arg_label24H: + h := (x >> 24) & 1 + imm := (x&(1<<24-1))<<2 | h<<1 + return PCRel(int32(imm<<6) >> 6) + + case arg_label_m_12: + d := int32(x & (1<<12 - 1)) + return Mem{Base: PC, Mode: AddrOffset, Offset: int16(-d)} + + case arg_label_p_12: + d := int32(x & (1<<12 - 1)) + return Mem{Base: PC, Mode: AddrOffset, Offset: int16(d)} + + case arg_label_pm_12: + d := int32(x & (1<<12 - 1)) + u := (x >> 23) & 1 + if u == 0 { + d = -d + } + return Mem{Base: PC, Mode: AddrOffset, Offset: int16(d)} + + case arg_label_pm_4_4: + d := int32((x>>8)&(1<<4-1)<<4 | x&(1<<4-1)) + u := (x >> 23) & 1 + if u == 0 { + d = -d + } + return PCRel(d) + + case arg_lsb_width: + lsb := (x >> 7) & (1<<5 - 1) + msb := (x >> 16) & (1<<5 - 1) + if msb < lsb || msb >= 32 { + return nil + } + return Imm(msb + 1 - lsb) + + case arg_mem_R: + Rn := Reg((x >> 16) & (1<<4 - 1)) + return Mem{Base: Rn, Mode: AddrOffset} + + case arg_mem_R_pm_R_postindex: + // Treat [<Rn>],+/-<Rm> like [<Rn>,+/-<Rm>{,<shift>}]{!} + // by forcing shift bits to <<0 and P=0, W=0 (postindex=true). + return decodeArg(arg_mem_R_pm_R_shift_imm_W, x&^((1<<7-1)<<5|1<<24|1<<21)) + + case arg_mem_R_pm_R_W: + // Treat [<Rn>,+/-<Rm>]{!} like [<Rn>,+/-<Rm>{,<shift>}]{!} + // by forcing shift bits to <<0. + return decodeArg(arg_mem_R_pm_R_shift_imm_W, x&^((1<<7-1)<<5)) + + case arg_mem_R_pm_R_shift_imm_offset: + // Treat [<Rn>],+/-<Rm>{,<shift>} like [<Rn>,+/-<Rm>{,<shift>}]{!} + // by forcing P=1, W=0 (index=false, wback=false). + return decodeArg(arg_mem_R_pm_R_shift_imm_W, x&^(1<<21)|1<<24) + + case arg_mem_R_pm_R_shift_imm_postindex: + // Treat [<Rn>],+/-<Rm>{,<shift>} like [<Rn>,+/-<Rm>{,<shift>}]{!} + // by forcing P=0, W=0 (postindex=true). + return decodeArg(arg_mem_R_pm_R_shift_imm_W, x&^(1<<24|1<<21)) + + case arg_mem_R_pm_R_shift_imm_W: + Rn := Reg((x >> 16) & (1<<4 - 1)) + Rm := Reg(x & (1<<4 - 1)) + typ, count := decodeShift(x) + u := (x >> 23) & 1 + w := (x >> 21) & 1 + p := (x >> 24) & 1 + if p == 0 && w == 1 { + return nil + } + sign := int8(+1) + if u == 0 { + sign = -1 + } + mode := AddrMode(uint8(p<<1) | uint8(w^1)) + return Mem{Base: Rn, Mode: mode, Sign: sign, Index: Rm, Shift: typ, Count: count} + + case arg_mem_R_pm_imm12_offset: + // Treat [<Rn>,#+/-<imm12>] like [<Rn>{,#+/-<imm12>}]{!} + // by forcing P=1, W=0 (index=false, wback=false). + return decodeArg(arg_mem_R_pm_imm12_W, x&^(1<<21)|1<<24) + + case arg_mem_R_pm_imm12_postindex: + // Treat [<Rn>],#+/-<imm12> like [<Rn>{,#+/-<imm12>}]{!} + // by forcing P=0, W=0 (postindex=true). + return decodeArg(arg_mem_R_pm_imm12_W, x&^(1<<24|1<<21)) + + case arg_mem_R_pm_imm12_W: + Rn := Reg((x >> 16) & (1<<4 - 1)) + u := (x >> 23) & 1 + w := (x >> 21) & 1 + p := (x >> 24) & 1 + if p == 0 && w == 1 { + return nil + } + sign := int8(+1) + if u == 0 { + sign = -1 + } + imm := int16(x & (1<<12 - 1)) + mode := AddrMode(uint8(p<<1) | uint8(w^1)) + return Mem{Base: Rn, Mode: mode, Offset: int16(sign) * imm} + + case arg_mem_R_pm_imm8_postindex: + // Treat [<Rn>],#+/-<imm8> like [<Rn>{,#+/-<imm8>}]{!} + // by forcing P=0, W=0 (postindex=true). + return decodeArg(arg_mem_R_pm_imm8_W, x&^(1<<24|1<<21)) + + case arg_mem_R_pm_imm8_W: + Rn := Reg((x >> 16) & (1<<4 - 1)) + u := (x >> 23) & 1 + w := (x >> 21) & 1 + p := (x >> 24) & 1 + if p == 0 && w == 1 { + return nil + } + sign := int8(+1) + if u == 0 { + sign = -1 + } + imm := int16((x>>8)&(1<<4-1)<<4 | x&(1<<4-1)) + mode := AddrMode(uint8(p<<1) | uint8(w^1)) + return Mem{Base: Rn, Mode: mode, Offset: int16(sign) * imm} + + case arg_mem_R_pm_imm8at0_offset: + Rn := Reg((x >> 16) & (1<<4 - 1)) + u := (x >> 23) & 1 + sign := int8(+1) + if u == 0 { + sign = -1 + } + imm := int16(x&(1<<8-1)) << 2 + return Mem{Base: Rn, Mode: AddrOffset, Offset: int16(sign) * imm} + + case arg_option: + return Imm(x & (1<<4 - 1)) + + case arg_registers: + return RegList(x & (1<<16 - 1)) + + case arg_registers2: + x &= 1<<16 - 1 + n := 0 + for i := 0; i < 16; i++ { + if x>>uint(i)&1 != 0 { + n++ + } + } + if n < 2 { + return nil + } + return RegList(x) + + case arg_registers1: + Rt := (x >> 12) & (1<<4 - 1) + return RegList(1 << Rt) + + case arg_satimm4: + return Imm((x >> 16) & (1<<4 - 1)) + + case arg_satimm5: + return Imm((x >> 16) & (1<<5 - 1)) + + case arg_satimm4m1: + return Imm((x>>16)&(1<<4-1) + 1) + + case arg_satimm5m1: + return Imm((x>>16)&(1<<5-1) + 1) + + case arg_widthm1: + return Imm((x>>16)&(1<<5-1) + 1) + + } +} + +// decodeShift decodes the shift-by-immediate encoded in x. +func decodeShift(x uint32) (Shift, uint8) { + count := (x >> 7) & (1<<5 - 1) + typ := Shift((x >> 5) & (1<<2 - 1)) + switch typ { + case ShiftRight, ShiftRightSigned: + if count == 0 { + count = 32 + } + case RotateRight: + if count == 0 { + typ = RotateRightExt + count = 1 + } + } + return typ, uint8(count) +} diff --git a/vendor/golang.org/x/arch/arm/armasm/gnu.go b/vendor/golang.org/x/arch/arm/armasm/gnu.go new file mode 100644 index 00000000..1a97a5a8 --- /dev/null +++ b/vendor/golang.org/x/arch/arm/armasm/gnu.go @@ -0,0 +1,164 @@ +// Copyright 2014 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package armasm + +import ( + "bytes" + "fmt" + "strings" +) + +var saveDot = strings.NewReplacer( + ".F16", "_dot_F16", + ".F32", "_dot_F32", + ".F64", "_dot_F64", + ".S32", "_dot_S32", + ".U32", "_dot_U32", + ".FXS", "_dot_S", + ".FXU", "_dot_U", + ".32", "_dot_32", +) + +// GNUSyntax returns the GNU assembler syntax for the instruction, as defined by GNU binutils. +// This form typically matches the syntax defined in the ARM Reference Manual. +func GNUSyntax(inst Inst) string { + var buf bytes.Buffer + op := inst.Op.String() + op = saveDot.Replace(op) + op = strings.Replace(op, ".", "", -1) + op = strings.Replace(op, "_dot_", ".", -1) + op = strings.ToLower(op) + buf.WriteString(op) + sep := " " + for i, arg := range inst.Args { + if arg == nil { + break + } + text := gnuArg(&inst, i, arg) + if text == "" { + continue + } + buf.WriteString(sep) + sep = ", " + buf.WriteString(text) + } + return buf.String() +} + +func gnuArg(inst *Inst, argIndex int, arg Arg) string { + switch inst.Op &^ 15 { + case LDRD_EQ, LDREXD_EQ, STRD_EQ: + if argIndex == 1 { + // second argument in consecutive pair not printed + return "" + } + case STREXD_EQ: + if argIndex == 2 { + // second argument in consecutive pair not printed + return "" + } + } + + switch arg := arg.(type) { + case Imm: + switch inst.Op &^ 15 { + case BKPT_EQ: + return fmt.Sprintf("%#04x", uint32(arg)) + case SVC_EQ: + return fmt.Sprintf("%#08x", uint32(arg)) + } + return fmt.Sprintf("#%d", int32(arg)) + + case ImmAlt: + return fmt.Sprintf("#%d, %d", arg.Val, arg.Rot) + + case Mem: + R := gnuArg(inst, -1, arg.Base) + X := "" + if arg.Sign != 0 { + X = "" + if arg.Sign < 0 { + X = "-" + } + X += gnuArg(inst, -1, arg.Index) + if arg.Shift == ShiftLeft && arg.Count == 0 { + // nothing + } else if arg.Shift == RotateRightExt { + X += ", rrx" + } else { + X += fmt.Sprintf(", %s #%d", strings.ToLower(arg.Shift.String()), arg.Count) + } + } else { + X = fmt.Sprintf("#%d", arg.Offset) + } + + switch arg.Mode { + case AddrOffset: + if X == "#0" { + return fmt.Sprintf("[%s]", R) + } + return fmt.Sprintf("[%s, %s]", R, X) + case AddrPreIndex: + return fmt.Sprintf("[%s, %s]!", R, X) + case AddrPostIndex: + return fmt.Sprintf("[%s], %s", R, X) + case AddrLDM: + if X == "#0" { + return R + } + case AddrLDM_WB: + if X == "#0" { + return R + "!" + } + } + return fmt.Sprintf("[%s Mode(%d) %s]", R, int(arg.Mode), X) + + case PCRel: + return fmt.Sprintf(".%+#x", int32(arg)+4) + + case Reg: + switch inst.Op &^ 15 { + case LDREX_EQ: + if argIndex == 0 { + return fmt.Sprintf("r%d", int32(arg)) + } + } + switch arg { + case R10: + return "sl" + case R11: + return "fp" + case R12: + return "ip" + } + + case RegList: + var buf bytes.Buffer + fmt.Fprintf(&buf, "{") + sep := "" + for i := 0; i < 16; i++ { + if arg&(1<<uint(i)) != 0 { + fmt.Fprintf(&buf, "%s%s", sep, gnuArg(inst, -1, Reg(i))) + sep = ", " + } + } + fmt.Fprintf(&buf, "}") + return buf.String() + + case RegShift: + if arg.Shift == ShiftLeft && arg.Count == 0 { + return gnuArg(inst, -1, arg.Reg) + } + if arg.Shift == RotateRightExt { + return gnuArg(inst, -1, arg.Reg) + ", rrx" + } + return fmt.Sprintf("%s, %s #%d", gnuArg(inst, -1, arg.Reg), strings.ToLower(arg.Shift.String()), arg.Count) + + case RegShiftReg: + return fmt.Sprintf("%s, %s %s", gnuArg(inst, -1, arg.Reg), strings.ToLower(arg.Shift.String()), gnuArg(inst, -1, arg.RegCount)) + + } + return strings.ToLower(arg.String()) +} diff --git a/vendor/golang.org/x/arch/arm/armasm/inst.go b/vendor/golang.org/x/arch/arm/armasm/inst.go new file mode 100644 index 00000000..60d633bd --- /dev/null +++ b/vendor/golang.org/x/arch/arm/armasm/inst.go @@ -0,0 +1,438 @@ +// Copyright 2014 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package armasm + +import ( + "bytes" + "fmt" +) + +// A Mode is an instruction execution mode. +type Mode int + +const ( + _ Mode = iota + ModeARM + ModeThumb +) + +func (m Mode) String() string { + switch m { + case ModeARM: + return "ARM" + case ModeThumb: + return "Thumb" + } + return fmt.Sprintf("Mode(%d)", int(m)) +} + +// An Op is an ARM opcode. +type Op uint16 + +// NOTE: The actual Op values are defined in tables.go. +// They are chosen to simplify instruction decoding and +// are not a dense packing from 0 to N, although the +// density is high, probably at least 90%. + +func (op Op) String() string { + if op >= Op(len(opstr)) || opstr[op] == "" { + return fmt.Sprintf("Op(%d)", int(op)) + } + return opstr[op] +} + +// An Inst is a single instruction. +type Inst struct { + Op Op // Opcode mnemonic + Enc uint32 // Raw encoding bits. + Len int // Length of encoding in bytes. + Args Args // Instruction arguments, in ARM manual order. +} + +func (i Inst) String() string { + var buf bytes.Buffer + buf.WriteString(i.Op.String()) + for j, arg := range i.Args { + if arg == nil { + break + } + if j == 0 { + buf.WriteString(" ") + } else { + buf.WriteString(", ") + } + buf.WriteString(arg.String()) + } + return buf.String() +} + +// An Args holds the instruction arguments. +// If an instruction has fewer than 4 arguments, +// the final elements in the array are nil. +type Args [4]Arg + +// An Arg is a single instruction argument, one of these types: +// Endian, Imm, Mem, PCRel, Reg, RegList, RegShift, RegShiftReg. +type Arg interface { + IsArg() + String() string +} + +type Float32Imm float32 + +func (Float32Imm) IsArg() {} + +func (f Float32Imm) String() string { + return fmt.Sprintf("#%v", float32(f)) +} + +type Float64Imm float32 + +func (Float64Imm) IsArg() {} + +func (f Float64Imm) String() string { + return fmt.Sprintf("#%v", float64(f)) +} + +// An Imm is an integer constant. +type Imm uint32 + +func (Imm) IsArg() {} + +func (i Imm) String() string { + return fmt.Sprintf("#%#x", uint32(i)) +} + +// A ImmAlt is an alternate encoding of an integer constant. +type ImmAlt struct { + Val uint8 + Rot uint8 +} + +func (ImmAlt) IsArg() {} + +func (i ImmAlt) Imm() Imm { + v := uint32(i.Val) + r := uint(i.Rot) + return Imm(v>>r | v<<(32-r)) +} + +func (i ImmAlt) String() string { + return fmt.Sprintf("#%#x, %d", i.Val, i.Rot) +} + +// A Label is a text (code) address. +type Label uint32 + +func (Label) IsArg() {} + +func (i Label) String() string { + return fmt.Sprintf("%#x", uint32(i)) +} + +// A Reg is a single register. +// The zero value denotes R0, not the absence of a register. +type Reg uint8 + +const ( + R0 Reg = iota + R1 + R2 + R3 + R4 + R5 + R6 + R7 + R8 + R9 + R10 + R11 + R12 + R13 + R14 + R15 + + S0 + S1 + S2 + S3 + S4 + S5 + S6 + S7 + S8 + S9 + S10 + S11 + S12 + S13 + S14 + S15 + S16 + S17 + S18 + S19 + S20 + S21 + S22 + S23 + S24 + S25 + S26 + S27 + S28 + S29 + S30 + S31 + + D0 + D1 + D2 + D3 + D4 + D5 + D6 + D7 + D8 + D9 + D10 + D11 + D12 + D13 + D14 + D15 + D16 + D17 + D18 + D19 + D20 + D21 + D22 + D23 + D24 + D25 + D26 + D27 + D28 + D29 + D30 + D31 + + APSR + APSR_nzcv + FPSCR + + SP = R13 + LR = R14 + PC = R15 +) + +func (Reg) IsArg() {} + +func (r Reg) String() string { + switch r { + case APSR: + return "APSR" + case APSR_nzcv: + return "APSR_nzcv" + case FPSCR: + return "FPSCR" + case SP: + return "SP" + case PC: + return "PC" + case LR: + return "LR" + } + if R0 <= r && r <= R15 { + return fmt.Sprintf("R%d", int(r-R0)) + } + if S0 <= r && r <= S31 { + return fmt.Sprintf("S%d", int(r-S0)) + } + if D0 <= r && r <= D31 { + return fmt.Sprintf("D%d", int(r-D0)) + } + return fmt.Sprintf("Reg(%d)", int(r)) +} + +// A RegX represents a fraction of a multi-value register. +// The Index field specifies the index number, +// but the size of the fraction is not specified. +// It must be inferred from the instruction and the register type. +// For example, in a VMOV instruction, RegX{D5, 1} represents +// the top 32 bits of the 64-bit D5 register. +type RegX struct { + Reg Reg + Index int +} + +func (RegX) IsArg() {} + +func (r RegX) String() string { + return fmt.Sprintf("%s[%d]", r.Reg, r.Index) +} + +// A RegList is a register list. +// Bits at indexes x = 0 through 15 indicate whether the corresponding Rx register is in the list. +type RegList uint16 + +func (RegList) IsArg() {} + +func (r RegList) String() string { + var buf bytes.Buffer + fmt.Fprintf(&buf, "{") + sep := "" + for i := 0; i < 16; i++ { + if r&(1<<uint(i)) != 0 { + fmt.Fprintf(&buf, "%s%s", sep, Reg(i).String()) + sep = "," + } + } + fmt.Fprintf(&buf, "}") + return buf.String() +} + +// An Endian is the argument to the SETEND instruction. +type Endian uint8 + +const ( + LittleEndian Endian = 0 + BigEndian Endian = 1 +) + +func (Endian) IsArg() {} + +func (e Endian) String() string { + if e != 0 { + return "BE" + } + return "LE" +} + +// A Shift describes an ARM shift operation. +type Shift uint8 + +const ( + ShiftLeft Shift = 0 // left shift + ShiftRight Shift = 1 // logical (unsigned) right shift + ShiftRightSigned Shift = 2 // arithmetic (signed) right shift + RotateRight Shift = 3 // right rotate + RotateRightExt Shift = 4 // right rotate through carry (Count will always be 1) +) + +var shiftName = [...]string{ + "LSL", "LSR", "ASR", "ROR", "RRX", +} + +func (s Shift) String() string { + if s < 5 { + return shiftName[s] + } + return fmt.Sprintf("Shift(%d)", int(s)) +} + +// A RegShift is a register shifted by a constant. +type RegShift struct { + Reg Reg + Shift Shift + Count uint8 +} + +func (RegShift) IsArg() {} + +func (r RegShift) String() string { + return fmt.Sprintf("%s %s #%d", r.Reg, r.Shift, r.Count) +} + +// A RegShiftReg is a register shifted by a register. +type RegShiftReg struct { + Reg Reg + Shift Shift + RegCount Reg +} + +func (RegShiftReg) IsArg() {} + +func (r RegShiftReg) String() string { + return fmt.Sprintf("%s %s %s", r.Reg, r.Shift, r.RegCount) +} + +// A PCRel describes a memory address (usually a code label) +// as a distance relative to the program counter. +// TODO(rsc): Define which program counter (PC+4? PC+8? PC?). +type PCRel int32 + +func (PCRel) IsArg() {} + +func (r PCRel) String() string { + return fmt.Sprintf("PC%+#x", int32(r)) +} + +// An AddrMode is an ARM addressing mode. +type AddrMode uint8 + +const ( + _ AddrMode = iota + AddrPostIndex // [R], X – use address R, set R = R + X + AddrPreIndex // [R, X]! – use address R + X, set R = R + X + AddrOffset // [R, X] – use address R + X + AddrLDM // R – [R] but formats as R, for LDM/STM only + AddrLDM_WB // R! - [R], X where X is instruction-specific amount, for LDM/STM only +) + +// A Mem is a memory reference made up of a base R and index expression X. +// The effective memory address is R or R+X depending on AddrMode. +// The index expression is X = Sign*(Index Shift Count) + Offset, +// but in any instruction either Sign = 0 or Offset = 0. +type Mem struct { + Base Reg + Mode AddrMode + Sign int8 + Index Reg + Shift Shift + Count uint8 + Offset int16 +} + +func (Mem) IsArg() {} + +func (m Mem) String() string { + R := m.Base.String() + X := "" + if m.Sign != 0 { + X = "+" + if m.Sign < 0 { + X = "-" + } + X += m.Index.String() + if m.Shift != ShiftLeft || m.Count != 0 { + X += fmt.Sprintf(", %s #%d", m.Shift, m.Count) + } + } else { + X = fmt.Sprintf("#%d", m.Offset) + } + + switch m.Mode { + case AddrOffset: + if X == "#0" { + return fmt.Sprintf("[%s]", R) + } + return fmt.Sprintf("[%s, %s]", R, X) + case AddrPreIndex: + return fmt.Sprintf("[%s, %s]!", R, X) + case AddrPostIndex: + return fmt.Sprintf("[%s], %s", R, X) + case AddrLDM: + if X == "#0" { + return R + } + case AddrLDM_WB: + if X == "#0" { + return R + "!" + } + } + return fmt.Sprintf("[%s Mode(%d) %s]", R, int(m.Mode), X) +} diff --git a/vendor/golang.org/x/arch/arm/armasm/plan9x.go b/vendor/golang.org/x/arch/arm/armasm/plan9x.go new file mode 100644 index 00000000..d43cc963 --- /dev/null +++ b/vendor/golang.org/x/arch/arm/armasm/plan9x.go @@ -0,0 +1,215 @@ +// Copyright 2014 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package armasm + +import ( + "bytes" + "encoding/binary" + "fmt" + "io" + "strings" +) + +// GoSyntax returns the Go assembler syntax for the instruction. +// The syntax was originally defined by Plan 9. +// The pc is the program counter of the instruction, used for expanding +// PC-relative addresses into absolute ones. +// The symname function queries the symbol table for the program +// being disassembled. Given a target address it returns the name and base +// address of the symbol containing the target, if any; otherwise it returns "", 0. +// The reader r should read from the text segment using text addresses +// as offsets; it is used to display pc-relative loads as constant loads. +func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text io.ReaderAt) string { + if symname == nil { + symname = func(uint64) (string, uint64) { return "", 0 } + } + + var args []string + for _, a := range inst.Args { + if a == nil { + break + } + args = append(args, plan9Arg(&inst, pc, symname, a)) + } + + op := inst.Op.String() + + switch inst.Op &^ 15 { + case LDR_EQ, LDRB_EQ, LDRH_EQ: + // Check for RET + reg, _ := inst.Args[0].(Reg) + mem, _ := inst.Args[1].(Mem) + if inst.Op&^15 == LDR_EQ && reg == R15 && mem.Base == SP && mem.Sign == 0 && mem.Mode == AddrPostIndex { + return fmt.Sprintf("RET%s #%d", op[3:], mem.Offset) + } + + // Check for PC-relative load. + if mem.Base == PC && mem.Sign == 0 && mem.Mode == AddrOffset && text != nil { + addr := uint32(pc) + 8 + uint32(mem.Offset) + buf := make([]byte, 4) + switch inst.Op &^ 15 { + case LDRB_EQ: + if _, err := text.ReadAt(buf[:1], int64(addr)); err != nil { + break + } + args[1] = fmt.Sprintf("$%#x", buf[0]) + + case LDRH_EQ: + if _, err := text.ReadAt(buf[:2], int64(addr)); err != nil { + break + } + args[1] = fmt.Sprintf("$%#x", binary.LittleEndian.Uint16(buf)) + + case LDR_EQ: + if _, err := text.ReadAt(buf, int64(addr)); err != nil { + break + } + x := binary.LittleEndian.Uint32(buf) + if s, base := symname(uint64(x)); s != "" && uint64(x) == base { + args[1] = fmt.Sprintf("$%s(SB)", s) + } else { + args[1] = fmt.Sprintf("$%#x", x) + } + } + } + } + + // Move addressing mode into opcode suffix. + suffix := "" + switch inst.Op &^ 15 { + case LDR_EQ, LDRB_EQ, LDRH_EQ, STR_EQ, STRB_EQ, STRH_EQ: + mem, _ := inst.Args[1].(Mem) + switch mem.Mode { + case AddrOffset, AddrLDM: + // no suffix + case AddrPreIndex, AddrLDM_WB: + suffix = ".W" + case AddrPostIndex: + suffix = ".P" + } + off := "" + if mem.Offset != 0 { + off = fmt.Sprintf("%#x", mem.Offset) + } + base := fmt.Sprintf("(R%d)", int(mem.Base)) + index := "" + if mem.Sign != 0 { + sign := "" + if mem.Sign < 0 { + sign = "" + } + shift := "" + if mem.Count != 0 { + shift = fmt.Sprintf("%s%d", plan9Shift[mem.Shift], mem.Count) + } + index = fmt.Sprintf("(%sR%d%s)", sign, int(mem.Index), shift) + } + args[1] = off + base + index + } + + // Reverse args, placing dest last. + for i, j := 0, len(args)-1; i < j; i, j = i+1, j-1 { + args[i], args[j] = args[j], args[i] + } + + switch inst.Op &^ 15 { + case MOV_EQ: + op = "MOVW" + op[3:] + + case LDR_EQ: + op = "MOVW" + op[3:] + suffix + case LDRB_EQ: + op = "MOVB" + op[4:] + suffix + case LDRH_EQ: + op = "MOVH" + op[4:] + suffix + + case STR_EQ: + op = "MOVW" + op[3:] + suffix + args[0], args[1] = args[1], args[0] + case STRB_EQ: + op = "MOVB" + op[4:] + suffix + args[0], args[1] = args[1], args[0] + case STRH_EQ: + op = "MOVH" + op[4:] + suffix + args[0], args[1] = args[1], args[0] + } + + if args != nil { + op += " " + strings.Join(args, ", ") + } + + return op +} + +// assembler syntax for the various shifts. +// @x> is a lie; the assembler uses @> 0 +// instead of @x> 1, but i wanted to be clear that it +// was a different operation (rotate right extended, not rotate right). +var plan9Shift = []string{"<<", ">>", "->", "@>", "@x>"} + +func plan9Arg(inst *Inst, pc uint64, symname func(uint64) (string, uint64), arg Arg) string { + switch a := arg.(type) { + case Endian: + + case Imm: + return fmt.Sprintf("$%d", int(a)) + + case Mem: + + case PCRel: + addr := uint32(pc) + 8 + uint32(a) + if s, base := symname(uint64(addr)); s != "" && uint64(addr) == base { + return fmt.Sprintf("%s(SB)", s) + } + return fmt.Sprintf("%#x", addr) + + case Reg: + if a < 16 { + return fmt.Sprintf("R%d", int(a)) + } + + case RegList: + var buf bytes.Buffer + start := -2 + end := -2 + fmt.Fprintf(&buf, "[") + flush := func() { + if start >= 0 { + if buf.Len() > 1 { + fmt.Fprintf(&buf, ",") + } + if start == end { + fmt.Fprintf(&buf, "R%d", start) + } else { + fmt.Fprintf(&buf, "R%d-R%d", start, end) + } + start = -2 + end = -2 + } + } + for i := 0; i < 16; i++ { + if a&(1<<uint(i)) != 0 { + if i == end+1 { + end++ + continue + } + start = i + end = i + } else { + flush() + } + } + flush() + fmt.Fprintf(&buf, "]") + return buf.String() + + case RegShift: + return fmt.Sprintf("R%d%s$%d", int(a.Reg), plan9Shift[a.Shift], int(a.Count)) + + case RegShiftReg: + return fmt.Sprintf("R%d%sR%d", int(a.Reg), plan9Shift[a.Shift], int(a.RegCount)) + } + return strings.ToUpper(arg.String()) +} diff --git a/vendor/golang.org/x/arch/arm/armasm/tables.go b/vendor/golang.org/x/arch/arm/armasm/tables.go new file mode 100644 index 00000000..58f51fe1 --- /dev/null +++ b/vendor/golang.org/x/arch/arm/armasm/tables.go @@ -0,0 +1,9448 @@ +package armasm + +const ( + _ Op = iota + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + ADC_EQ + ADC_NE + ADC_CS + ADC_CC + ADC_MI + ADC_PL + ADC_VS + ADC_VC + ADC_HI + ADC_LS + ADC_GE + ADC_LT + ADC_GT + ADC_LE + ADC + ADC_ZZ + ADC_S_EQ + ADC_S_NE + ADC_S_CS + ADC_S_CC + ADC_S_MI + ADC_S_PL + ADC_S_VS + ADC_S_VC + ADC_S_HI + ADC_S_LS + ADC_S_GE + ADC_S_LT + ADC_S_GT + ADC_S_LE + ADC_S + ADC_S_ZZ + ADD_EQ + ADD_NE + ADD_CS + ADD_CC + ADD_MI + ADD_PL + ADD_VS + ADD_VC + ADD_HI + ADD_LS + ADD_GE + ADD_LT + ADD_GT + ADD_LE + ADD + ADD_ZZ + ADD_S_EQ + ADD_S_NE + ADD_S_CS + ADD_S_CC + ADD_S_MI + ADD_S_PL + ADD_S_VS + ADD_S_VC + ADD_S_HI + ADD_S_LS + ADD_S_GE + ADD_S_LT + ADD_S_GT + ADD_S_LE + ADD_S + ADD_S_ZZ + AND_EQ + AND_NE + AND_CS + AND_CC + AND_MI + AND_PL + AND_VS + AND_VC + AND_HI + AND_LS + AND_GE + AND_LT + AND_GT + AND_LE + AND + AND_ZZ + AND_S_EQ + AND_S_NE + AND_S_CS + AND_S_CC + AND_S_MI + AND_S_PL + AND_S_VS + AND_S_VC + AND_S_HI + AND_S_LS + AND_S_GE + AND_S_LT + AND_S_GT + AND_S_LE + AND_S + AND_S_ZZ + ASR_EQ + ASR_NE + ASR_CS + ASR_CC + ASR_MI + ASR_PL + ASR_VS + ASR_VC + ASR_HI + ASR_LS + ASR_GE + ASR_LT + ASR_GT + ASR_LE + ASR + ASR_ZZ + ASR_S_EQ + ASR_S_NE + ASR_S_CS + ASR_S_CC + ASR_S_MI + ASR_S_PL + ASR_S_VS + ASR_S_VC + ASR_S_HI + ASR_S_LS + ASR_S_GE + ASR_S_LT + ASR_S_GT + ASR_S_LE + ASR_S + ASR_S_ZZ + B_EQ + B_NE + B_CS + B_CC + B_MI + B_PL + B_VS + B_VC + B_HI + B_LS + B_GE + B_LT + B_GT + B_LE + B + B_ZZ + BFC_EQ + BFC_NE + BFC_CS + BFC_CC + BFC_MI + BFC_PL + BFC_VS + BFC_VC + BFC_HI + BFC_LS + BFC_GE + BFC_LT + BFC_GT + BFC_LE + BFC + BFC_ZZ + BFI_EQ + BFI_NE + BFI_CS + BFI_CC + BFI_MI + BFI_PL + BFI_VS + BFI_VC + BFI_HI + BFI_LS + BFI_GE + BFI_LT + BFI_GT + BFI_LE + BFI + BFI_ZZ + BIC_EQ + BIC_NE + BIC_CS + BIC_CC + BIC_MI + BIC_PL + BIC_VS + BIC_VC + BIC_HI + BIC_LS + BIC_GE + BIC_LT + BIC_GT + BIC_LE + BIC + BIC_ZZ + BIC_S_EQ + BIC_S_NE + BIC_S_CS + BIC_S_CC + BIC_S_MI + BIC_S_PL + BIC_S_VS + BIC_S_VC + BIC_S_HI + BIC_S_LS + BIC_S_GE + BIC_S_LT + BIC_S_GT + BIC_S_LE + BIC_S + BIC_S_ZZ + BKPT_EQ + BKPT_NE + BKPT_CS + BKPT_CC + BKPT_MI + BKPT_PL + BKPT_VS + BKPT_VC + BKPT_HI + BKPT_LS + BKPT_GE + BKPT_LT + BKPT_GT + BKPT_LE + BKPT + BKPT_ZZ + BL_EQ + BL_NE + BL_CS + BL_CC + BL_MI + BL_PL + BL_VS + BL_VC + BL_HI + BL_LS + BL_GE + BL_LT + BL_GT + BL_LE + BL + BL_ZZ + BLX_EQ + BLX_NE + BLX_CS + BLX_CC + BLX_MI + BLX_PL + BLX_VS + BLX_VC + BLX_HI + BLX_LS + BLX_GE + BLX_LT + BLX_GT + BLX_LE + BLX + BLX_ZZ + BX_EQ + BX_NE + BX_CS + BX_CC + BX_MI + BX_PL + BX_VS + BX_VC + BX_HI + BX_LS + BX_GE + BX_LT + BX_GT + BX_LE + BX + BX_ZZ + BXJ_EQ + BXJ_NE + BXJ_CS + BXJ_CC + BXJ_MI + BXJ_PL + BXJ_VS + BXJ_VC + BXJ_HI + BXJ_LS + BXJ_GE + BXJ_LT + BXJ_GT + BXJ_LE + BXJ + BXJ_ZZ + CLREX + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + CLZ_EQ + CLZ_NE + CLZ_CS + CLZ_CC + CLZ_MI + CLZ_PL + CLZ_VS + CLZ_VC + CLZ_HI + CLZ_LS + CLZ_GE + CLZ_LT + CLZ_GT + CLZ_LE + CLZ + CLZ_ZZ + CMN_EQ + CMN_NE + CMN_CS + CMN_CC + CMN_MI + CMN_PL + CMN_VS + CMN_VC + CMN_HI + CMN_LS + CMN_GE + CMN_LT + CMN_GT + CMN_LE + CMN + CMN_ZZ + CMP_EQ + CMP_NE + CMP_CS + CMP_CC + CMP_MI + CMP_PL + CMP_VS + CMP_VC + CMP_HI + CMP_LS + CMP_GE + CMP_LT + CMP_GT + CMP_LE + CMP + CMP_ZZ + DBG_EQ + DBG_NE + DBG_CS + DBG_CC + DBG_MI + DBG_PL + DBG_VS + DBG_VC + DBG_HI + DBG_LS + DBG_GE + DBG_LT + DBG_GT + DBG_LE + DBG + DBG_ZZ + DMB + DSB + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + EOR_EQ + EOR_NE + EOR_CS + EOR_CC + EOR_MI + EOR_PL + EOR_VS + EOR_VC + EOR_HI + EOR_LS + EOR_GE + EOR_LT + EOR_GT + EOR_LE + EOR + EOR_ZZ + EOR_S_EQ + EOR_S_NE + EOR_S_CS + EOR_S_CC + EOR_S_MI + EOR_S_PL + EOR_S_VS + EOR_S_VC + EOR_S_HI + EOR_S_LS + EOR_S_GE + EOR_S_LT + EOR_S_GT + EOR_S_LE + EOR_S + EOR_S_ZZ + ISB + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + LDM_EQ + LDM_NE + LDM_CS + LDM_CC + LDM_MI + LDM_PL + LDM_VS + LDM_VC + LDM_HI + LDM_LS + LDM_GE + LDM_LT + LDM_GT + LDM_LE + LDM + LDM_ZZ + LDMDA_EQ + LDMDA_NE + LDMDA_CS + LDMDA_CC + LDMDA_MI + LDMDA_PL + LDMDA_VS + LDMDA_VC + LDMDA_HI + LDMDA_LS + LDMDA_GE + LDMDA_LT + LDMDA_GT + LDMDA_LE + LDMDA + LDMDA_ZZ + LDMDB_EQ + LDMDB_NE + LDMDB_CS + LDMDB_CC + LDMDB_MI + LDMDB_PL + LDMDB_VS + LDMDB_VC + LDMDB_HI + LDMDB_LS + LDMDB_GE + LDMDB_LT + LDMDB_GT + LDMDB_LE + LDMDB + LDMDB_ZZ + LDMIB_EQ + LDMIB_NE + LDMIB_CS + LDMIB_CC + LDMIB_MI + LDMIB_PL + LDMIB_VS + LDMIB_VC + LDMIB_HI + LDMIB_LS + LDMIB_GE + LDMIB_LT + LDMIB_GT + LDMIB_LE + LDMIB + LDMIB_ZZ + LDR_EQ + LDR_NE + LDR_CS + LDR_CC + LDR_MI + LDR_PL + LDR_VS + LDR_VC + LDR_HI + LDR_LS + LDR_GE + LDR_LT + LDR_GT + LDR_LE + LDR + LDR_ZZ + LDRB_EQ + LDRB_NE + LDRB_CS + LDRB_CC + LDRB_MI + LDRB_PL + LDRB_VS + LDRB_VC + LDRB_HI + LDRB_LS + LDRB_GE + LDRB_LT + LDRB_GT + LDRB_LE + LDRB + LDRB_ZZ + LDRBT_EQ + LDRBT_NE + LDRBT_CS + LDRBT_CC + LDRBT_MI + LDRBT_PL + LDRBT_VS + LDRBT_VC + LDRBT_HI + LDRBT_LS + LDRBT_GE + LDRBT_LT + LDRBT_GT + LDRBT_LE + LDRBT + LDRBT_ZZ + LDRD_EQ + LDRD_NE + LDRD_CS + LDRD_CC + LDRD_MI + LDRD_PL + LDRD_VS + LDRD_VC + LDRD_HI + LDRD_LS + LDRD_GE + LDRD_LT + LDRD_GT + LDRD_LE + LDRD + LDRD_ZZ + LDREX_EQ + LDREX_NE + LDREX_CS + LDREX_CC + LDREX_MI + LDREX_PL + LDREX_VS + LDREX_VC + LDREX_HI + LDREX_LS + LDREX_GE + LDREX_LT + LDREX_GT + LDREX_LE + LDREX + LDREX_ZZ + LDREXB_EQ + LDREXB_NE + LDREXB_CS + LDREXB_CC + LDREXB_MI + LDREXB_PL + LDREXB_VS + LDREXB_VC + LDREXB_HI + LDREXB_LS + LDREXB_GE + LDREXB_LT + LDREXB_GT + LDREXB_LE + LDREXB + LDREXB_ZZ + LDREXD_EQ + LDREXD_NE + LDREXD_CS + LDREXD_CC + LDREXD_MI + LDREXD_PL + LDREXD_VS + LDREXD_VC + LDREXD_HI + LDREXD_LS + LDREXD_GE + LDREXD_LT + LDREXD_GT + LDREXD_LE + LDREXD + LDREXD_ZZ + LDREXH_EQ + LDREXH_NE + LDREXH_CS + LDREXH_CC + LDREXH_MI + LDREXH_PL + LDREXH_VS + LDREXH_VC + LDREXH_HI + LDREXH_LS + LDREXH_GE + LDREXH_LT + LDREXH_GT + LDREXH_LE + LDREXH + LDREXH_ZZ + LDRH_EQ + LDRH_NE + LDRH_CS + LDRH_CC + LDRH_MI + LDRH_PL + LDRH_VS + LDRH_VC + LDRH_HI + LDRH_LS + LDRH_GE + LDRH_LT + LDRH_GT + LDRH_LE + LDRH + LDRH_ZZ + LDRHT_EQ + LDRHT_NE + LDRHT_CS + LDRHT_CC + LDRHT_MI + LDRHT_PL + LDRHT_VS + LDRHT_VC + LDRHT_HI + LDRHT_LS + LDRHT_GE + LDRHT_LT + LDRHT_GT + LDRHT_LE + LDRHT + LDRHT_ZZ + LDRSB_EQ + LDRSB_NE + LDRSB_CS + LDRSB_CC + LDRSB_MI + LDRSB_PL + LDRSB_VS + LDRSB_VC + LDRSB_HI + LDRSB_LS + LDRSB_GE + LDRSB_LT + LDRSB_GT + LDRSB_LE + LDRSB + LDRSB_ZZ + LDRSBT_EQ + LDRSBT_NE + LDRSBT_CS + LDRSBT_CC + LDRSBT_MI + LDRSBT_PL + LDRSBT_VS + LDRSBT_VC + LDRSBT_HI + LDRSBT_LS + LDRSBT_GE + LDRSBT_LT + LDRSBT_GT + LDRSBT_LE + LDRSBT + LDRSBT_ZZ + LDRSH_EQ + LDRSH_NE + LDRSH_CS + LDRSH_CC + LDRSH_MI + LDRSH_PL + LDRSH_VS + LDRSH_VC + LDRSH_HI + LDRSH_LS + LDRSH_GE + LDRSH_LT + LDRSH_GT + LDRSH_LE + LDRSH + LDRSH_ZZ + LDRSHT_EQ + LDRSHT_NE + LDRSHT_CS + LDRSHT_CC + LDRSHT_MI + LDRSHT_PL + LDRSHT_VS + LDRSHT_VC + LDRSHT_HI + LDRSHT_LS + LDRSHT_GE + LDRSHT_LT + LDRSHT_GT + LDRSHT_LE + LDRSHT + LDRSHT_ZZ + LDRT_EQ + LDRT_NE + LDRT_CS + LDRT_CC + LDRT_MI + LDRT_PL + LDRT_VS + LDRT_VC + LDRT_HI + LDRT_LS + LDRT_GE + LDRT_LT + LDRT_GT + LDRT_LE + LDRT + LDRT_ZZ + LSL_EQ + LSL_NE + LSL_CS + LSL_CC + LSL_MI + LSL_PL + LSL_VS + LSL_VC + LSL_HI + LSL_LS + LSL_GE + LSL_LT + LSL_GT + LSL_LE + LSL + LSL_ZZ + LSL_S_EQ + LSL_S_NE + LSL_S_CS + LSL_S_CC + LSL_S_MI + LSL_S_PL + LSL_S_VS + LSL_S_VC + LSL_S_HI + LSL_S_LS + LSL_S_GE + LSL_S_LT + LSL_S_GT + LSL_S_LE + LSL_S + LSL_S_ZZ + LSR_EQ + LSR_NE + LSR_CS + LSR_CC + LSR_MI + LSR_PL + LSR_VS + LSR_VC + LSR_HI + LSR_LS + LSR_GE + LSR_LT + LSR_GT + LSR_LE + LSR + LSR_ZZ + LSR_S_EQ + LSR_S_NE + LSR_S_CS + LSR_S_CC + LSR_S_MI + LSR_S_PL + LSR_S_VS + LSR_S_VC + LSR_S_HI + LSR_S_LS + LSR_S_GE + LSR_S_LT + LSR_S_GT + LSR_S_LE + LSR_S + LSR_S_ZZ + MLA_EQ + MLA_NE + MLA_CS + MLA_CC + MLA_MI + MLA_PL + MLA_VS + MLA_VC + MLA_HI + MLA_LS + MLA_GE + MLA_LT + MLA_GT + MLA_LE + MLA + MLA_ZZ + MLA_S_EQ + MLA_S_NE + MLA_S_CS + MLA_S_CC + MLA_S_MI + MLA_S_PL + MLA_S_VS + MLA_S_VC + MLA_S_HI + MLA_S_LS + MLA_S_GE + MLA_S_LT + MLA_S_GT + MLA_S_LE + MLA_S + MLA_S_ZZ + MLS_EQ + MLS_NE + MLS_CS + MLS_CC + MLS_MI + MLS_PL + MLS_VS + MLS_VC + MLS_HI + MLS_LS + MLS_GE + MLS_LT + MLS_GT + MLS_LE + MLS + MLS_ZZ + MOV_EQ + MOV_NE + MOV_CS + MOV_CC + MOV_MI + MOV_PL + MOV_VS + MOV_VC + MOV_HI + MOV_LS + MOV_GE + MOV_LT + MOV_GT + MOV_LE + MOV + MOV_ZZ + MOV_S_EQ + MOV_S_NE + MOV_S_CS + MOV_S_CC + MOV_S_MI + MOV_S_PL + MOV_S_VS + MOV_S_VC + MOV_S_HI + MOV_S_LS + MOV_S_GE + MOV_S_LT + MOV_S_GT + MOV_S_LE + MOV_S + MOV_S_ZZ + MOVT_EQ + MOVT_NE + MOVT_CS + MOVT_CC + MOVT_MI + MOVT_PL + MOVT_VS + MOVT_VC + MOVT_HI + MOVT_LS + MOVT_GE + MOVT_LT + MOVT_GT + MOVT_LE + MOVT + MOVT_ZZ + MOVW_EQ + MOVW_NE + MOVW_CS + MOVW_CC + MOVW_MI + MOVW_PL + MOVW_VS + MOVW_VC + MOVW_HI + MOVW_LS + MOVW_GE + MOVW_LT + MOVW_GT + MOVW_LE + MOVW + MOVW_ZZ + MRS_EQ + MRS_NE + MRS_CS + MRS_CC + MRS_MI + MRS_PL + MRS_VS + MRS_VC + MRS_HI + MRS_LS + MRS_GE + MRS_LT + MRS_GT + MRS_LE + MRS + MRS_ZZ + MUL_EQ + MUL_NE + MUL_CS + MUL_CC + MUL_MI + MUL_PL + MUL_VS + MUL_VC + MUL_HI + MUL_LS + MUL_GE + MUL_LT + MUL_GT + MUL_LE + MUL + MUL_ZZ + MUL_S_EQ + MUL_S_NE + MUL_S_CS + MUL_S_CC + MUL_S_MI + MUL_S_PL + MUL_S_VS + MUL_S_VC + MUL_S_HI + MUL_S_LS + MUL_S_GE + MUL_S_LT + MUL_S_GT + MUL_S_LE + MUL_S + MUL_S_ZZ + MVN_EQ + MVN_NE + MVN_CS + MVN_CC + MVN_MI + MVN_PL + MVN_VS + MVN_VC + MVN_HI + MVN_LS + MVN_GE + MVN_LT + MVN_GT + MVN_LE + MVN + MVN_ZZ + MVN_S_EQ + MVN_S_NE + MVN_S_CS + MVN_S_CC + MVN_S_MI + MVN_S_PL + MVN_S_VS + MVN_S_VC + MVN_S_HI + MVN_S_LS + MVN_S_GE + MVN_S_LT + MVN_S_GT + MVN_S_LE + MVN_S + MVN_S_ZZ + NOP_EQ + NOP_NE + NOP_CS + NOP_CC + NOP_MI + NOP_PL + NOP_VS + NOP_VC + NOP_HI + NOP_LS + NOP_GE + NOP_LT + NOP_GT + NOP_LE + NOP + NOP_ZZ + ORR_EQ + ORR_NE + ORR_CS + ORR_CC + ORR_MI + ORR_PL + ORR_VS + ORR_VC + ORR_HI + ORR_LS + ORR_GE + ORR_LT + ORR_GT + ORR_LE + ORR + ORR_ZZ + ORR_S_EQ + ORR_S_NE + ORR_S_CS + ORR_S_CC + ORR_S_MI + ORR_S_PL + ORR_S_VS + ORR_S_VC + ORR_S_HI + ORR_S_LS + ORR_S_GE + ORR_S_LT + ORR_S_GT + ORR_S_LE + ORR_S + ORR_S_ZZ + PKHBT_EQ + PKHBT_NE + PKHBT_CS + PKHBT_CC + PKHBT_MI + PKHBT_PL + PKHBT_VS + PKHBT_VC + PKHBT_HI + PKHBT_LS + PKHBT_GE + PKHBT_LT + PKHBT_GT + PKHBT_LE + PKHBT + PKHBT_ZZ + PKHTB_EQ + PKHTB_NE + PKHTB_CS + PKHTB_CC + PKHTB_MI + PKHTB_PL + PKHTB_VS + PKHTB_VC + PKHTB_HI + PKHTB_LS + PKHTB_GE + PKHTB_LT + PKHTB_GT + PKHTB_LE + PKHTB + PKHTB_ZZ + PLD_W + PLD + PLI + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + POP_EQ + POP_NE + POP_CS + POP_CC + POP_MI + POP_PL + POP_VS + POP_VC + POP_HI + POP_LS + POP_GE + POP_LT + POP_GT + POP_LE + POP + POP_ZZ + PUSH_EQ + PUSH_NE + PUSH_CS + PUSH_CC + PUSH_MI + PUSH_PL + PUSH_VS + PUSH_VC + PUSH_HI + PUSH_LS + PUSH_GE + PUSH_LT + PUSH_GT + PUSH_LE + PUSH + PUSH_ZZ + QADD_EQ + QADD_NE + QADD_CS + QADD_CC + QADD_MI + QADD_PL + QADD_VS + QADD_VC + QADD_HI + QADD_LS + QADD_GE + QADD_LT + QADD_GT + QADD_LE + QADD + QADD_ZZ + QADD16_EQ + QADD16_NE + QADD16_CS + QADD16_CC + QADD16_MI + QADD16_PL + QADD16_VS + QADD16_VC + QADD16_HI + QADD16_LS + QADD16_GE + QADD16_LT + QADD16_GT + QADD16_LE + QADD16 + QADD16_ZZ + QADD8_EQ + QADD8_NE + QADD8_CS + QADD8_CC + QADD8_MI + QADD8_PL + QADD8_VS + QADD8_VC + QADD8_HI + QADD8_LS + QADD8_GE + QADD8_LT + QADD8_GT + QADD8_LE + QADD8 + QADD8_ZZ + QASX_EQ + QASX_NE + QASX_CS + QASX_CC + QASX_MI + QASX_PL + QASX_VS + QASX_VC + QASX_HI + QASX_LS + QASX_GE + QASX_LT + QASX_GT + QASX_LE + QASX + QASX_ZZ + QDADD_EQ + QDADD_NE + QDADD_CS + QDADD_CC + QDADD_MI + QDADD_PL + QDADD_VS + QDADD_VC + QDADD_HI + QDADD_LS + QDADD_GE + QDADD_LT + QDADD_GT + QDADD_LE + QDADD + QDADD_ZZ + QDSUB_EQ + QDSUB_NE + QDSUB_CS + QDSUB_CC + QDSUB_MI + QDSUB_PL + QDSUB_VS + QDSUB_VC + QDSUB_HI + QDSUB_LS + QDSUB_GE + QDSUB_LT + QDSUB_GT + QDSUB_LE + QDSUB + QDSUB_ZZ + QSAX_EQ + QSAX_NE + QSAX_CS + QSAX_CC + QSAX_MI + QSAX_PL + QSAX_VS + QSAX_VC + QSAX_HI + QSAX_LS + QSAX_GE + QSAX_LT + QSAX_GT + QSAX_LE + QSAX + QSAX_ZZ + QSUB_EQ + QSUB_NE + QSUB_CS + QSUB_CC + QSUB_MI + QSUB_PL + QSUB_VS + QSUB_VC + QSUB_HI + QSUB_LS + QSUB_GE + QSUB_LT + QSUB_GT + QSUB_LE + QSUB + QSUB_ZZ + QSUB16_EQ + QSUB16_NE + QSUB16_CS + QSUB16_CC + QSUB16_MI + QSUB16_PL + QSUB16_VS + QSUB16_VC + QSUB16_HI + QSUB16_LS + QSUB16_GE + QSUB16_LT + QSUB16_GT + QSUB16_LE + QSUB16 + QSUB16_ZZ + QSUB8_EQ + QSUB8_NE + QSUB8_CS + QSUB8_CC + QSUB8_MI + QSUB8_PL + QSUB8_VS + QSUB8_VC + QSUB8_HI + QSUB8_LS + QSUB8_GE + QSUB8_LT + QSUB8_GT + QSUB8_LE + QSUB8 + QSUB8_ZZ + RBIT_EQ + RBIT_NE + RBIT_CS + RBIT_CC + RBIT_MI + RBIT_PL + RBIT_VS + RBIT_VC + RBIT_HI + RBIT_LS + RBIT_GE + RBIT_LT + RBIT_GT + RBIT_LE + RBIT + RBIT_ZZ + REV_EQ + REV_NE + REV_CS + REV_CC + REV_MI + REV_PL + REV_VS + REV_VC + REV_HI + REV_LS + REV_GE + REV_LT + REV_GT + REV_LE + REV + REV_ZZ + REV16_EQ + REV16_NE + REV16_CS + REV16_CC + REV16_MI + REV16_PL + REV16_VS + REV16_VC + REV16_HI + REV16_LS + REV16_GE + REV16_LT + REV16_GT + REV16_LE + REV16 + REV16_ZZ + REVSH_EQ + REVSH_NE + REVSH_CS + REVSH_CC + REVSH_MI + REVSH_PL + REVSH_VS + REVSH_VC + REVSH_HI + REVSH_LS + REVSH_GE + REVSH_LT + REVSH_GT + REVSH_LE + REVSH + REVSH_ZZ + ROR_EQ + ROR_NE + ROR_CS + ROR_CC + ROR_MI + ROR_PL + ROR_VS + ROR_VC + ROR_HI + ROR_LS + ROR_GE + ROR_LT + ROR_GT + ROR_LE + ROR + ROR_ZZ + ROR_S_EQ + ROR_S_NE + ROR_S_CS + ROR_S_CC + ROR_S_MI + ROR_S_PL + ROR_S_VS + ROR_S_VC + ROR_S_HI + ROR_S_LS + ROR_S_GE + ROR_S_LT + ROR_S_GT + ROR_S_LE + ROR_S + ROR_S_ZZ + RRX_EQ + RRX_NE + RRX_CS + RRX_CC + RRX_MI + RRX_PL + RRX_VS + RRX_VC + RRX_HI + RRX_LS + RRX_GE + RRX_LT + RRX_GT + RRX_LE + RRX + RRX_ZZ + RRX_S_EQ + RRX_S_NE + RRX_S_CS + RRX_S_CC + RRX_S_MI + RRX_S_PL + RRX_S_VS + RRX_S_VC + RRX_S_HI + RRX_S_LS + RRX_S_GE + RRX_S_LT + RRX_S_GT + RRX_S_LE + RRX_S + RRX_S_ZZ + RSB_EQ + RSB_NE + RSB_CS + RSB_CC + RSB_MI + RSB_PL + RSB_VS + RSB_VC + RSB_HI + RSB_LS + RSB_GE + RSB_LT + RSB_GT + RSB_LE + RSB + RSB_ZZ + RSB_S_EQ + RSB_S_NE + RSB_S_CS + RSB_S_CC + RSB_S_MI + RSB_S_PL + RSB_S_VS + RSB_S_VC + RSB_S_HI + RSB_S_LS + RSB_S_GE + RSB_S_LT + RSB_S_GT + RSB_S_LE + RSB_S + RSB_S_ZZ + RSC_EQ + RSC_NE + RSC_CS + RSC_CC + RSC_MI + RSC_PL + RSC_VS + RSC_VC + RSC_HI + RSC_LS + RSC_GE + RSC_LT + RSC_GT + RSC_LE + RSC + RSC_ZZ + RSC_S_EQ + RSC_S_NE + RSC_S_CS + RSC_S_CC + RSC_S_MI + RSC_S_PL + RSC_S_VS + RSC_S_VC + RSC_S_HI + RSC_S_LS + RSC_S_GE + RSC_S_LT + RSC_S_GT + RSC_S_LE + RSC_S + RSC_S_ZZ + SADD16_EQ + SADD16_NE + SADD16_CS + SADD16_CC + SADD16_MI + SADD16_PL + SADD16_VS + SADD16_VC + SADD16_HI + SADD16_LS + SADD16_GE + SADD16_LT + SADD16_GT + SADD16_LE + SADD16 + SADD16_ZZ + SADD8_EQ + SADD8_NE + SADD8_CS + SADD8_CC + SADD8_MI + SADD8_PL + SADD8_VS + SADD8_VC + SADD8_HI + SADD8_LS + SADD8_GE + SADD8_LT + SADD8_GT + SADD8_LE + SADD8 + SADD8_ZZ + SASX_EQ + SASX_NE + SASX_CS + SASX_CC + SASX_MI + SASX_PL + SASX_VS + SASX_VC + SASX_HI + SASX_LS + SASX_GE + SASX_LT + SASX_GT + SASX_LE + SASX + SASX_ZZ + SBC_EQ + SBC_NE + SBC_CS + SBC_CC + SBC_MI + SBC_PL + SBC_VS + SBC_VC + SBC_HI + SBC_LS + SBC_GE + SBC_LT + SBC_GT + SBC_LE + SBC + SBC_ZZ + SBC_S_EQ + SBC_S_NE + SBC_S_CS + SBC_S_CC + SBC_S_MI + SBC_S_PL + SBC_S_VS + SBC_S_VC + SBC_S_HI + SBC_S_LS + SBC_S_GE + SBC_S_LT + SBC_S_GT + SBC_S_LE + SBC_S + SBC_S_ZZ + SBFX_EQ + SBFX_NE + SBFX_CS + SBFX_CC + SBFX_MI + SBFX_PL + SBFX_VS + SBFX_VC + SBFX_HI + SBFX_LS + SBFX_GE + SBFX_LT + SBFX_GT + SBFX_LE + SBFX + SBFX_ZZ + SEL_EQ + SEL_NE + SEL_CS + SEL_CC + SEL_MI + SEL_PL + SEL_VS + SEL_VC + SEL_HI + SEL_LS + SEL_GE + SEL_LT + SEL_GT + SEL_LE + SEL + SEL_ZZ + SETEND + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + SEV_EQ + SEV_NE + SEV_CS + SEV_CC + SEV_MI + SEV_PL + SEV_VS + SEV_VC + SEV_HI + SEV_LS + SEV_GE + SEV_LT + SEV_GT + SEV_LE + SEV + SEV_ZZ + SHADD16_EQ + SHADD16_NE + SHADD16_CS + SHADD16_CC + SHADD16_MI + SHADD16_PL + SHADD16_VS + SHADD16_VC + SHADD16_HI + SHADD16_LS + SHADD16_GE + SHADD16_LT + SHADD16_GT + SHADD16_LE + SHADD16 + SHADD16_ZZ + SHADD8_EQ + SHADD8_NE + SHADD8_CS + SHADD8_CC + SHADD8_MI + SHADD8_PL + SHADD8_VS + SHADD8_VC + SHADD8_HI + SHADD8_LS + SHADD8_GE + SHADD8_LT + SHADD8_GT + SHADD8_LE + SHADD8 + SHADD8_ZZ + SHASX_EQ + SHASX_NE + SHASX_CS + SHASX_CC + SHASX_MI + SHASX_PL + SHASX_VS + SHASX_VC + SHASX_HI + SHASX_LS + SHASX_GE + SHASX_LT + SHASX_GT + SHASX_LE + SHASX + SHASX_ZZ + SHSAX_EQ + SHSAX_NE + SHSAX_CS + SHSAX_CC + SHSAX_MI + SHSAX_PL + SHSAX_VS + SHSAX_VC + SHSAX_HI + SHSAX_LS + SHSAX_GE + SHSAX_LT + SHSAX_GT + SHSAX_LE + SHSAX + SHSAX_ZZ + SHSUB16_EQ + SHSUB16_NE + SHSUB16_CS + SHSUB16_CC + SHSUB16_MI + SHSUB16_PL + SHSUB16_VS + SHSUB16_VC + SHSUB16_HI + SHSUB16_LS + SHSUB16_GE + SHSUB16_LT + SHSUB16_GT + SHSUB16_LE + SHSUB16 + SHSUB16_ZZ + SHSUB8_EQ + SHSUB8_NE + SHSUB8_CS + SHSUB8_CC + SHSUB8_MI + SHSUB8_PL + SHSUB8_VS + SHSUB8_VC + SHSUB8_HI + SHSUB8_LS + SHSUB8_GE + SHSUB8_LT + SHSUB8_GT + SHSUB8_LE + SHSUB8 + SHSUB8_ZZ + SMLABB_EQ + SMLABB_NE + SMLABB_CS + SMLABB_CC + SMLABB_MI + SMLABB_PL + SMLABB_VS + SMLABB_VC + SMLABB_HI + SMLABB_LS + SMLABB_GE + SMLABB_LT + SMLABB_GT + SMLABB_LE + SMLABB + SMLABB_ZZ + SMLABT_EQ + SMLABT_NE + SMLABT_CS + SMLABT_CC + SMLABT_MI + SMLABT_PL + SMLABT_VS + SMLABT_VC + SMLABT_HI + SMLABT_LS + SMLABT_GE + SMLABT_LT + SMLABT_GT + SMLABT_LE + SMLABT + SMLABT_ZZ + SMLATB_EQ + SMLATB_NE + SMLATB_CS + SMLATB_CC + SMLATB_MI + SMLATB_PL + SMLATB_VS + SMLATB_VC + SMLATB_HI + SMLATB_LS + SMLATB_GE + SMLATB_LT + SMLATB_GT + SMLATB_LE + SMLATB + SMLATB_ZZ + SMLATT_EQ + SMLATT_NE + SMLATT_CS + SMLATT_CC + SMLATT_MI + SMLATT_PL + SMLATT_VS + SMLATT_VC + SMLATT_HI + SMLATT_LS + SMLATT_GE + SMLATT_LT + SMLATT_GT + SMLATT_LE + SMLATT + SMLATT_ZZ + SMLAD_EQ + SMLAD_NE + SMLAD_CS + SMLAD_CC + SMLAD_MI + SMLAD_PL + SMLAD_VS + SMLAD_VC + SMLAD_HI + SMLAD_LS + SMLAD_GE + SMLAD_LT + SMLAD_GT + SMLAD_LE + SMLAD + SMLAD_ZZ + SMLAD_X_EQ + SMLAD_X_NE + SMLAD_X_CS + SMLAD_X_CC + SMLAD_X_MI + SMLAD_X_PL + SMLAD_X_VS + SMLAD_X_VC + SMLAD_X_HI + SMLAD_X_LS + SMLAD_X_GE + SMLAD_X_LT + SMLAD_X_GT + SMLAD_X_LE + SMLAD_X + SMLAD_X_ZZ + SMLAL_EQ + SMLAL_NE + SMLAL_CS + SMLAL_CC + SMLAL_MI + SMLAL_PL + SMLAL_VS + SMLAL_VC + SMLAL_HI + SMLAL_LS + SMLAL_GE + SMLAL_LT + SMLAL_GT + SMLAL_LE + SMLAL + SMLAL_ZZ + SMLAL_S_EQ + SMLAL_S_NE + SMLAL_S_CS + SMLAL_S_CC + SMLAL_S_MI + SMLAL_S_PL + SMLAL_S_VS + SMLAL_S_VC + SMLAL_S_HI + SMLAL_S_LS + SMLAL_S_GE + SMLAL_S_LT + SMLAL_S_GT + SMLAL_S_LE + SMLAL_S + SMLAL_S_ZZ + SMLALBB_EQ + SMLALBB_NE + SMLALBB_CS + SMLALBB_CC + SMLALBB_MI + SMLALBB_PL + SMLALBB_VS + SMLALBB_VC + SMLALBB_HI + SMLALBB_LS + SMLALBB_GE + SMLALBB_LT + SMLALBB_GT + SMLALBB_LE + SMLALBB + SMLALBB_ZZ + SMLALBT_EQ + SMLALBT_NE + SMLALBT_CS + SMLALBT_CC + SMLALBT_MI + SMLALBT_PL + SMLALBT_VS + SMLALBT_VC + SMLALBT_HI + SMLALBT_LS + SMLALBT_GE + SMLALBT_LT + SMLALBT_GT + SMLALBT_LE + SMLALBT + SMLALBT_ZZ + SMLALTB_EQ + SMLALTB_NE + SMLALTB_CS + SMLALTB_CC + SMLALTB_MI + SMLALTB_PL + SMLALTB_VS + SMLALTB_VC + SMLALTB_HI + SMLALTB_LS + SMLALTB_GE + SMLALTB_LT + SMLALTB_GT + SMLALTB_LE + SMLALTB + SMLALTB_ZZ + SMLALTT_EQ + SMLALTT_NE + SMLALTT_CS + SMLALTT_CC + SMLALTT_MI + SMLALTT_PL + SMLALTT_VS + SMLALTT_VC + SMLALTT_HI + SMLALTT_LS + SMLALTT_GE + SMLALTT_LT + SMLALTT_GT + SMLALTT_LE + SMLALTT + SMLALTT_ZZ + SMLALD_EQ + SMLALD_NE + SMLALD_CS + SMLALD_CC + SMLALD_MI + SMLALD_PL + SMLALD_VS + SMLALD_VC + SMLALD_HI + SMLALD_LS + SMLALD_GE + SMLALD_LT + SMLALD_GT + SMLALD_LE + SMLALD + SMLALD_ZZ + SMLALD_X_EQ + SMLALD_X_NE + SMLALD_X_CS + SMLALD_X_CC + SMLALD_X_MI + SMLALD_X_PL + SMLALD_X_VS + SMLALD_X_VC + SMLALD_X_HI + SMLALD_X_LS + SMLALD_X_GE + SMLALD_X_LT + SMLALD_X_GT + SMLALD_X_LE + SMLALD_X + SMLALD_X_ZZ + SMLAWB_EQ + SMLAWB_NE + SMLAWB_CS + SMLAWB_CC + SMLAWB_MI + SMLAWB_PL + SMLAWB_VS + SMLAWB_VC + SMLAWB_HI + SMLAWB_LS + SMLAWB_GE + SMLAWB_LT + SMLAWB_GT + SMLAWB_LE + SMLAWB + SMLAWB_ZZ + SMLAWT_EQ + SMLAWT_NE + SMLAWT_CS + SMLAWT_CC + SMLAWT_MI + SMLAWT_PL + SMLAWT_VS + SMLAWT_VC + SMLAWT_HI + SMLAWT_LS + SMLAWT_GE + SMLAWT_LT + SMLAWT_GT + SMLAWT_LE + SMLAWT + SMLAWT_ZZ + SMLSD_EQ + SMLSD_NE + SMLSD_CS + SMLSD_CC + SMLSD_MI + SMLSD_PL + SMLSD_VS + SMLSD_VC + SMLSD_HI + SMLSD_LS + SMLSD_GE + SMLSD_LT + SMLSD_GT + SMLSD_LE + SMLSD + SMLSD_ZZ + SMLSD_X_EQ + SMLSD_X_NE + SMLSD_X_CS + SMLSD_X_CC + SMLSD_X_MI + SMLSD_X_PL + SMLSD_X_VS + SMLSD_X_VC + SMLSD_X_HI + SMLSD_X_LS + SMLSD_X_GE + SMLSD_X_LT + SMLSD_X_GT + SMLSD_X_LE + SMLSD_X + SMLSD_X_ZZ + SMLSLD_EQ + SMLSLD_NE + SMLSLD_CS + SMLSLD_CC + SMLSLD_MI + SMLSLD_PL + SMLSLD_VS + SMLSLD_VC + SMLSLD_HI + SMLSLD_LS + SMLSLD_GE + SMLSLD_LT + SMLSLD_GT + SMLSLD_LE + SMLSLD + SMLSLD_ZZ + SMLSLD_X_EQ + SMLSLD_X_NE + SMLSLD_X_CS + SMLSLD_X_CC + SMLSLD_X_MI + SMLSLD_X_PL + SMLSLD_X_VS + SMLSLD_X_VC + SMLSLD_X_HI + SMLSLD_X_LS + SMLSLD_X_GE + SMLSLD_X_LT + SMLSLD_X_GT + SMLSLD_X_LE + SMLSLD_X + SMLSLD_X_ZZ + SMMLA_EQ + SMMLA_NE + SMMLA_CS + SMMLA_CC + SMMLA_MI + SMMLA_PL + SMMLA_VS + SMMLA_VC + SMMLA_HI + SMMLA_LS + SMMLA_GE + SMMLA_LT + SMMLA_GT + SMMLA_LE + SMMLA + SMMLA_ZZ + SMMLA_R_EQ + SMMLA_R_NE + SMMLA_R_CS + SMMLA_R_CC + SMMLA_R_MI + SMMLA_R_PL + SMMLA_R_VS + SMMLA_R_VC + SMMLA_R_HI + SMMLA_R_LS + SMMLA_R_GE + SMMLA_R_LT + SMMLA_R_GT + SMMLA_R_LE + SMMLA_R + SMMLA_R_ZZ + SMMLS_EQ + SMMLS_NE + SMMLS_CS + SMMLS_CC + SMMLS_MI + SMMLS_PL + SMMLS_VS + SMMLS_VC + SMMLS_HI + SMMLS_LS + SMMLS_GE + SMMLS_LT + SMMLS_GT + SMMLS_LE + SMMLS + SMMLS_ZZ + SMMLS_R_EQ + SMMLS_R_NE + SMMLS_R_CS + SMMLS_R_CC + SMMLS_R_MI + SMMLS_R_PL + SMMLS_R_VS + SMMLS_R_VC + SMMLS_R_HI + SMMLS_R_LS + SMMLS_R_GE + SMMLS_R_LT + SMMLS_R_GT + SMMLS_R_LE + SMMLS_R + SMMLS_R_ZZ + SMMUL_EQ + SMMUL_NE + SMMUL_CS + SMMUL_CC + SMMUL_MI + SMMUL_PL + SMMUL_VS + SMMUL_VC + SMMUL_HI + SMMUL_LS + SMMUL_GE + SMMUL_LT + SMMUL_GT + SMMUL_LE + SMMUL + SMMUL_ZZ + SMMUL_R_EQ + SMMUL_R_NE + SMMUL_R_CS + SMMUL_R_CC + SMMUL_R_MI + SMMUL_R_PL + SMMUL_R_VS + SMMUL_R_VC + SMMUL_R_HI + SMMUL_R_LS + SMMUL_R_GE + SMMUL_R_LT + SMMUL_R_GT + SMMUL_R_LE + SMMUL_R + SMMUL_R_ZZ + SMUAD_EQ + SMUAD_NE + SMUAD_CS + SMUAD_CC + SMUAD_MI + SMUAD_PL + SMUAD_VS + SMUAD_VC + SMUAD_HI + SMUAD_LS + SMUAD_GE + SMUAD_LT + SMUAD_GT + SMUAD_LE + SMUAD + SMUAD_ZZ + SMUAD_X_EQ + SMUAD_X_NE + SMUAD_X_CS + SMUAD_X_CC + SMUAD_X_MI + SMUAD_X_PL + SMUAD_X_VS + SMUAD_X_VC + SMUAD_X_HI + SMUAD_X_LS + SMUAD_X_GE + SMUAD_X_LT + SMUAD_X_GT + SMUAD_X_LE + SMUAD_X + SMUAD_X_ZZ + SMULBB_EQ + SMULBB_NE + SMULBB_CS + SMULBB_CC + SMULBB_MI + SMULBB_PL + SMULBB_VS + SMULBB_VC + SMULBB_HI + SMULBB_LS + SMULBB_GE + SMULBB_LT + SMULBB_GT + SMULBB_LE + SMULBB + SMULBB_ZZ + SMULBT_EQ + SMULBT_NE + SMULBT_CS + SMULBT_CC + SMULBT_MI + SMULBT_PL + SMULBT_VS + SMULBT_VC + SMULBT_HI + SMULBT_LS + SMULBT_GE + SMULBT_LT + SMULBT_GT + SMULBT_LE + SMULBT + SMULBT_ZZ + SMULTB_EQ + SMULTB_NE + SMULTB_CS + SMULTB_CC + SMULTB_MI + SMULTB_PL + SMULTB_VS + SMULTB_VC + SMULTB_HI + SMULTB_LS + SMULTB_GE + SMULTB_LT + SMULTB_GT + SMULTB_LE + SMULTB + SMULTB_ZZ + SMULTT_EQ + SMULTT_NE + SMULTT_CS + SMULTT_CC + SMULTT_MI + SMULTT_PL + SMULTT_VS + SMULTT_VC + SMULTT_HI + SMULTT_LS + SMULTT_GE + SMULTT_LT + SMULTT_GT + SMULTT_LE + SMULTT + SMULTT_ZZ + SMULL_EQ + SMULL_NE + SMULL_CS + SMULL_CC + SMULL_MI + SMULL_PL + SMULL_VS + SMULL_VC + SMULL_HI + SMULL_LS + SMULL_GE + SMULL_LT + SMULL_GT + SMULL_LE + SMULL + SMULL_ZZ + SMULL_S_EQ + SMULL_S_NE + SMULL_S_CS + SMULL_S_CC + SMULL_S_MI + SMULL_S_PL + SMULL_S_VS + SMULL_S_VC + SMULL_S_HI + SMULL_S_LS + SMULL_S_GE + SMULL_S_LT + SMULL_S_GT + SMULL_S_LE + SMULL_S + SMULL_S_ZZ + SMULWB_EQ + SMULWB_NE + SMULWB_CS + SMULWB_CC + SMULWB_MI + SMULWB_PL + SMULWB_VS + SMULWB_VC + SMULWB_HI + SMULWB_LS + SMULWB_GE + SMULWB_LT + SMULWB_GT + SMULWB_LE + SMULWB + SMULWB_ZZ + SMULWT_EQ + SMULWT_NE + SMULWT_CS + SMULWT_CC + SMULWT_MI + SMULWT_PL + SMULWT_VS + SMULWT_VC + SMULWT_HI + SMULWT_LS + SMULWT_GE + SMULWT_LT + SMULWT_GT + SMULWT_LE + SMULWT + SMULWT_ZZ + SMUSD_EQ + SMUSD_NE + SMUSD_CS + SMUSD_CC + SMUSD_MI + SMUSD_PL + SMUSD_VS + SMUSD_VC + SMUSD_HI + SMUSD_LS + SMUSD_GE + SMUSD_LT + SMUSD_GT + SMUSD_LE + SMUSD + SMUSD_ZZ + SMUSD_X_EQ + SMUSD_X_NE + SMUSD_X_CS + SMUSD_X_CC + SMUSD_X_MI + SMUSD_X_PL + SMUSD_X_VS + SMUSD_X_VC + SMUSD_X_HI + SMUSD_X_LS + SMUSD_X_GE + SMUSD_X_LT + SMUSD_X_GT + SMUSD_X_LE + SMUSD_X + SMUSD_X_ZZ + SSAT_EQ + SSAT_NE + SSAT_CS + SSAT_CC + SSAT_MI + SSAT_PL + SSAT_VS + SSAT_VC + SSAT_HI + SSAT_LS + SSAT_GE + SSAT_LT + SSAT_GT + SSAT_LE + SSAT + SSAT_ZZ + SSAT16_EQ + SSAT16_NE + SSAT16_CS + SSAT16_CC + SSAT16_MI + SSAT16_PL + SSAT16_VS + SSAT16_VC + SSAT16_HI + SSAT16_LS + SSAT16_GE + SSAT16_LT + SSAT16_GT + SSAT16_LE + SSAT16 + SSAT16_ZZ + SSAX_EQ + SSAX_NE + SSAX_CS + SSAX_CC + SSAX_MI + SSAX_PL + SSAX_VS + SSAX_VC + SSAX_HI + SSAX_LS + SSAX_GE + SSAX_LT + SSAX_GT + SSAX_LE + SSAX + SSAX_ZZ + SSUB16_EQ + SSUB16_NE + SSUB16_CS + SSUB16_CC + SSUB16_MI + SSUB16_PL + SSUB16_VS + SSUB16_VC + SSUB16_HI + SSUB16_LS + SSUB16_GE + SSUB16_LT + SSUB16_GT + SSUB16_LE + SSUB16 + SSUB16_ZZ + SSUB8_EQ + SSUB8_NE + SSUB8_CS + SSUB8_CC + SSUB8_MI + SSUB8_PL + SSUB8_VS + SSUB8_VC + SSUB8_HI + SSUB8_LS + SSUB8_GE + SSUB8_LT + SSUB8_GT + SSUB8_LE + SSUB8 + SSUB8_ZZ + STM_EQ + STM_NE + STM_CS + STM_CC + STM_MI + STM_PL + STM_VS + STM_VC + STM_HI + STM_LS + STM_GE + STM_LT + STM_GT + STM_LE + STM + STM_ZZ + STMDA_EQ + STMDA_NE + STMDA_CS + STMDA_CC + STMDA_MI + STMDA_PL + STMDA_VS + STMDA_VC + STMDA_HI + STMDA_LS + STMDA_GE + STMDA_LT + STMDA_GT + STMDA_LE + STMDA + STMDA_ZZ + STMDB_EQ + STMDB_NE + STMDB_CS + STMDB_CC + STMDB_MI + STMDB_PL + STMDB_VS + STMDB_VC + STMDB_HI + STMDB_LS + STMDB_GE + STMDB_LT + STMDB_GT + STMDB_LE + STMDB + STMDB_ZZ + STMIB_EQ + STMIB_NE + STMIB_CS + STMIB_CC + STMIB_MI + STMIB_PL + STMIB_VS + STMIB_VC + STMIB_HI + STMIB_LS + STMIB_GE + STMIB_LT + STMIB_GT + STMIB_LE + STMIB + STMIB_ZZ + STR_EQ + STR_NE + STR_CS + STR_CC + STR_MI + STR_PL + STR_VS + STR_VC + STR_HI + STR_LS + STR_GE + STR_LT + STR_GT + STR_LE + STR + STR_ZZ + STRB_EQ + STRB_NE + STRB_CS + STRB_CC + STRB_MI + STRB_PL + STRB_VS + STRB_VC + STRB_HI + STRB_LS + STRB_GE + STRB_LT + STRB_GT + STRB_LE + STRB + STRB_ZZ + STRBT_EQ + STRBT_NE + STRBT_CS + STRBT_CC + STRBT_MI + STRBT_PL + STRBT_VS + STRBT_VC + STRBT_HI + STRBT_LS + STRBT_GE + STRBT_LT + STRBT_GT + STRBT_LE + STRBT + STRBT_ZZ + STRD_EQ + STRD_NE + STRD_CS + STRD_CC + STRD_MI + STRD_PL + STRD_VS + STRD_VC + STRD_HI + STRD_LS + STRD_GE + STRD_LT + STRD_GT + STRD_LE + STRD + STRD_ZZ + STREX_EQ + STREX_NE + STREX_CS + STREX_CC + STREX_MI + STREX_PL + STREX_VS + STREX_VC + STREX_HI + STREX_LS + STREX_GE + STREX_LT + STREX_GT + STREX_LE + STREX + STREX_ZZ + STREXB_EQ + STREXB_NE + STREXB_CS + STREXB_CC + STREXB_MI + STREXB_PL + STREXB_VS + STREXB_VC + STREXB_HI + STREXB_LS + STREXB_GE + STREXB_LT + STREXB_GT + STREXB_LE + STREXB + STREXB_ZZ + STREXD_EQ + STREXD_NE + STREXD_CS + STREXD_CC + STREXD_MI + STREXD_PL + STREXD_VS + STREXD_VC + STREXD_HI + STREXD_LS + STREXD_GE + STREXD_LT + STREXD_GT + STREXD_LE + STREXD + STREXD_ZZ + STREXH_EQ + STREXH_NE + STREXH_CS + STREXH_CC + STREXH_MI + STREXH_PL + STREXH_VS + STREXH_VC + STREXH_HI + STREXH_LS + STREXH_GE + STREXH_LT + STREXH_GT + STREXH_LE + STREXH + STREXH_ZZ + STRH_EQ + STRH_NE + STRH_CS + STRH_CC + STRH_MI + STRH_PL + STRH_VS + STRH_VC + STRH_HI + STRH_LS + STRH_GE + STRH_LT + STRH_GT + STRH_LE + STRH + STRH_ZZ + STRHT_EQ + STRHT_NE + STRHT_CS + STRHT_CC + STRHT_MI + STRHT_PL + STRHT_VS + STRHT_VC + STRHT_HI + STRHT_LS + STRHT_GE + STRHT_LT + STRHT_GT + STRHT_LE + STRHT + STRHT_ZZ + STRT_EQ + STRT_NE + STRT_CS + STRT_CC + STRT_MI + STRT_PL + STRT_VS + STRT_VC + STRT_HI + STRT_LS + STRT_GE + STRT_LT + STRT_GT + STRT_LE + STRT + STRT_ZZ + SUB_EQ + SUB_NE + SUB_CS + SUB_CC + SUB_MI + SUB_PL + SUB_VS + SUB_VC + SUB_HI + SUB_LS + SUB_GE + SUB_LT + SUB_GT + SUB_LE + SUB + SUB_ZZ + SUB_S_EQ + SUB_S_NE + SUB_S_CS + SUB_S_CC + SUB_S_MI + SUB_S_PL + SUB_S_VS + SUB_S_VC + SUB_S_HI + SUB_S_LS + SUB_S_GE + SUB_S_LT + SUB_S_GT + SUB_S_LE + SUB_S + SUB_S_ZZ + SVC_EQ + SVC_NE + SVC_CS + SVC_CC + SVC_MI + SVC_PL + SVC_VS + SVC_VC + SVC_HI + SVC_LS + SVC_GE + SVC_LT + SVC_GT + SVC_LE + SVC + SVC_ZZ + SWP_EQ + SWP_NE + SWP_CS + SWP_CC + SWP_MI + SWP_PL + SWP_VS + SWP_VC + SWP_HI + SWP_LS + SWP_GE + SWP_LT + SWP_GT + SWP_LE + SWP + SWP_ZZ + SWP_B_EQ + SWP_B_NE + SWP_B_CS + SWP_B_CC + SWP_B_MI + SWP_B_PL + SWP_B_VS + SWP_B_VC + SWP_B_HI + SWP_B_LS + SWP_B_GE + SWP_B_LT + SWP_B_GT + SWP_B_LE + SWP_B + SWP_B_ZZ + SXTAB_EQ + SXTAB_NE + SXTAB_CS + SXTAB_CC + SXTAB_MI + SXTAB_PL + SXTAB_VS + SXTAB_VC + SXTAB_HI + SXTAB_LS + SXTAB_GE + SXTAB_LT + SXTAB_GT + SXTAB_LE + SXTAB + SXTAB_ZZ + SXTAB16_EQ + SXTAB16_NE + SXTAB16_CS + SXTAB16_CC + SXTAB16_MI + SXTAB16_PL + SXTAB16_VS + SXTAB16_VC + SXTAB16_HI + SXTAB16_LS + SXTAB16_GE + SXTAB16_LT + SXTAB16_GT + SXTAB16_LE + SXTAB16 + SXTAB16_ZZ + SXTAH_EQ + SXTAH_NE + SXTAH_CS + SXTAH_CC + SXTAH_MI + SXTAH_PL + SXTAH_VS + SXTAH_VC + SXTAH_HI + SXTAH_LS + SXTAH_GE + SXTAH_LT + SXTAH_GT + SXTAH_LE + SXTAH + SXTAH_ZZ + SXTB_EQ + SXTB_NE + SXTB_CS + SXTB_CC + SXTB_MI + SXTB_PL + SXTB_VS + SXTB_VC + SXTB_HI + SXTB_LS + SXTB_GE + SXTB_LT + SXTB_GT + SXTB_LE + SXTB + SXTB_ZZ + SXTB16_EQ + SXTB16_NE + SXTB16_CS + SXTB16_CC + SXTB16_MI + SXTB16_PL + SXTB16_VS + SXTB16_VC + SXTB16_HI + SXTB16_LS + SXTB16_GE + SXTB16_LT + SXTB16_GT + SXTB16_LE + SXTB16 + SXTB16_ZZ + SXTH_EQ + SXTH_NE + SXTH_CS + SXTH_CC + SXTH_MI + SXTH_PL + SXTH_VS + SXTH_VC + SXTH_HI + SXTH_LS + SXTH_GE + SXTH_LT + SXTH_GT + SXTH_LE + SXTH + SXTH_ZZ + TEQ_EQ + TEQ_NE + TEQ_CS + TEQ_CC + TEQ_MI + TEQ_PL + TEQ_VS + TEQ_VC + TEQ_HI + TEQ_LS + TEQ_GE + TEQ_LT + TEQ_GT + TEQ_LE + TEQ + TEQ_ZZ + TST_EQ + TST_NE + TST_CS + TST_CC + TST_MI + TST_PL + TST_VS + TST_VC + TST_HI + TST_LS + TST_GE + TST_LT + TST_GT + TST_LE + TST + TST_ZZ + UADD16_EQ + UADD16_NE + UADD16_CS + UADD16_CC + UADD16_MI + UADD16_PL + UADD16_VS + UADD16_VC + UADD16_HI + UADD16_LS + UADD16_GE + UADD16_LT + UADD16_GT + UADD16_LE + UADD16 + UADD16_ZZ + UADD8_EQ + UADD8_NE + UADD8_CS + UADD8_CC + UADD8_MI + UADD8_PL + UADD8_VS + UADD8_VC + UADD8_HI + UADD8_LS + UADD8_GE + UADD8_LT + UADD8_GT + UADD8_LE + UADD8 + UADD8_ZZ + UASX_EQ + UASX_NE + UASX_CS + UASX_CC + UASX_MI + UASX_PL + UASX_VS + UASX_VC + UASX_HI + UASX_LS + UASX_GE + UASX_LT + UASX_GT + UASX_LE + UASX + UASX_ZZ + UBFX_EQ + UBFX_NE + UBFX_CS + UBFX_CC + UBFX_MI + UBFX_PL + UBFX_VS + UBFX_VC + UBFX_HI + UBFX_LS + UBFX_GE + UBFX_LT + UBFX_GT + UBFX_LE + UBFX + UBFX_ZZ + UHADD16_EQ + UHADD16_NE + UHADD16_CS + UHADD16_CC + UHADD16_MI + UHADD16_PL + UHADD16_VS + UHADD16_VC + UHADD16_HI + UHADD16_LS + UHADD16_GE + UHADD16_LT + UHADD16_GT + UHADD16_LE + UHADD16 + UHADD16_ZZ + UHADD8_EQ + UHADD8_NE + UHADD8_CS + UHADD8_CC + UHADD8_MI + UHADD8_PL + UHADD8_VS + UHADD8_VC + UHADD8_HI + UHADD8_LS + UHADD8_GE + UHADD8_LT + UHADD8_GT + UHADD8_LE + UHADD8 + UHADD8_ZZ + UHASX_EQ + UHASX_NE + UHASX_CS + UHASX_CC + UHASX_MI + UHASX_PL + UHASX_VS + UHASX_VC + UHASX_HI + UHASX_LS + UHASX_GE + UHASX_LT + UHASX_GT + UHASX_LE + UHASX + UHASX_ZZ + UHSAX_EQ + UHSAX_NE + UHSAX_CS + UHSAX_CC + UHSAX_MI + UHSAX_PL + UHSAX_VS + UHSAX_VC + UHSAX_HI + UHSAX_LS + UHSAX_GE + UHSAX_LT + UHSAX_GT + UHSAX_LE + UHSAX + UHSAX_ZZ + UHSUB16_EQ + UHSUB16_NE + UHSUB16_CS + UHSUB16_CC + UHSUB16_MI + UHSUB16_PL + UHSUB16_VS + UHSUB16_VC + UHSUB16_HI + UHSUB16_LS + UHSUB16_GE + UHSUB16_LT + UHSUB16_GT + UHSUB16_LE + UHSUB16 + UHSUB16_ZZ + UHSUB8_EQ + UHSUB8_NE + UHSUB8_CS + UHSUB8_CC + UHSUB8_MI + UHSUB8_PL + UHSUB8_VS + UHSUB8_VC + UHSUB8_HI + UHSUB8_LS + UHSUB8_GE + UHSUB8_LT + UHSUB8_GT + UHSUB8_LE + UHSUB8 + UHSUB8_ZZ + UMAAL_EQ + UMAAL_NE + UMAAL_CS + UMAAL_CC + UMAAL_MI + UMAAL_PL + UMAAL_VS + UMAAL_VC + UMAAL_HI + UMAAL_LS + UMAAL_GE + UMAAL_LT + UMAAL_GT + UMAAL_LE + UMAAL + UMAAL_ZZ + UMLAL_EQ + UMLAL_NE + UMLAL_CS + UMLAL_CC + UMLAL_MI + UMLAL_PL + UMLAL_VS + UMLAL_VC + UMLAL_HI + UMLAL_LS + UMLAL_GE + UMLAL_LT + UMLAL_GT + UMLAL_LE + UMLAL + UMLAL_ZZ + UMLAL_S_EQ + UMLAL_S_NE + UMLAL_S_CS + UMLAL_S_CC + UMLAL_S_MI + UMLAL_S_PL + UMLAL_S_VS + UMLAL_S_VC + UMLAL_S_HI + UMLAL_S_LS + UMLAL_S_GE + UMLAL_S_LT + UMLAL_S_GT + UMLAL_S_LE + UMLAL_S + UMLAL_S_ZZ + UMULL_EQ + UMULL_NE + UMULL_CS + UMULL_CC + UMULL_MI + UMULL_PL + UMULL_VS + UMULL_VC + UMULL_HI + UMULL_LS + UMULL_GE + UMULL_LT + UMULL_GT + UMULL_LE + UMULL + UMULL_ZZ + UMULL_S_EQ + UMULL_S_NE + UMULL_S_CS + UMULL_S_CC + UMULL_S_MI + UMULL_S_PL + UMULL_S_VS + UMULL_S_VC + UMULL_S_HI + UMULL_S_LS + UMULL_S_GE + UMULL_S_LT + UMULL_S_GT + UMULL_S_LE + UMULL_S + UMULL_S_ZZ + UNDEF + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + UQADD16_EQ + UQADD16_NE + UQADD16_CS + UQADD16_CC + UQADD16_MI + UQADD16_PL + UQADD16_VS + UQADD16_VC + UQADD16_HI + UQADD16_LS + UQADD16_GE + UQADD16_LT + UQADD16_GT + UQADD16_LE + UQADD16 + UQADD16_ZZ + UQADD8_EQ + UQADD8_NE + UQADD8_CS + UQADD8_CC + UQADD8_MI + UQADD8_PL + UQADD8_VS + UQADD8_VC + UQADD8_HI + UQADD8_LS + UQADD8_GE + UQADD8_LT + UQADD8_GT + UQADD8_LE + UQADD8 + UQADD8_ZZ + UQASX_EQ + UQASX_NE + UQASX_CS + UQASX_CC + UQASX_MI + UQASX_PL + UQASX_VS + UQASX_VC + UQASX_HI + UQASX_LS + UQASX_GE + UQASX_LT + UQASX_GT + UQASX_LE + UQASX + UQASX_ZZ + UQSAX_EQ + UQSAX_NE + UQSAX_CS + UQSAX_CC + UQSAX_MI + UQSAX_PL + UQSAX_VS + UQSAX_VC + UQSAX_HI + UQSAX_LS + UQSAX_GE + UQSAX_LT + UQSAX_GT + UQSAX_LE + UQSAX + UQSAX_ZZ + UQSUB16_EQ + UQSUB16_NE + UQSUB16_CS + UQSUB16_CC + UQSUB16_MI + UQSUB16_PL + UQSUB16_VS + UQSUB16_VC + UQSUB16_HI + UQSUB16_LS + UQSUB16_GE + UQSUB16_LT + UQSUB16_GT + UQSUB16_LE + UQSUB16 + UQSUB16_ZZ + UQSUB8_EQ + UQSUB8_NE + UQSUB8_CS + UQSUB8_CC + UQSUB8_MI + UQSUB8_PL + UQSUB8_VS + UQSUB8_VC + UQSUB8_HI + UQSUB8_LS + UQSUB8_GE + UQSUB8_LT + UQSUB8_GT + UQSUB8_LE + UQSUB8 + UQSUB8_ZZ + USAD8_EQ + USAD8_NE + USAD8_CS + USAD8_CC + USAD8_MI + USAD8_PL + USAD8_VS + USAD8_VC + USAD8_HI + USAD8_LS + USAD8_GE + USAD8_LT + USAD8_GT + USAD8_LE + USAD8 + USAD8_ZZ + USADA8_EQ + USADA8_NE + USADA8_CS + USADA8_CC + USADA8_MI + USADA8_PL + USADA8_VS + USADA8_VC + USADA8_HI + USADA8_LS + USADA8_GE + USADA8_LT + USADA8_GT + USADA8_LE + USADA8 + USADA8_ZZ + USAT_EQ + USAT_NE + USAT_CS + USAT_CC + USAT_MI + USAT_PL + USAT_VS + USAT_VC + USAT_HI + USAT_LS + USAT_GE + USAT_LT + USAT_GT + USAT_LE + USAT + USAT_ZZ + USAT16_EQ + USAT16_NE + USAT16_CS + USAT16_CC + USAT16_MI + USAT16_PL + USAT16_VS + USAT16_VC + USAT16_HI + USAT16_LS + USAT16_GE + USAT16_LT + USAT16_GT + USAT16_LE + USAT16 + USAT16_ZZ + USAX_EQ + USAX_NE + USAX_CS + USAX_CC + USAX_MI + USAX_PL + USAX_VS + USAX_VC + USAX_HI + USAX_LS + USAX_GE + USAX_LT + USAX_GT + USAX_LE + USAX + USAX_ZZ + USUB16_EQ + USUB16_NE + USUB16_CS + USUB16_CC + USUB16_MI + USUB16_PL + USUB16_VS + USUB16_VC + USUB16_HI + USUB16_LS + USUB16_GE + USUB16_LT + USUB16_GT + USUB16_LE + USUB16 + USUB16_ZZ + USUB8_EQ + USUB8_NE + USUB8_CS + USUB8_CC + USUB8_MI + USUB8_PL + USUB8_VS + USUB8_VC + USUB8_HI + USUB8_LS + USUB8_GE + USUB8_LT + USUB8_GT + USUB8_LE + USUB8 + USUB8_ZZ + UXTAB_EQ + UXTAB_NE + UXTAB_CS + UXTAB_CC + UXTAB_MI + UXTAB_PL + UXTAB_VS + UXTAB_VC + UXTAB_HI + UXTAB_LS + UXTAB_GE + UXTAB_LT + UXTAB_GT + UXTAB_LE + UXTAB + UXTAB_ZZ + UXTAB16_EQ + UXTAB16_NE + UXTAB16_CS + UXTAB16_CC + UXTAB16_MI + UXTAB16_PL + UXTAB16_VS + UXTAB16_VC + UXTAB16_HI + UXTAB16_LS + UXTAB16_GE + UXTAB16_LT + UXTAB16_GT + UXTAB16_LE + UXTAB16 + UXTAB16_ZZ + UXTAH_EQ + UXTAH_NE + UXTAH_CS + UXTAH_CC + UXTAH_MI + UXTAH_PL + UXTAH_VS + UXTAH_VC + UXTAH_HI + UXTAH_LS + UXTAH_GE + UXTAH_LT + UXTAH_GT + UXTAH_LE + UXTAH + UXTAH_ZZ + UXTB_EQ + UXTB_NE + UXTB_CS + UXTB_CC + UXTB_MI + UXTB_PL + UXTB_VS + UXTB_VC + UXTB_HI + UXTB_LS + UXTB_GE + UXTB_LT + UXTB_GT + UXTB_LE + UXTB + UXTB_ZZ + UXTB16_EQ + UXTB16_NE + UXTB16_CS + UXTB16_CC + UXTB16_MI + UXTB16_PL + UXTB16_VS + UXTB16_VC + UXTB16_HI + UXTB16_LS + UXTB16_GE + UXTB16_LT + UXTB16_GT + UXTB16_LE + UXTB16 + UXTB16_ZZ + UXTH_EQ + UXTH_NE + UXTH_CS + UXTH_CC + UXTH_MI + UXTH_PL + UXTH_VS + UXTH_VC + UXTH_HI + UXTH_LS + UXTH_GE + UXTH_LT + UXTH_GT + UXTH_LE + UXTH + UXTH_ZZ + VABS_EQ_F32 + VABS_NE_F32 + VABS_CS_F32 + VABS_CC_F32 + VABS_MI_F32 + VABS_PL_F32 + VABS_VS_F32 + VABS_VC_F32 + VABS_HI_F32 + VABS_LS_F32 + VABS_GE_F32 + VABS_LT_F32 + VABS_GT_F32 + VABS_LE_F32 + VABS_F32 + VABS_ZZ_F32 + VABS_EQ_F64 + VABS_NE_F64 + VABS_CS_F64 + VABS_CC_F64 + VABS_MI_F64 + VABS_PL_F64 + VABS_VS_F64 + VABS_VC_F64 + VABS_HI_F64 + VABS_LS_F64 + VABS_GE_F64 + VABS_LT_F64 + VABS_GT_F64 + VABS_LE_F64 + VABS_F64 + VABS_ZZ_F64 + VADD_EQ_F32 + VADD_NE_F32 + VADD_CS_F32 + VADD_CC_F32 + VADD_MI_F32 + VADD_PL_F32 + VADD_VS_F32 + VADD_VC_F32 + VADD_HI_F32 + VADD_LS_F32 + VADD_GE_F32 + VADD_LT_F32 + VADD_GT_F32 + VADD_LE_F32 + VADD_F32 + VADD_ZZ_F32 + VADD_EQ_F64 + VADD_NE_F64 + VADD_CS_F64 + VADD_CC_F64 + VADD_MI_F64 + VADD_PL_F64 + VADD_VS_F64 + VADD_VC_F64 + VADD_HI_F64 + VADD_LS_F64 + VADD_GE_F64 + VADD_LT_F64 + VADD_GT_F64 + VADD_LE_F64 + VADD_F64 + VADD_ZZ_F64 + VCMP_EQ_F32 + VCMP_NE_F32 + VCMP_CS_F32 + VCMP_CC_F32 + VCMP_MI_F32 + VCMP_PL_F32 + VCMP_VS_F32 + VCMP_VC_F32 + VCMP_HI_F32 + VCMP_LS_F32 + VCMP_GE_F32 + VCMP_LT_F32 + VCMP_GT_F32 + VCMP_LE_F32 + VCMP_F32 + VCMP_ZZ_F32 + VCMP_EQ_F64 + VCMP_NE_F64 + VCMP_CS_F64 + VCMP_CC_F64 + VCMP_MI_F64 + VCMP_PL_F64 + VCMP_VS_F64 + VCMP_VC_F64 + VCMP_HI_F64 + VCMP_LS_F64 + VCMP_GE_F64 + VCMP_LT_F64 + VCMP_GT_F64 + VCMP_LE_F64 + VCMP_F64 + VCMP_ZZ_F64 + VCMP_E_EQ_F32 + VCMP_E_NE_F32 + VCMP_E_CS_F32 + VCMP_E_CC_F32 + VCMP_E_MI_F32 + VCMP_E_PL_F32 + VCMP_E_VS_F32 + VCMP_E_VC_F32 + VCMP_E_HI_F32 + VCMP_E_LS_F32 + VCMP_E_GE_F32 + VCMP_E_LT_F32 + VCMP_E_GT_F32 + VCMP_E_LE_F32 + VCMP_E_F32 + VCMP_E_ZZ_F32 + VCMP_E_EQ_F64 + VCMP_E_NE_F64 + VCMP_E_CS_F64 + VCMP_E_CC_F64 + VCMP_E_MI_F64 + VCMP_E_PL_F64 + VCMP_E_VS_F64 + VCMP_E_VC_F64 + VCMP_E_HI_F64 + VCMP_E_LS_F64 + VCMP_E_GE_F64 + VCMP_E_LT_F64 + VCMP_E_GT_F64 + VCMP_E_LE_F64 + VCMP_E_F64 + VCMP_E_ZZ_F64 + VCVT_EQ_F32_FXS16 + VCVT_NE_F32_FXS16 + VCVT_CS_F32_FXS16 + VCVT_CC_F32_FXS16 + VCVT_MI_F32_FXS16 + VCVT_PL_F32_FXS16 + VCVT_VS_F32_FXS16 + VCVT_VC_F32_FXS16 + VCVT_HI_F32_FXS16 + VCVT_LS_F32_FXS16 + VCVT_GE_F32_FXS16 + VCVT_LT_F32_FXS16 + VCVT_GT_F32_FXS16 + VCVT_LE_F32_FXS16 + VCVT_F32_FXS16 + VCVT_ZZ_F32_FXS16 + VCVT_EQ_F32_FXS32 + VCVT_NE_F32_FXS32 + VCVT_CS_F32_FXS32 + VCVT_CC_F32_FXS32 + VCVT_MI_F32_FXS32 + VCVT_PL_F32_FXS32 + VCVT_VS_F32_FXS32 + VCVT_VC_F32_FXS32 + VCVT_HI_F32_FXS32 + VCVT_LS_F32_FXS32 + VCVT_GE_F32_FXS32 + VCVT_LT_F32_FXS32 + VCVT_GT_F32_FXS32 + VCVT_LE_F32_FXS32 + VCVT_F32_FXS32 + VCVT_ZZ_F32_FXS32 + VCVT_EQ_F32_FXU16 + VCVT_NE_F32_FXU16 + VCVT_CS_F32_FXU16 + VCVT_CC_F32_FXU16 + VCVT_MI_F32_FXU16 + VCVT_PL_F32_FXU16 + VCVT_VS_F32_FXU16 + VCVT_VC_F32_FXU16 + VCVT_HI_F32_FXU16 + VCVT_LS_F32_FXU16 + VCVT_GE_F32_FXU16 + VCVT_LT_F32_FXU16 + VCVT_GT_F32_FXU16 + VCVT_LE_F32_FXU16 + VCVT_F32_FXU16 + VCVT_ZZ_F32_FXU16 + VCVT_EQ_F32_FXU32 + VCVT_NE_F32_FXU32 + VCVT_CS_F32_FXU32 + VCVT_CC_F32_FXU32 + VCVT_MI_F32_FXU32 + VCVT_PL_F32_FXU32 + VCVT_VS_F32_FXU32 + VCVT_VC_F32_FXU32 + VCVT_HI_F32_FXU32 + VCVT_LS_F32_FXU32 + VCVT_GE_F32_FXU32 + VCVT_LT_F32_FXU32 + VCVT_GT_F32_FXU32 + VCVT_LE_F32_FXU32 + VCVT_F32_FXU32 + VCVT_ZZ_F32_FXU32 + VCVT_EQ_F64_FXS16 + VCVT_NE_F64_FXS16 + VCVT_CS_F64_FXS16 + VCVT_CC_F64_FXS16 + VCVT_MI_F64_FXS16 + VCVT_PL_F64_FXS16 + VCVT_VS_F64_FXS16 + VCVT_VC_F64_FXS16 + VCVT_HI_F64_FXS16 + VCVT_LS_F64_FXS16 + VCVT_GE_F64_FXS16 + VCVT_LT_F64_FXS16 + VCVT_GT_F64_FXS16 + VCVT_LE_F64_FXS16 + VCVT_F64_FXS16 + VCVT_ZZ_F64_FXS16 + VCVT_EQ_F64_FXS32 + VCVT_NE_F64_FXS32 + VCVT_CS_F64_FXS32 + VCVT_CC_F64_FXS32 + VCVT_MI_F64_FXS32 + VCVT_PL_F64_FXS32 + VCVT_VS_F64_FXS32 + VCVT_VC_F64_FXS32 + VCVT_HI_F64_FXS32 + VCVT_LS_F64_FXS32 + VCVT_GE_F64_FXS32 + VCVT_LT_F64_FXS32 + VCVT_GT_F64_FXS32 + VCVT_LE_F64_FXS32 + VCVT_F64_FXS32 + VCVT_ZZ_F64_FXS32 + VCVT_EQ_F64_FXU16 + VCVT_NE_F64_FXU16 + VCVT_CS_F64_FXU16 + VCVT_CC_F64_FXU16 + VCVT_MI_F64_FXU16 + VCVT_PL_F64_FXU16 + VCVT_VS_F64_FXU16 + VCVT_VC_F64_FXU16 + VCVT_HI_F64_FXU16 + VCVT_LS_F64_FXU16 + VCVT_GE_F64_FXU16 + VCVT_LT_F64_FXU16 + VCVT_GT_F64_FXU16 + VCVT_LE_F64_FXU16 + VCVT_F64_FXU16 + VCVT_ZZ_F64_FXU16 + VCVT_EQ_F64_FXU32 + VCVT_NE_F64_FXU32 + VCVT_CS_F64_FXU32 + VCVT_CC_F64_FXU32 + VCVT_MI_F64_FXU32 + VCVT_PL_F64_FXU32 + VCVT_VS_F64_FXU32 + VCVT_VC_F64_FXU32 + VCVT_HI_F64_FXU32 + VCVT_LS_F64_FXU32 + VCVT_GE_F64_FXU32 + VCVT_LT_F64_FXU32 + VCVT_GT_F64_FXU32 + VCVT_LE_F64_FXU32 + VCVT_F64_FXU32 + VCVT_ZZ_F64_FXU32 + VCVT_EQ_F32_U32 + VCVT_NE_F32_U32 + VCVT_CS_F32_U32 + VCVT_CC_F32_U32 + VCVT_MI_F32_U32 + VCVT_PL_F32_U32 + VCVT_VS_F32_U32 + VCVT_VC_F32_U32 + VCVT_HI_F32_U32 + VCVT_LS_F32_U32 + VCVT_GE_F32_U32 + VCVT_LT_F32_U32 + VCVT_GT_F32_U32 + VCVT_LE_F32_U32 + VCVT_F32_U32 + VCVT_ZZ_F32_U32 + VCVT_EQ_F32_S32 + VCVT_NE_F32_S32 + VCVT_CS_F32_S32 + VCVT_CC_F32_S32 + VCVT_MI_F32_S32 + VCVT_PL_F32_S32 + VCVT_VS_F32_S32 + VCVT_VC_F32_S32 + VCVT_HI_F32_S32 + VCVT_LS_F32_S32 + VCVT_GE_F32_S32 + VCVT_LT_F32_S32 + VCVT_GT_F32_S32 + VCVT_LE_F32_S32 + VCVT_F32_S32 + VCVT_ZZ_F32_S32 + VCVT_EQ_F64_U32 + VCVT_NE_F64_U32 + VCVT_CS_F64_U32 + VCVT_CC_F64_U32 + VCVT_MI_F64_U32 + VCVT_PL_F64_U32 + VCVT_VS_F64_U32 + VCVT_VC_F64_U32 + VCVT_HI_F64_U32 + VCVT_LS_F64_U32 + VCVT_GE_F64_U32 + VCVT_LT_F64_U32 + VCVT_GT_F64_U32 + VCVT_LE_F64_U32 + VCVT_F64_U32 + VCVT_ZZ_F64_U32 + VCVT_EQ_F64_S32 + VCVT_NE_F64_S32 + VCVT_CS_F64_S32 + VCVT_CC_F64_S32 + VCVT_MI_F64_S32 + VCVT_PL_F64_S32 + VCVT_VS_F64_S32 + VCVT_VC_F64_S32 + VCVT_HI_F64_S32 + VCVT_LS_F64_S32 + VCVT_GE_F64_S32 + VCVT_LT_F64_S32 + VCVT_GT_F64_S32 + VCVT_LE_F64_S32 + VCVT_F64_S32 + VCVT_ZZ_F64_S32 + VCVT_EQ_F64_F32 + VCVT_NE_F64_F32 + VCVT_CS_F64_F32 + VCVT_CC_F64_F32 + VCVT_MI_F64_F32 + VCVT_PL_F64_F32 + VCVT_VS_F64_F32 + VCVT_VC_F64_F32 + VCVT_HI_F64_F32 + VCVT_LS_F64_F32 + VCVT_GE_F64_F32 + VCVT_LT_F64_F32 + VCVT_GT_F64_F32 + VCVT_LE_F64_F32 + VCVT_F64_F32 + VCVT_ZZ_F64_F32 + VCVT_EQ_F32_F64 + VCVT_NE_F32_F64 + VCVT_CS_F32_F64 + VCVT_CC_F32_F64 + VCVT_MI_F32_F64 + VCVT_PL_F32_F64 + VCVT_VS_F32_F64 + VCVT_VC_F32_F64 + VCVT_HI_F32_F64 + VCVT_LS_F32_F64 + VCVT_GE_F32_F64 + VCVT_LT_F32_F64 + VCVT_GT_F32_F64 + VCVT_LE_F32_F64 + VCVT_F32_F64 + VCVT_ZZ_F32_F64 + VCVT_EQ_FXS16_F32 + VCVT_NE_FXS16_F32 + VCVT_CS_FXS16_F32 + VCVT_CC_FXS16_F32 + VCVT_MI_FXS16_F32 + VCVT_PL_FXS16_F32 + VCVT_VS_FXS16_F32 + VCVT_VC_FXS16_F32 + VCVT_HI_FXS16_F32 + VCVT_LS_FXS16_F32 + VCVT_GE_FXS16_F32 + VCVT_LT_FXS16_F32 + VCVT_GT_FXS16_F32 + VCVT_LE_FXS16_F32 + VCVT_FXS16_F32 + VCVT_ZZ_FXS16_F32 + VCVT_EQ_FXS16_F64 + VCVT_NE_FXS16_F64 + VCVT_CS_FXS16_F64 + VCVT_CC_FXS16_F64 + VCVT_MI_FXS16_F64 + VCVT_PL_FXS16_F64 + VCVT_VS_FXS16_F64 + VCVT_VC_FXS16_F64 + VCVT_HI_FXS16_F64 + VCVT_LS_FXS16_F64 + VCVT_GE_FXS16_F64 + VCVT_LT_FXS16_F64 + VCVT_GT_FXS16_F64 + VCVT_LE_FXS16_F64 + VCVT_FXS16_F64 + VCVT_ZZ_FXS16_F64 + VCVT_EQ_FXS32_F32 + VCVT_NE_FXS32_F32 + VCVT_CS_FXS32_F32 + VCVT_CC_FXS32_F32 + VCVT_MI_FXS32_F32 + VCVT_PL_FXS32_F32 + VCVT_VS_FXS32_F32 + VCVT_VC_FXS32_F32 + VCVT_HI_FXS32_F32 + VCVT_LS_FXS32_F32 + VCVT_GE_FXS32_F32 + VCVT_LT_FXS32_F32 + VCVT_GT_FXS32_F32 + VCVT_LE_FXS32_F32 + VCVT_FXS32_F32 + VCVT_ZZ_FXS32_F32 + VCVT_EQ_FXS32_F64 + VCVT_NE_FXS32_F64 + VCVT_CS_FXS32_F64 + VCVT_CC_FXS32_F64 + VCVT_MI_FXS32_F64 + VCVT_PL_FXS32_F64 + VCVT_VS_FXS32_F64 + VCVT_VC_FXS32_F64 + VCVT_HI_FXS32_F64 + VCVT_LS_FXS32_F64 + VCVT_GE_FXS32_F64 + VCVT_LT_FXS32_F64 + VCVT_GT_FXS32_F64 + VCVT_LE_FXS32_F64 + VCVT_FXS32_F64 + VCVT_ZZ_FXS32_F64 + VCVT_EQ_FXU16_F32 + VCVT_NE_FXU16_F32 + VCVT_CS_FXU16_F32 + VCVT_CC_FXU16_F32 + VCVT_MI_FXU16_F32 + VCVT_PL_FXU16_F32 + VCVT_VS_FXU16_F32 + VCVT_VC_FXU16_F32 + VCVT_HI_FXU16_F32 + VCVT_LS_FXU16_F32 + VCVT_GE_FXU16_F32 + VCVT_LT_FXU16_F32 + VCVT_GT_FXU16_F32 + VCVT_LE_FXU16_F32 + VCVT_FXU16_F32 + VCVT_ZZ_FXU16_F32 + VCVT_EQ_FXU16_F64 + VCVT_NE_FXU16_F64 + VCVT_CS_FXU16_F64 + VCVT_CC_FXU16_F64 + VCVT_MI_FXU16_F64 + VCVT_PL_FXU16_F64 + VCVT_VS_FXU16_F64 + VCVT_VC_FXU16_F64 + VCVT_HI_FXU16_F64 + VCVT_LS_FXU16_F64 + VCVT_GE_FXU16_F64 + VCVT_LT_FXU16_F64 + VCVT_GT_FXU16_F64 + VCVT_LE_FXU16_F64 + VCVT_FXU16_F64 + VCVT_ZZ_FXU16_F64 + VCVT_EQ_FXU32_F32 + VCVT_NE_FXU32_F32 + VCVT_CS_FXU32_F32 + VCVT_CC_FXU32_F32 + VCVT_MI_FXU32_F32 + VCVT_PL_FXU32_F32 + VCVT_VS_FXU32_F32 + VCVT_VC_FXU32_F32 + VCVT_HI_FXU32_F32 + VCVT_LS_FXU32_F32 + VCVT_GE_FXU32_F32 + VCVT_LT_FXU32_F32 + VCVT_GT_FXU32_F32 + VCVT_LE_FXU32_F32 + VCVT_FXU32_F32 + VCVT_ZZ_FXU32_F32 + VCVT_EQ_FXU32_F64 + VCVT_NE_FXU32_F64 + VCVT_CS_FXU32_F64 + VCVT_CC_FXU32_F64 + VCVT_MI_FXU32_F64 + VCVT_PL_FXU32_F64 + VCVT_VS_FXU32_F64 + VCVT_VC_FXU32_F64 + VCVT_HI_FXU32_F64 + VCVT_LS_FXU32_F64 + VCVT_GE_FXU32_F64 + VCVT_LT_FXU32_F64 + VCVT_GT_FXU32_F64 + VCVT_LE_FXU32_F64 + VCVT_FXU32_F64 + VCVT_ZZ_FXU32_F64 + VCVTB_EQ_F32_F16 + VCVTB_NE_F32_F16 + VCVTB_CS_F32_F16 + VCVTB_CC_F32_F16 + VCVTB_MI_F32_F16 + VCVTB_PL_F32_F16 + VCVTB_VS_F32_F16 + VCVTB_VC_F32_F16 + VCVTB_HI_F32_F16 + VCVTB_LS_F32_F16 + VCVTB_GE_F32_F16 + VCVTB_LT_F32_F16 + VCVTB_GT_F32_F16 + VCVTB_LE_F32_F16 + VCVTB_F32_F16 + VCVTB_ZZ_F32_F16 + VCVTB_EQ_F16_F32 + VCVTB_NE_F16_F32 + VCVTB_CS_F16_F32 + VCVTB_CC_F16_F32 + VCVTB_MI_F16_F32 + VCVTB_PL_F16_F32 + VCVTB_VS_F16_F32 + VCVTB_VC_F16_F32 + VCVTB_HI_F16_F32 + VCVTB_LS_F16_F32 + VCVTB_GE_F16_F32 + VCVTB_LT_F16_F32 + VCVTB_GT_F16_F32 + VCVTB_LE_F16_F32 + VCVTB_F16_F32 + VCVTB_ZZ_F16_F32 + VCVTT_EQ_F32_F16 + VCVTT_NE_F32_F16 + VCVTT_CS_F32_F16 + VCVTT_CC_F32_F16 + VCVTT_MI_F32_F16 + VCVTT_PL_F32_F16 + VCVTT_VS_F32_F16 + VCVTT_VC_F32_F16 + VCVTT_HI_F32_F16 + VCVTT_LS_F32_F16 + VCVTT_GE_F32_F16 + VCVTT_LT_F32_F16 + VCVTT_GT_F32_F16 + VCVTT_LE_F32_F16 + VCVTT_F32_F16 + VCVTT_ZZ_F32_F16 + VCVTT_EQ_F16_F32 + VCVTT_NE_F16_F32 + VCVTT_CS_F16_F32 + VCVTT_CC_F16_F32 + VCVTT_MI_F16_F32 + VCVTT_PL_F16_F32 + VCVTT_VS_F16_F32 + VCVTT_VC_F16_F32 + VCVTT_HI_F16_F32 + VCVTT_LS_F16_F32 + VCVTT_GE_F16_F32 + VCVTT_LT_F16_F32 + VCVTT_GT_F16_F32 + VCVTT_LE_F16_F32 + VCVTT_F16_F32 + VCVTT_ZZ_F16_F32 + VCVTR_EQ_U32_F32 + VCVTR_NE_U32_F32 + VCVTR_CS_U32_F32 + VCVTR_CC_U32_F32 + VCVTR_MI_U32_F32 + VCVTR_PL_U32_F32 + VCVTR_VS_U32_F32 + VCVTR_VC_U32_F32 + VCVTR_HI_U32_F32 + VCVTR_LS_U32_F32 + VCVTR_GE_U32_F32 + VCVTR_LT_U32_F32 + VCVTR_GT_U32_F32 + VCVTR_LE_U32_F32 + VCVTR_U32_F32 + VCVTR_ZZ_U32_F32 + VCVTR_EQ_U32_F64 + VCVTR_NE_U32_F64 + VCVTR_CS_U32_F64 + VCVTR_CC_U32_F64 + VCVTR_MI_U32_F64 + VCVTR_PL_U32_F64 + VCVTR_VS_U32_F64 + VCVTR_VC_U32_F64 + VCVTR_HI_U32_F64 + VCVTR_LS_U32_F64 + VCVTR_GE_U32_F64 + VCVTR_LT_U32_F64 + VCVTR_GT_U32_F64 + VCVTR_LE_U32_F64 + VCVTR_U32_F64 + VCVTR_ZZ_U32_F64 + VCVTR_EQ_S32_F32 + VCVTR_NE_S32_F32 + VCVTR_CS_S32_F32 + VCVTR_CC_S32_F32 + VCVTR_MI_S32_F32 + VCVTR_PL_S32_F32 + VCVTR_VS_S32_F32 + VCVTR_VC_S32_F32 + VCVTR_HI_S32_F32 + VCVTR_LS_S32_F32 + VCVTR_GE_S32_F32 + VCVTR_LT_S32_F32 + VCVTR_GT_S32_F32 + VCVTR_LE_S32_F32 + VCVTR_S32_F32 + VCVTR_ZZ_S32_F32 + VCVTR_EQ_S32_F64 + VCVTR_NE_S32_F64 + VCVTR_CS_S32_F64 + VCVTR_CC_S32_F64 + VCVTR_MI_S32_F64 + VCVTR_PL_S32_F64 + VCVTR_VS_S32_F64 + VCVTR_VC_S32_F64 + VCVTR_HI_S32_F64 + VCVTR_LS_S32_F64 + VCVTR_GE_S32_F64 + VCVTR_LT_S32_F64 + VCVTR_GT_S32_F64 + VCVTR_LE_S32_F64 + VCVTR_S32_F64 + VCVTR_ZZ_S32_F64 + VCVT_EQ_U32_F32 + VCVT_NE_U32_F32 + VCVT_CS_U32_F32 + VCVT_CC_U32_F32 + VCVT_MI_U32_F32 + VCVT_PL_U32_F32 + VCVT_VS_U32_F32 + VCVT_VC_U32_F32 + VCVT_HI_U32_F32 + VCVT_LS_U32_F32 + VCVT_GE_U32_F32 + VCVT_LT_U32_F32 + VCVT_GT_U32_F32 + VCVT_LE_U32_F32 + VCVT_U32_F32 + VCVT_ZZ_U32_F32 + VCVT_EQ_U32_F64 + VCVT_NE_U32_F64 + VCVT_CS_U32_F64 + VCVT_CC_U32_F64 + VCVT_MI_U32_F64 + VCVT_PL_U32_F64 + VCVT_VS_U32_F64 + VCVT_VC_U32_F64 + VCVT_HI_U32_F64 + VCVT_LS_U32_F64 + VCVT_GE_U32_F64 + VCVT_LT_U32_F64 + VCVT_GT_U32_F64 + VCVT_LE_U32_F64 + VCVT_U32_F64 + VCVT_ZZ_U32_F64 + VCVT_EQ_S32_F32 + VCVT_NE_S32_F32 + VCVT_CS_S32_F32 + VCVT_CC_S32_F32 + VCVT_MI_S32_F32 + VCVT_PL_S32_F32 + VCVT_VS_S32_F32 + VCVT_VC_S32_F32 + VCVT_HI_S32_F32 + VCVT_LS_S32_F32 + VCVT_GE_S32_F32 + VCVT_LT_S32_F32 + VCVT_GT_S32_F32 + VCVT_LE_S32_F32 + VCVT_S32_F32 + VCVT_ZZ_S32_F32 + VCVT_EQ_S32_F64 + VCVT_NE_S32_F64 + VCVT_CS_S32_F64 + VCVT_CC_S32_F64 + VCVT_MI_S32_F64 + VCVT_PL_S32_F64 + VCVT_VS_S32_F64 + VCVT_VC_S32_F64 + VCVT_HI_S32_F64 + VCVT_LS_S32_F64 + VCVT_GE_S32_F64 + VCVT_LT_S32_F64 + VCVT_GT_S32_F64 + VCVT_LE_S32_F64 + VCVT_S32_F64 + VCVT_ZZ_S32_F64 + VDIV_EQ_F32 + VDIV_NE_F32 + VDIV_CS_F32 + VDIV_CC_F32 + VDIV_MI_F32 + VDIV_PL_F32 + VDIV_VS_F32 + VDIV_VC_F32 + VDIV_HI_F32 + VDIV_LS_F32 + VDIV_GE_F32 + VDIV_LT_F32 + VDIV_GT_F32 + VDIV_LE_F32 + VDIV_F32 + VDIV_ZZ_F32 + VDIV_EQ_F64 + VDIV_NE_F64 + VDIV_CS_F64 + VDIV_CC_F64 + VDIV_MI_F64 + VDIV_PL_F64 + VDIV_VS_F64 + VDIV_VC_F64 + VDIV_HI_F64 + VDIV_LS_F64 + VDIV_GE_F64 + VDIV_LT_F64 + VDIV_GT_F64 + VDIV_LE_F64 + VDIV_F64 + VDIV_ZZ_F64 + VLDR_EQ + VLDR_NE + VLDR_CS + VLDR_CC + VLDR_MI + VLDR_PL + VLDR_VS + VLDR_VC + VLDR_HI + VLDR_LS + VLDR_GE + VLDR_LT + VLDR_GT + VLDR_LE + VLDR + VLDR_ZZ + VMLA_EQ_F32 + VMLA_NE_F32 + VMLA_CS_F32 + VMLA_CC_F32 + VMLA_MI_F32 + VMLA_PL_F32 + VMLA_VS_F32 + VMLA_VC_F32 + VMLA_HI_F32 + VMLA_LS_F32 + VMLA_GE_F32 + VMLA_LT_F32 + VMLA_GT_F32 + VMLA_LE_F32 + VMLA_F32 + VMLA_ZZ_F32 + VMLA_EQ_F64 + VMLA_NE_F64 + VMLA_CS_F64 + VMLA_CC_F64 + VMLA_MI_F64 + VMLA_PL_F64 + VMLA_VS_F64 + VMLA_VC_F64 + VMLA_HI_F64 + VMLA_LS_F64 + VMLA_GE_F64 + VMLA_LT_F64 + VMLA_GT_F64 + VMLA_LE_F64 + VMLA_F64 + VMLA_ZZ_F64 + VMLS_EQ_F32 + VMLS_NE_F32 + VMLS_CS_F32 + VMLS_CC_F32 + VMLS_MI_F32 + VMLS_PL_F32 + VMLS_VS_F32 + VMLS_VC_F32 + VMLS_HI_F32 + VMLS_LS_F32 + VMLS_GE_F32 + VMLS_LT_F32 + VMLS_GT_F32 + VMLS_LE_F32 + VMLS_F32 + VMLS_ZZ_F32 + VMLS_EQ_F64 + VMLS_NE_F64 + VMLS_CS_F64 + VMLS_CC_F64 + VMLS_MI_F64 + VMLS_PL_F64 + VMLS_VS_F64 + VMLS_VC_F64 + VMLS_HI_F64 + VMLS_LS_F64 + VMLS_GE_F64 + VMLS_LT_F64 + VMLS_GT_F64 + VMLS_LE_F64 + VMLS_F64 + VMLS_ZZ_F64 + VMOV_EQ + VMOV_NE + VMOV_CS + VMOV_CC + VMOV_MI + VMOV_PL + VMOV_VS + VMOV_VC + VMOV_HI + VMOV_LS + VMOV_GE + VMOV_LT + VMOV_GT + VMOV_LE + VMOV + VMOV_ZZ + VMOV_EQ_32 + VMOV_NE_32 + VMOV_CS_32 + VMOV_CC_32 + VMOV_MI_32 + VMOV_PL_32 + VMOV_VS_32 + VMOV_VC_32 + VMOV_HI_32 + VMOV_LS_32 + VMOV_GE_32 + VMOV_LT_32 + VMOV_GT_32 + VMOV_LE_32 + VMOV_32 + VMOV_ZZ_32 + VMOV_EQ_F32 + VMOV_NE_F32 + VMOV_CS_F32 + VMOV_CC_F32 + VMOV_MI_F32 + VMOV_PL_F32 + VMOV_VS_F32 + VMOV_VC_F32 + VMOV_HI_F32 + VMOV_LS_F32 + VMOV_GE_F32 + VMOV_LT_F32 + VMOV_GT_F32 + VMOV_LE_F32 + VMOV_F32 + VMOV_ZZ_F32 + VMOV_EQ_F64 + VMOV_NE_F64 + VMOV_CS_F64 + VMOV_CC_F64 + VMOV_MI_F64 + VMOV_PL_F64 + VMOV_VS_F64 + VMOV_VC_F64 + VMOV_HI_F64 + VMOV_LS_F64 + VMOV_GE_F64 + VMOV_LT_F64 + VMOV_GT_F64 + VMOV_LE_F64 + VMOV_F64 + VMOV_ZZ_F64 + VMRS_EQ + VMRS_NE + VMRS_CS + VMRS_CC + VMRS_MI + VMRS_PL + VMRS_VS + VMRS_VC + VMRS_HI + VMRS_LS + VMRS_GE + VMRS_LT + VMRS_GT + VMRS_LE + VMRS + VMRS_ZZ + VMSR_EQ + VMSR_NE + VMSR_CS + VMSR_CC + VMSR_MI + VMSR_PL + VMSR_VS + VMSR_VC + VMSR_HI + VMSR_LS + VMSR_GE + VMSR_LT + VMSR_GT + VMSR_LE + VMSR + VMSR_ZZ + VMUL_EQ_F32 + VMUL_NE_F32 + VMUL_CS_F32 + VMUL_CC_F32 + VMUL_MI_F32 + VMUL_PL_F32 + VMUL_VS_F32 + VMUL_VC_F32 + VMUL_HI_F32 + VMUL_LS_F32 + VMUL_GE_F32 + VMUL_LT_F32 + VMUL_GT_F32 + VMUL_LE_F32 + VMUL_F32 + VMUL_ZZ_F32 + VMUL_EQ_F64 + VMUL_NE_F64 + VMUL_CS_F64 + VMUL_CC_F64 + VMUL_MI_F64 + VMUL_PL_F64 + VMUL_VS_F64 + VMUL_VC_F64 + VMUL_HI_F64 + VMUL_LS_F64 + VMUL_GE_F64 + VMUL_LT_F64 + VMUL_GT_F64 + VMUL_LE_F64 + VMUL_F64 + VMUL_ZZ_F64 + VNEG_EQ_F32 + VNEG_NE_F32 + VNEG_CS_F32 + VNEG_CC_F32 + VNEG_MI_F32 + VNEG_PL_F32 + VNEG_VS_F32 + VNEG_VC_F32 + VNEG_HI_F32 + VNEG_LS_F32 + VNEG_GE_F32 + VNEG_LT_F32 + VNEG_GT_F32 + VNEG_LE_F32 + VNEG_F32 + VNEG_ZZ_F32 + VNEG_EQ_F64 + VNEG_NE_F64 + VNEG_CS_F64 + VNEG_CC_F64 + VNEG_MI_F64 + VNEG_PL_F64 + VNEG_VS_F64 + VNEG_VC_F64 + VNEG_HI_F64 + VNEG_LS_F64 + VNEG_GE_F64 + VNEG_LT_F64 + VNEG_GT_F64 + VNEG_LE_F64 + VNEG_F64 + VNEG_ZZ_F64 + VNMLS_EQ_F32 + VNMLS_NE_F32 + VNMLS_CS_F32 + VNMLS_CC_F32 + VNMLS_MI_F32 + VNMLS_PL_F32 + VNMLS_VS_F32 + VNMLS_VC_F32 + VNMLS_HI_F32 + VNMLS_LS_F32 + VNMLS_GE_F32 + VNMLS_LT_F32 + VNMLS_GT_F32 + VNMLS_LE_F32 + VNMLS_F32 + VNMLS_ZZ_F32 + VNMLS_EQ_F64 + VNMLS_NE_F64 + VNMLS_CS_F64 + VNMLS_CC_F64 + VNMLS_MI_F64 + VNMLS_PL_F64 + VNMLS_VS_F64 + VNMLS_VC_F64 + VNMLS_HI_F64 + VNMLS_LS_F64 + VNMLS_GE_F64 + VNMLS_LT_F64 + VNMLS_GT_F64 + VNMLS_LE_F64 + VNMLS_F64 + VNMLS_ZZ_F64 + VNMLA_EQ_F32 + VNMLA_NE_F32 + VNMLA_CS_F32 + VNMLA_CC_F32 + VNMLA_MI_F32 + VNMLA_PL_F32 + VNMLA_VS_F32 + VNMLA_VC_F32 + VNMLA_HI_F32 + VNMLA_LS_F32 + VNMLA_GE_F32 + VNMLA_LT_F32 + VNMLA_GT_F32 + VNMLA_LE_F32 + VNMLA_F32 + VNMLA_ZZ_F32 + VNMLA_EQ_F64 + VNMLA_NE_F64 + VNMLA_CS_F64 + VNMLA_CC_F64 + VNMLA_MI_F64 + VNMLA_PL_F64 + VNMLA_VS_F64 + VNMLA_VC_F64 + VNMLA_HI_F64 + VNMLA_LS_F64 + VNMLA_GE_F64 + VNMLA_LT_F64 + VNMLA_GT_F64 + VNMLA_LE_F64 + VNMLA_F64 + VNMLA_ZZ_F64 + VNMUL_EQ_F32 + VNMUL_NE_F32 + VNMUL_CS_F32 + VNMUL_CC_F32 + VNMUL_MI_F32 + VNMUL_PL_F32 + VNMUL_VS_F32 + VNMUL_VC_F32 + VNMUL_HI_F32 + VNMUL_LS_F32 + VNMUL_GE_F32 + VNMUL_LT_F32 + VNMUL_GT_F32 + VNMUL_LE_F32 + VNMUL_F32 + VNMUL_ZZ_F32 + VNMUL_EQ_F64 + VNMUL_NE_F64 + VNMUL_CS_F64 + VNMUL_CC_F64 + VNMUL_MI_F64 + VNMUL_PL_F64 + VNMUL_VS_F64 + VNMUL_VC_F64 + VNMUL_HI_F64 + VNMUL_LS_F64 + VNMUL_GE_F64 + VNMUL_LT_F64 + VNMUL_GT_F64 + VNMUL_LE_F64 + VNMUL_F64 + VNMUL_ZZ_F64 + VSQRT_EQ_F32 + VSQRT_NE_F32 + VSQRT_CS_F32 + VSQRT_CC_F32 + VSQRT_MI_F32 + VSQRT_PL_F32 + VSQRT_VS_F32 + VSQRT_VC_F32 + VSQRT_HI_F32 + VSQRT_LS_F32 + VSQRT_GE_F32 + VSQRT_LT_F32 + VSQRT_GT_F32 + VSQRT_LE_F32 + VSQRT_F32 + VSQRT_ZZ_F32 + VSQRT_EQ_F64 + VSQRT_NE_F64 + VSQRT_CS_F64 + VSQRT_CC_F64 + VSQRT_MI_F64 + VSQRT_PL_F64 + VSQRT_VS_F64 + VSQRT_VC_F64 + VSQRT_HI_F64 + VSQRT_LS_F64 + VSQRT_GE_F64 + VSQRT_LT_F64 + VSQRT_GT_F64 + VSQRT_LE_F64 + VSQRT_F64 + VSQRT_ZZ_F64 + VSTR_EQ + VSTR_NE + VSTR_CS + VSTR_CC + VSTR_MI + VSTR_PL + VSTR_VS + VSTR_VC + VSTR_HI + VSTR_LS + VSTR_GE + VSTR_LT + VSTR_GT + VSTR_LE + VSTR + VSTR_ZZ + VSUB_EQ_F32 + VSUB_NE_F32 + VSUB_CS_F32 + VSUB_CC_F32 + VSUB_MI_F32 + VSUB_PL_F32 + VSUB_VS_F32 + VSUB_VC_F32 + VSUB_HI_F32 + VSUB_LS_F32 + VSUB_GE_F32 + VSUB_LT_F32 + VSUB_GT_F32 + VSUB_LE_F32 + VSUB_F32 + VSUB_ZZ_F32 + VSUB_EQ_F64 + VSUB_NE_F64 + VSUB_CS_F64 + VSUB_CC_F64 + VSUB_MI_F64 + VSUB_PL_F64 + VSUB_VS_F64 + VSUB_VC_F64 + VSUB_HI_F64 + VSUB_LS_F64 + VSUB_GE_F64 + VSUB_LT_F64 + VSUB_GT_F64 + VSUB_LE_F64 + VSUB_F64 + VSUB_ZZ_F64 + WFE_EQ + WFE_NE + WFE_CS + WFE_CC + WFE_MI + WFE_PL + WFE_VS + WFE_VC + WFE_HI + WFE_LS + WFE_GE + WFE_LT + WFE_GT + WFE_LE + WFE + WFE_ZZ + WFI_EQ + WFI_NE + WFI_CS + WFI_CC + WFI_MI + WFI_PL + WFI_VS + WFI_VC + WFI_HI + WFI_LS + WFI_GE + WFI_LT + WFI_GT + WFI_LE + WFI + WFI_ZZ + YIELD_EQ + YIELD_NE + YIELD_CS + YIELD_CC + YIELD_MI + YIELD_PL + YIELD_VS + YIELD_VC + YIELD_HI + YIELD_LS + YIELD_GE + YIELD_LT + YIELD_GT + YIELD_LE + YIELD + YIELD_ZZ +) + +var opstr = [...]string{ + ADC_EQ: "ADC.EQ", + ADC_NE: "ADC.NE", + ADC_CS: "ADC.CS", + ADC_CC: "ADC.CC", + ADC_MI: "ADC.MI", + ADC_PL: "ADC.PL", + ADC_VS: "ADC.VS", + ADC_VC: "ADC.VC", + ADC_HI: "ADC.HI", + ADC_LS: "ADC.LS", + ADC_GE: "ADC.GE", + ADC_LT: "ADC.LT", + ADC_GT: "ADC.GT", + ADC_LE: "ADC.LE", + ADC: "ADC", + ADC_ZZ: "ADC.ZZ", + ADC_S_EQ: "ADC.S.EQ", + ADC_S_NE: "ADC.S.NE", + ADC_S_CS: "ADC.S.CS", + ADC_S_CC: "ADC.S.CC", + ADC_S_MI: "ADC.S.MI", + ADC_S_PL: "ADC.S.PL", + ADC_S_VS: "ADC.S.VS", + ADC_S_VC: "ADC.S.VC", + ADC_S_HI: "ADC.S.HI", + ADC_S_LS: "ADC.S.LS", + ADC_S_GE: "ADC.S.GE", + ADC_S_LT: "ADC.S.LT", + ADC_S_GT: "ADC.S.GT", + ADC_S_LE: "ADC.S.LE", + ADC_S: "ADC.S", + ADC_S_ZZ: "ADC.S.ZZ", + ADD_EQ: "ADD.EQ", + ADD_NE: "ADD.NE", + ADD_CS: "ADD.CS", + ADD_CC: "ADD.CC", + ADD_MI: "ADD.MI", + ADD_PL: "ADD.PL", + ADD_VS: "ADD.VS", + ADD_VC: "ADD.VC", + ADD_HI: "ADD.HI", + ADD_LS: "ADD.LS", + ADD_GE: "ADD.GE", + ADD_LT: "ADD.LT", + ADD_GT: "ADD.GT", + ADD_LE: "ADD.LE", + ADD: "ADD", + ADD_ZZ: "ADD.ZZ", + ADD_S_EQ: "ADD.S.EQ", + ADD_S_NE: "ADD.S.NE", + ADD_S_CS: "ADD.S.CS", + ADD_S_CC: "ADD.S.CC", + ADD_S_MI: "ADD.S.MI", + ADD_S_PL: "ADD.S.PL", + ADD_S_VS: "ADD.S.VS", + ADD_S_VC: "ADD.S.VC", + ADD_S_HI: "ADD.S.HI", + ADD_S_LS: "ADD.S.LS", + ADD_S_GE: "ADD.S.GE", + ADD_S_LT: "ADD.S.LT", + ADD_S_GT: "ADD.S.GT", + ADD_S_LE: "ADD.S.LE", + ADD_S: "ADD.S", + ADD_S_ZZ: "ADD.S.ZZ", + AND_EQ: "AND.EQ", + AND_NE: "AND.NE", + AND_CS: "AND.CS", + AND_CC: "AND.CC", + AND_MI: "AND.MI", + AND_PL: "AND.PL", + AND_VS: "AND.VS", + AND_VC: "AND.VC", + AND_HI: "AND.HI", + AND_LS: "AND.LS", + AND_GE: "AND.GE", + AND_LT: "AND.LT", + AND_GT: "AND.GT", + AND_LE: "AND.LE", + AND: "AND", + AND_ZZ: "AND.ZZ", + AND_S_EQ: "AND.S.EQ", + AND_S_NE: "AND.S.NE", + AND_S_CS: "AND.S.CS", + AND_S_CC: "AND.S.CC", + AND_S_MI: "AND.S.MI", + AND_S_PL: "AND.S.PL", + AND_S_VS: "AND.S.VS", + AND_S_VC: "AND.S.VC", + AND_S_HI: "AND.S.HI", + AND_S_LS: "AND.S.LS", + AND_S_GE: "AND.S.GE", + AND_S_LT: "AND.S.LT", + AND_S_GT: "AND.S.GT", + AND_S_LE: "AND.S.LE", + AND_S: "AND.S", + AND_S_ZZ: "AND.S.ZZ", + ASR_EQ: "ASR.EQ", + ASR_NE: "ASR.NE", + ASR_CS: "ASR.CS", + ASR_CC: "ASR.CC", + ASR_MI: "ASR.MI", + ASR_PL: "ASR.PL", + ASR_VS: "ASR.VS", + ASR_VC: "ASR.VC", + ASR_HI: "ASR.HI", + ASR_LS: "ASR.LS", + ASR_GE: "ASR.GE", + ASR_LT: "ASR.LT", + ASR_GT: "ASR.GT", + ASR_LE: "ASR.LE", + ASR: "ASR", + ASR_ZZ: "ASR.ZZ", + ASR_S_EQ: "ASR.S.EQ", + ASR_S_NE: "ASR.S.NE", + ASR_S_CS: "ASR.S.CS", + ASR_S_CC: "ASR.S.CC", + ASR_S_MI: "ASR.S.MI", + ASR_S_PL: "ASR.S.PL", + ASR_S_VS: "ASR.S.VS", + ASR_S_VC: "ASR.S.VC", + ASR_S_HI: "ASR.S.HI", + ASR_S_LS: "ASR.S.LS", + ASR_S_GE: "ASR.S.GE", + ASR_S_LT: "ASR.S.LT", + ASR_S_GT: "ASR.S.GT", + ASR_S_LE: "ASR.S.LE", + ASR_S: "ASR.S", + ASR_S_ZZ: "ASR.S.ZZ", + B_EQ: "B.EQ", + B_NE: "B.NE", + B_CS: "B.CS", + B_CC: "B.CC", + B_MI: "B.MI", + B_PL: "B.PL", + B_VS: "B.VS", + B_VC: "B.VC", + B_HI: "B.HI", + B_LS: "B.LS", + B_GE: "B.GE", + B_LT: "B.LT", + B_GT: "B.GT", + B_LE: "B.LE", + B: "B", + B_ZZ: "B.ZZ", + BFC_EQ: "BFC.EQ", + BFC_NE: "BFC.NE", + BFC_CS: "BFC.CS", + BFC_CC: "BFC.CC", + BFC_MI: "BFC.MI", + BFC_PL: "BFC.PL", + BFC_VS: "BFC.VS", + BFC_VC: "BFC.VC", + BFC_HI: "BFC.HI", + BFC_LS: "BFC.LS", + BFC_GE: "BFC.GE", + BFC_LT: "BFC.LT", + BFC_GT: "BFC.GT", + BFC_LE: "BFC.LE", + BFC: "BFC", + BFC_ZZ: "BFC.ZZ", + BFI_EQ: "BFI.EQ", + BFI_NE: "BFI.NE", + BFI_CS: "BFI.CS", + BFI_CC: "BFI.CC", + BFI_MI: "BFI.MI", + BFI_PL: "BFI.PL", + BFI_VS: "BFI.VS", + BFI_VC: "BFI.VC", + BFI_HI: "BFI.HI", + BFI_LS: "BFI.LS", + BFI_GE: "BFI.GE", + BFI_LT: "BFI.LT", + BFI_GT: "BFI.GT", + BFI_LE: "BFI.LE", + BFI: "BFI", + BFI_ZZ: "BFI.ZZ", + BIC_EQ: "BIC.EQ", + BIC_NE: "BIC.NE", + BIC_CS: "BIC.CS", + BIC_CC: "BIC.CC", + BIC_MI: "BIC.MI", + BIC_PL: "BIC.PL", + BIC_VS: "BIC.VS", + BIC_VC: "BIC.VC", + BIC_HI: "BIC.HI", + BIC_LS: "BIC.LS", + BIC_GE: "BIC.GE", + BIC_LT: "BIC.LT", + BIC_GT: "BIC.GT", + BIC_LE: "BIC.LE", + BIC: "BIC", + BIC_ZZ: "BIC.ZZ", + BIC_S_EQ: "BIC.S.EQ", + BIC_S_NE: "BIC.S.NE", + BIC_S_CS: "BIC.S.CS", + BIC_S_CC: "BIC.S.CC", + BIC_S_MI: "BIC.S.MI", + BIC_S_PL: "BIC.S.PL", + BIC_S_VS: "BIC.S.VS", + BIC_S_VC: "BIC.S.VC", + BIC_S_HI: "BIC.S.HI", + BIC_S_LS: "BIC.S.LS", + BIC_S_GE: "BIC.S.GE", + BIC_S_LT: "BIC.S.LT", + BIC_S_GT: "BIC.S.GT", + BIC_S_LE: "BIC.S.LE", + BIC_S: "BIC.S", + BIC_S_ZZ: "BIC.S.ZZ", + BKPT_EQ: "BKPT.EQ", + BKPT_NE: "BKPT.NE", + BKPT_CS: "BKPT.CS", + BKPT_CC: "BKPT.CC", + BKPT_MI: "BKPT.MI", + BKPT_PL: "BKPT.PL", + BKPT_VS: "BKPT.VS", + BKPT_VC: "BKPT.VC", + BKPT_HI: "BKPT.HI", + BKPT_LS: "BKPT.LS", + BKPT_GE: "BKPT.GE", + BKPT_LT: "BKPT.LT", + BKPT_GT: "BKPT.GT", + BKPT_LE: "BKPT.LE", + BKPT: "BKPT", + BKPT_ZZ: "BKPT.ZZ", + BL_EQ: "BL.EQ", + BL_NE: "BL.NE", + BL_CS: "BL.CS", + BL_CC: "BL.CC", + BL_MI: "BL.MI", + BL_PL: "BL.PL", + BL_VS: "BL.VS", + BL_VC: "BL.VC", + BL_HI: "BL.HI", + BL_LS: "BL.LS", + BL_GE: "BL.GE", + BL_LT: "BL.LT", + BL_GT: "BL.GT", + BL_LE: "BL.LE", + BL: "BL", + BL_ZZ: "BL.ZZ", + BLX_EQ: "BLX.EQ", + BLX_NE: "BLX.NE", + BLX_CS: "BLX.CS", + BLX_CC: "BLX.CC", + BLX_MI: "BLX.MI", + BLX_PL: "BLX.PL", + BLX_VS: "BLX.VS", + BLX_VC: "BLX.VC", + BLX_HI: "BLX.HI", + BLX_LS: "BLX.LS", + BLX_GE: "BLX.GE", + BLX_LT: "BLX.LT", + BLX_GT: "BLX.GT", + BLX_LE: "BLX.LE", + BLX: "BLX", + BLX_ZZ: "BLX.ZZ", + BX_EQ: "BX.EQ", + BX_NE: "BX.NE", + BX_CS: "BX.CS", + BX_CC: "BX.CC", + BX_MI: "BX.MI", + BX_PL: "BX.PL", + BX_VS: "BX.VS", + BX_VC: "BX.VC", + BX_HI: "BX.HI", + BX_LS: "BX.LS", + BX_GE: "BX.GE", + BX_LT: "BX.LT", + BX_GT: "BX.GT", + BX_LE: "BX.LE", + BX: "BX", + BX_ZZ: "BX.ZZ", + BXJ_EQ: "BXJ.EQ", + BXJ_NE: "BXJ.NE", + BXJ_CS: "BXJ.CS", + BXJ_CC: "BXJ.CC", + BXJ_MI: "BXJ.MI", + BXJ_PL: "BXJ.PL", + BXJ_VS: "BXJ.VS", + BXJ_VC: "BXJ.VC", + BXJ_HI: "BXJ.HI", + BXJ_LS: "BXJ.LS", + BXJ_GE: "BXJ.GE", + BXJ_LT: "BXJ.LT", + BXJ_GT: "BXJ.GT", + BXJ_LE: "BXJ.LE", + BXJ: "BXJ", + BXJ_ZZ: "BXJ.ZZ", + CLREX: "CLREX", + CLZ_EQ: "CLZ.EQ", + CLZ_NE: "CLZ.NE", + CLZ_CS: "CLZ.CS", + CLZ_CC: "CLZ.CC", + CLZ_MI: "CLZ.MI", + CLZ_PL: "CLZ.PL", + CLZ_VS: "CLZ.VS", + CLZ_VC: "CLZ.VC", + CLZ_HI: "CLZ.HI", + CLZ_LS: "CLZ.LS", + CLZ_GE: "CLZ.GE", + CLZ_LT: "CLZ.LT", + CLZ_GT: "CLZ.GT", + CLZ_LE: "CLZ.LE", + CLZ: "CLZ", + CLZ_ZZ: "CLZ.ZZ", + CMN_EQ: "CMN.EQ", + CMN_NE: "CMN.NE", + CMN_CS: "CMN.CS", + CMN_CC: "CMN.CC", + CMN_MI: "CMN.MI", + CMN_PL: "CMN.PL", + CMN_VS: "CMN.VS", + CMN_VC: "CMN.VC", + CMN_HI: "CMN.HI", + CMN_LS: "CMN.LS", + CMN_GE: "CMN.GE", + CMN_LT: "CMN.LT", + CMN_GT: "CMN.GT", + CMN_LE: "CMN.LE", + CMN: "CMN", + CMN_ZZ: "CMN.ZZ", + CMP_EQ: "CMP.EQ", + CMP_NE: "CMP.NE", + CMP_CS: "CMP.CS", + CMP_CC: "CMP.CC", + CMP_MI: "CMP.MI", + CMP_PL: "CMP.PL", + CMP_VS: "CMP.VS", + CMP_VC: "CMP.VC", + CMP_HI: "CMP.HI", + CMP_LS: "CMP.LS", + CMP_GE: "CMP.GE", + CMP_LT: "CMP.LT", + CMP_GT: "CMP.GT", + CMP_LE: "CMP.LE", + CMP: "CMP", + CMP_ZZ: "CMP.ZZ", + DBG_EQ: "DBG.EQ", + DBG_NE: "DBG.NE", + DBG_CS: "DBG.CS", + DBG_CC: "DBG.CC", + DBG_MI: "DBG.MI", + DBG_PL: "DBG.PL", + DBG_VS: "DBG.VS", + DBG_VC: "DBG.VC", + DBG_HI: "DBG.HI", + DBG_LS: "DBG.LS", + DBG_GE: "DBG.GE", + DBG_LT: "DBG.LT", + DBG_GT: "DBG.GT", + DBG_LE: "DBG.LE", + DBG: "DBG", + DBG_ZZ: "DBG.ZZ", + DMB: "DMB", + DSB: "DSB", + EOR_EQ: "EOR.EQ", + EOR_NE: "EOR.NE", + EOR_CS: "EOR.CS", + EOR_CC: "EOR.CC", + EOR_MI: "EOR.MI", + EOR_PL: "EOR.PL", + EOR_VS: "EOR.VS", + EOR_VC: "EOR.VC", + EOR_HI: "EOR.HI", + EOR_LS: "EOR.LS", + EOR_GE: "EOR.GE", + EOR_LT: "EOR.LT", + EOR_GT: "EOR.GT", + EOR_LE: "EOR.LE", + EOR: "EOR", + EOR_ZZ: "EOR.ZZ", + EOR_S_EQ: "EOR.S.EQ", + EOR_S_NE: "EOR.S.NE", + EOR_S_CS: "EOR.S.CS", + EOR_S_CC: "EOR.S.CC", + EOR_S_MI: "EOR.S.MI", + EOR_S_PL: "EOR.S.PL", + EOR_S_VS: "EOR.S.VS", + EOR_S_VC: "EOR.S.VC", + EOR_S_HI: "EOR.S.HI", + EOR_S_LS: "EOR.S.LS", + EOR_S_GE: "EOR.S.GE", + EOR_S_LT: "EOR.S.LT", + EOR_S_GT: "EOR.S.GT", + EOR_S_LE: "EOR.S.LE", + EOR_S: "EOR.S", + EOR_S_ZZ: "EOR.S.ZZ", + ISB: "ISB", + LDM_EQ: "LDM.EQ", + LDM_NE: "LDM.NE", + LDM_CS: "LDM.CS", + LDM_CC: "LDM.CC", + LDM_MI: "LDM.MI", + LDM_PL: "LDM.PL", + LDM_VS: "LDM.VS", + LDM_VC: "LDM.VC", + LDM_HI: "LDM.HI", + LDM_LS: "LDM.LS", + LDM_GE: "LDM.GE", + LDM_LT: "LDM.LT", + LDM_GT: "LDM.GT", + LDM_LE: "LDM.LE", + LDM: "LDM", + LDM_ZZ: "LDM.ZZ", + LDMDA_EQ: "LDMDA.EQ", + LDMDA_NE: "LDMDA.NE", + LDMDA_CS: "LDMDA.CS", + LDMDA_CC: "LDMDA.CC", + LDMDA_MI: "LDMDA.MI", + LDMDA_PL: "LDMDA.PL", + LDMDA_VS: "LDMDA.VS", + LDMDA_VC: "LDMDA.VC", + LDMDA_HI: "LDMDA.HI", + LDMDA_LS: "LDMDA.LS", + LDMDA_GE: "LDMDA.GE", + LDMDA_LT: "LDMDA.LT", + LDMDA_GT: "LDMDA.GT", + LDMDA_LE: "LDMDA.LE", + LDMDA: "LDMDA", + LDMDA_ZZ: "LDMDA.ZZ", + LDMDB_EQ: "LDMDB.EQ", + LDMDB_NE: "LDMDB.NE", + LDMDB_CS: "LDMDB.CS", + LDMDB_CC: "LDMDB.CC", + LDMDB_MI: "LDMDB.MI", + LDMDB_PL: "LDMDB.PL", + LDMDB_VS: "LDMDB.VS", + LDMDB_VC: "LDMDB.VC", + LDMDB_HI: "LDMDB.HI", + LDMDB_LS: "LDMDB.LS", + LDMDB_GE: "LDMDB.GE", + LDMDB_LT: "LDMDB.LT", + LDMDB_GT: "LDMDB.GT", + LDMDB_LE: "LDMDB.LE", + LDMDB: "LDMDB", + LDMDB_ZZ: "LDMDB.ZZ", + LDMIB_EQ: "LDMIB.EQ", + LDMIB_NE: "LDMIB.NE", + LDMIB_CS: "LDMIB.CS", + LDMIB_CC: "LDMIB.CC", + LDMIB_MI: "LDMIB.MI", + LDMIB_PL: "LDMIB.PL", + LDMIB_VS: "LDMIB.VS", + LDMIB_VC: "LDMIB.VC", + LDMIB_HI: "LDMIB.HI", + LDMIB_LS: "LDMIB.LS", + LDMIB_GE: "LDMIB.GE", + LDMIB_LT: "LDMIB.LT", + LDMIB_GT: "LDMIB.GT", + LDMIB_LE: "LDMIB.LE", + LDMIB: "LDMIB", + LDMIB_ZZ: "LDMIB.ZZ", + LDR_EQ: "LDR.EQ", + LDR_NE: "LDR.NE", + LDR_CS: "LDR.CS", + LDR_CC: "LDR.CC", + LDR_MI: "LDR.MI", + LDR_PL: "LDR.PL", + LDR_VS: "LDR.VS", + LDR_VC: "LDR.VC", + LDR_HI: "LDR.HI", + LDR_LS: "LDR.LS", + LDR_GE: "LDR.GE", + LDR_LT: "LDR.LT", + LDR_GT: "LDR.GT", + LDR_LE: "LDR.LE", + LDR: "LDR", + LDR_ZZ: "LDR.ZZ", + LDRB_EQ: "LDRB.EQ", + LDRB_NE: "LDRB.NE", + LDRB_CS: "LDRB.CS", + LDRB_CC: "LDRB.CC", + LDRB_MI: "LDRB.MI", + LDRB_PL: "LDRB.PL", + LDRB_VS: "LDRB.VS", + LDRB_VC: "LDRB.VC", + LDRB_HI: "LDRB.HI", + LDRB_LS: "LDRB.LS", + LDRB_GE: "LDRB.GE", + LDRB_LT: "LDRB.LT", + LDRB_GT: "LDRB.GT", + LDRB_LE: "LDRB.LE", + LDRB: "LDRB", + LDRB_ZZ: "LDRB.ZZ", + LDRBT_EQ: "LDRBT.EQ", + LDRBT_NE: "LDRBT.NE", + LDRBT_CS: "LDRBT.CS", + LDRBT_CC: "LDRBT.CC", + LDRBT_MI: "LDRBT.MI", + LDRBT_PL: "LDRBT.PL", + LDRBT_VS: "LDRBT.VS", + LDRBT_VC: "LDRBT.VC", + LDRBT_HI: "LDRBT.HI", + LDRBT_LS: "LDRBT.LS", + LDRBT_GE: "LDRBT.GE", + LDRBT_LT: "LDRBT.LT", + LDRBT_GT: "LDRBT.GT", + LDRBT_LE: "LDRBT.LE", + LDRBT: "LDRBT", + LDRBT_ZZ: "LDRBT.ZZ", + LDRD_EQ: "LDRD.EQ", + LDRD_NE: "LDRD.NE", + LDRD_CS: "LDRD.CS", + LDRD_CC: "LDRD.CC", + LDRD_MI: "LDRD.MI", + LDRD_PL: "LDRD.PL", + LDRD_VS: "LDRD.VS", + LDRD_VC: "LDRD.VC", + LDRD_HI: "LDRD.HI", + LDRD_LS: "LDRD.LS", + LDRD_GE: "LDRD.GE", + LDRD_LT: "LDRD.LT", + LDRD_GT: "LDRD.GT", + LDRD_LE: "LDRD.LE", + LDRD: "LDRD", + LDRD_ZZ: "LDRD.ZZ", + LDREX_EQ: "LDREX.EQ", + LDREX_NE: "LDREX.NE", + LDREX_CS: "LDREX.CS", + LDREX_CC: "LDREX.CC", + LDREX_MI: "LDREX.MI", + LDREX_PL: "LDREX.PL", + LDREX_VS: "LDREX.VS", + LDREX_VC: "LDREX.VC", + LDREX_HI: "LDREX.HI", + LDREX_LS: "LDREX.LS", + LDREX_GE: "LDREX.GE", + LDREX_LT: "LDREX.LT", + LDREX_GT: "LDREX.GT", + LDREX_LE: "LDREX.LE", + LDREX: "LDREX", + LDREX_ZZ: "LDREX.ZZ", + LDREXB_EQ: "LDREXB.EQ", + LDREXB_NE: "LDREXB.NE", + LDREXB_CS: "LDREXB.CS", + LDREXB_CC: "LDREXB.CC", + LDREXB_MI: "LDREXB.MI", + LDREXB_PL: "LDREXB.PL", + LDREXB_VS: "LDREXB.VS", + LDREXB_VC: "LDREXB.VC", + LDREXB_HI: "LDREXB.HI", + LDREXB_LS: "LDREXB.LS", + LDREXB_GE: "LDREXB.GE", + LDREXB_LT: "LDREXB.LT", + LDREXB_GT: "LDREXB.GT", + LDREXB_LE: "LDREXB.LE", + LDREXB: "LDREXB", + LDREXB_ZZ: "LDREXB.ZZ", + LDREXD_EQ: "LDREXD.EQ", + LDREXD_NE: "LDREXD.NE", + LDREXD_CS: "LDREXD.CS", + LDREXD_CC: "LDREXD.CC", + LDREXD_MI: "LDREXD.MI", + LDREXD_PL: "LDREXD.PL", + LDREXD_VS: "LDREXD.VS", + LDREXD_VC: "LDREXD.VC", + LDREXD_HI: "LDREXD.HI", + LDREXD_LS: "LDREXD.LS", + LDREXD_GE: "LDREXD.GE", + LDREXD_LT: "LDREXD.LT", + LDREXD_GT: "LDREXD.GT", + LDREXD_LE: "LDREXD.LE", + LDREXD: "LDREXD", + LDREXD_ZZ: "LDREXD.ZZ", + LDREXH_EQ: "LDREXH.EQ", + LDREXH_NE: "LDREXH.NE", + LDREXH_CS: "LDREXH.CS", + LDREXH_CC: "LDREXH.CC", + LDREXH_MI: "LDREXH.MI", + LDREXH_PL: "LDREXH.PL", + LDREXH_VS: "LDREXH.VS", + LDREXH_VC: "LDREXH.VC", + LDREXH_HI: "LDREXH.HI", + LDREXH_LS: "LDREXH.LS", + LDREXH_GE: "LDREXH.GE", + LDREXH_LT: "LDREXH.LT", + LDREXH_GT: "LDREXH.GT", + LDREXH_LE: "LDREXH.LE", + LDREXH: "LDREXH", + LDREXH_ZZ: "LDREXH.ZZ", + LDRH_EQ: "LDRH.EQ", + LDRH_NE: "LDRH.NE", + LDRH_CS: "LDRH.CS", + LDRH_CC: "LDRH.CC", + LDRH_MI: "LDRH.MI", + LDRH_PL: "LDRH.PL", + LDRH_VS: "LDRH.VS", + LDRH_VC: "LDRH.VC", + LDRH_HI: "LDRH.HI", + LDRH_LS: "LDRH.LS", + LDRH_GE: "LDRH.GE", + LDRH_LT: "LDRH.LT", + LDRH_GT: "LDRH.GT", + LDRH_LE: "LDRH.LE", + LDRH: "LDRH", + LDRH_ZZ: "LDRH.ZZ", + LDRHT_EQ: "LDRHT.EQ", + LDRHT_NE: "LDRHT.NE", + LDRHT_CS: "LDRHT.CS", + LDRHT_CC: "LDRHT.CC", + LDRHT_MI: "LDRHT.MI", + LDRHT_PL: "LDRHT.PL", + LDRHT_VS: "LDRHT.VS", + LDRHT_VC: "LDRHT.VC", + LDRHT_HI: "LDRHT.HI", + LDRHT_LS: "LDRHT.LS", + LDRHT_GE: "LDRHT.GE", + LDRHT_LT: "LDRHT.LT", + LDRHT_GT: "LDRHT.GT", + LDRHT_LE: "LDRHT.LE", + LDRHT: "LDRHT", + LDRHT_ZZ: "LDRHT.ZZ", + LDRSB_EQ: "LDRSB.EQ", + LDRSB_NE: "LDRSB.NE", + LDRSB_CS: "LDRSB.CS", + LDRSB_CC: "LDRSB.CC", + LDRSB_MI: "LDRSB.MI", + LDRSB_PL: "LDRSB.PL", + LDRSB_VS: "LDRSB.VS", + LDRSB_VC: "LDRSB.VC", + LDRSB_HI: "LDRSB.HI", + LDRSB_LS: "LDRSB.LS", + LDRSB_GE: "LDRSB.GE", + LDRSB_LT: "LDRSB.LT", + LDRSB_GT: "LDRSB.GT", + LDRSB_LE: "LDRSB.LE", + LDRSB: "LDRSB", + LDRSB_ZZ: "LDRSB.ZZ", + LDRSBT_EQ: "LDRSBT.EQ", + LDRSBT_NE: "LDRSBT.NE", + LDRSBT_CS: "LDRSBT.CS", + LDRSBT_CC: "LDRSBT.CC", + LDRSBT_MI: "LDRSBT.MI", + LDRSBT_PL: "LDRSBT.PL", + LDRSBT_VS: "LDRSBT.VS", + LDRSBT_VC: "LDRSBT.VC", + LDRSBT_HI: "LDRSBT.HI", + LDRSBT_LS: "LDRSBT.LS", + LDRSBT_GE: "LDRSBT.GE", + LDRSBT_LT: "LDRSBT.LT", + LDRSBT_GT: "LDRSBT.GT", + LDRSBT_LE: "LDRSBT.LE", + LDRSBT: "LDRSBT", + LDRSBT_ZZ: "LDRSBT.ZZ", + LDRSH_EQ: "LDRSH.EQ", + LDRSH_NE: "LDRSH.NE", + LDRSH_CS: "LDRSH.CS", + LDRSH_CC: "LDRSH.CC", + LDRSH_MI: "LDRSH.MI", + LDRSH_PL: "LDRSH.PL", + LDRSH_VS: "LDRSH.VS", + LDRSH_VC: "LDRSH.VC", + LDRSH_HI: "LDRSH.HI", + LDRSH_LS: "LDRSH.LS", + LDRSH_GE: "LDRSH.GE", + LDRSH_LT: "LDRSH.LT", + LDRSH_GT: "LDRSH.GT", + LDRSH_LE: "LDRSH.LE", + LDRSH: "LDRSH", + LDRSH_ZZ: "LDRSH.ZZ", + LDRSHT_EQ: "LDRSHT.EQ", + LDRSHT_NE: "LDRSHT.NE", + LDRSHT_CS: "LDRSHT.CS", + LDRSHT_CC: "LDRSHT.CC", + LDRSHT_MI: "LDRSHT.MI", + LDRSHT_PL: "LDRSHT.PL", + LDRSHT_VS: "LDRSHT.VS", + LDRSHT_VC: "LDRSHT.VC", + LDRSHT_HI: "LDRSHT.HI", + LDRSHT_LS: "LDRSHT.LS", + LDRSHT_GE: "LDRSHT.GE", + LDRSHT_LT: "LDRSHT.LT", + LDRSHT_GT: "LDRSHT.GT", + LDRSHT_LE: "LDRSHT.LE", + LDRSHT: "LDRSHT", + LDRSHT_ZZ: "LDRSHT.ZZ", + LDRT_EQ: "LDRT.EQ", + LDRT_NE: "LDRT.NE", + LDRT_CS: "LDRT.CS", + LDRT_CC: "LDRT.CC", + LDRT_MI: "LDRT.MI", + LDRT_PL: "LDRT.PL", + LDRT_VS: "LDRT.VS", + LDRT_VC: "LDRT.VC", + LDRT_HI: "LDRT.HI", + LDRT_LS: "LDRT.LS", + LDRT_GE: "LDRT.GE", + LDRT_LT: "LDRT.LT", + LDRT_GT: "LDRT.GT", + LDRT_LE: "LDRT.LE", + LDRT: "LDRT", + LDRT_ZZ: "LDRT.ZZ", + LSL_EQ: "LSL.EQ", + LSL_NE: "LSL.NE", + LSL_CS: "LSL.CS", + LSL_CC: "LSL.CC", + LSL_MI: "LSL.MI", + LSL_PL: "LSL.PL", + LSL_VS: "LSL.VS", + LSL_VC: "LSL.VC", + LSL_HI: "LSL.HI", + LSL_LS: "LSL.LS", + LSL_GE: "LSL.GE", + LSL_LT: "LSL.LT", + LSL_GT: "LSL.GT", + LSL_LE: "LSL.LE", + LSL: "LSL", + LSL_ZZ: "LSL.ZZ", + LSL_S_EQ: "LSL.S.EQ", + LSL_S_NE: "LSL.S.NE", + LSL_S_CS: "LSL.S.CS", + LSL_S_CC: "LSL.S.CC", + LSL_S_MI: "LSL.S.MI", + LSL_S_PL: "LSL.S.PL", + LSL_S_VS: "LSL.S.VS", + LSL_S_VC: "LSL.S.VC", + LSL_S_HI: "LSL.S.HI", + LSL_S_LS: "LSL.S.LS", + LSL_S_GE: "LSL.S.GE", + LSL_S_LT: "LSL.S.LT", + LSL_S_GT: "LSL.S.GT", + LSL_S_LE: "LSL.S.LE", + LSL_S: "LSL.S", + LSL_S_ZZ: "LSL.S.ZZ", + LSR_EQ: "LSR.EQ", + LSR_NE: "LSR.NE", + LSR_CS: "LSR.CS", + LSR_CC: "LSR.CC", + LSR_MI: "LSR.MI", + LSR_PL: "LSR.PL", + LSR_VS: "LSR.VS", + LSR_VC: "LSR.VC", + LSR_HI: "LSR.HI", + LSR_LS: "LSR.LS", + LSR_GE: "LSR.GE", + LSR_LT: "LSR.LT", + LSR_GT: "LSR.GT", + LSR_LE: "LSR.LE", + LSR: "LSR", + LSR_ZZ: "LSR.ZZ", + LSR_S_EQ: "LSR.S.EQ", + LSR_S_NE: "LSR.S.NE", + LSR_S_CS: "LSR.S.CS", + LSR_S_CC: "LSR.S.CC", + LSR_S_MI: "LSR.S.MI", + LSR_S_PL: "LSR.S.PL", + LSR_S_VS: "LSR.S.VS", + LSR_S_VC: "LSR.S.VC", + LSR_S_HI: "LSR.S.HI", + LSR_S_LS: "LSR.S.LS", + LSR_S_GE: "LSR.S.GE", + LSR_S_LT: "LSR.S.LT", + LSR_S_GT: "LSR.S.GT", + LSR_S_LE: "LSR.S.LE", + LSR_S: "LSR.S", + LSR_S_ZZ: "LSR.S.ZZ", + MLA_EQ: "MLA.EQ", + MLA_NE: "MLA.NE", + MLA_CS: "MLA.CS", + MLA_CC: "MLA.CC", + MLA_MI: "MLA.MI", + MLA_PL: "MLA.PL", + MLA_VS: "MLA.VS", + MLA_VC: "MLA.VC", + MLA_HI: "MLA.HI", + MLA_LS: "MLA.LS", + MLA_GE: "MLA.GE", + MLA_LT: "MLA.LT", + MLA_GT: "MLA.GT", + MLA_LE: "MLA.LE", + MLA: "MLA", + MLA_ZZ: "MLA.ZZ", + MLA_S_EQ: "MLA.S.EQ", + MLA_S_NE: "MLA.S.NE", + MLA_S_CS: "MLA.S.CS", + MLA_S_CC: "MLA.S.CC", + MLA_S_MI: "MLA.S.MI", + MLA_S_PL: "MLA.S.PL", + MLA_S_VS: "MLA.S.VS", + MLA_S_VC: "MLA.S.VC", + MLA_S_HI: "MLA.S.HI", + MLA_S_LS: "MLA.S.LS", + MLA_S_GE: "MLA.S.GE", + MLA_S_LT: "MLA.S.LT", + MLA_S_GT: "MLA.S.GT", + MLA_S_LE: "MLA.S.LE", + MLA_S: "MLA.S", + MLA_S_ZZ: "MLA.S.ZZ", + MLS_EQ: "MLS.EQ", + MLS_NE: "MLS.NE", + MLS_CS: "MLS.CS", + MLS_CC: "MLS.CC", + MLS_MI: "MLS.MI", + MLS_PL: "MLS.PL", + MLS_VS: "MLS.VS", + MLS_VC: "MLS.VC", + MLS_HI: "MLS.HI", + MLS_LS: "MLS.LS", + MLS_GE: "MLS.GE", + MLS_LT: "MLS.LT", + MLS_GT: "MLS.GT", + MLS_LE: "MLS.LE", + MLS: "MLS", + MLS_ZZ: "MLS.ZZ", + MOV_EQ: "MOV.EQ", + MOV_NE: "MOV.NE", + MOV_CS: "MOV.CS", + MOV_CC: "MOV.CC", + MOV_MI: "MOV.MI", + MOV_PL: "MOV.PL", + MOV_VS: "MOV.VS", + MOV_VC: "MOV.VC", + MOV_HI: "MOV.HI", + MOV_LS: "MOV.LS", + MOV_GE: "MOV.GE", + MOV_LT: "MOV.LT", + MOV_GT: "MOV.GT", + MOV_LE: "MOV.LE", + MOV: "MOV", + MOV_ZZ: "MOV.ZZ", + MOV_S_EQ: "MOV.S.EQ", + MOV_S_NE: "MOV.S.NE", + MOV_S_CS: "MOV.S.CS", + MOV_S_CC: "MOV.S.CC", + MOV_S_MI: "MOV.S.MI", + MOV_S_PL: "MOV.S.PL", + MOV_S_VS: "MOV.S.VS", + MOV_S_VC: "MOV.S.VC", + MOV_S_HI: "MOV.S.HI", + MOV_S_LS: "MOV.S.LS", + MOV_S_GE: "MOV.S.GE", + MOV_S_LT: "MOV.S.LT", + MOV_S_GT: "MOV.S.GT", + MOV_S_LE: "MOV.S.LE", + MOV_S: "MOV.S", + MOV_S_ZZ: "MOV.S.ZZ", + MOVT_EQ: "MOVT.EQ", + MOVT_NE: "MOVT.NE", + MOVT_CS: "MOVT.CS", + MOVT_CC: "MOVT.CC", + MOVT_MI: "MOVT.MI", + MOVT_PL: "MOVT.PL", + MOVT_VS: "MOVT.VS", + MOVT_VC: "MOVT.VC", + MOVT_HI: "MOVT.HI", + MOVT_LS: "MOVT.LS", + MOVT_GE: "MOVT.GE", + MOVT_LT: "MOVT.LT", + MOVT_GT: "MOVT.GT", + MOVT_LE: "MOVT.LE", + MOVT: "MOVT", + MOVT_ZZ: "MOVT.ZZ", + MOVW_EQ: "MOVW.EQ", + MOVW_NE: "MOVW.NE", + MOVW_CS: "MOVW.CS", + MOVW_CC: "MOVW.CC", + MOVW_MI: "MOVW.MI", + MOVW_PL: "MOVW.PL", + MOVW_VS: "MOVW.VS", + MOVW_VC: "MOVW.VC", + MOVW_HI: "MOVW.HI", + MOVW_LS: "MOVW.LS", + MOVW_GE: "MOVW.GE", + MOVW_LT: "MOVW.LT", + MOVW_GT: "MOVW.GT", + MOVW_LE: "MOVW.LE", + MOVW: "MOVW", + MOVW_ZZ: "MOVW.ZZ", + MRS_EQ: "MRS.EQ", + MRS_NE: "MRS.NE", + MRS_CS: "MRS.CS", + MRS_CC: "MRS.CC", + MRS_MI: "MRS.MI", + MRS_PL: "MRS.PL", + MRS_VS: "MRS.VS", + MRS_VC: "MRS.VC", + MRS_HI: "MRS.HI", + MRS_LS: "MRS.LS", + MRS_GE: "MRS.GE", + MRS_LT: "MRS.LT", + MRS_GT: "MRS.GT", + MRS_LE: "MRS.LE", + MRS: "MRS", + MRS_ZZ: "MRS.ZZ", + MUL_EQ: "MUL.EQ", + MUL_NE: "MUL.NE", + MUL_CS: "MUL.CS", + MUL_CC: "MUL.CC", + MUL_MI: "MUL.MI", + MUL_PL: "MUL.PL", + MUL_VS: "MUL.VS", + MUL_VC: "MUL.VC", + MUL_HI: "MUL.HI", + MUL_LS: "MUL.LS", + MUL_GE: "MUL.GE", + MUL_LT: "MUL.LT", + MUL_GT: "MUL.GT", + MUL_LE: "MUL.LE", + MUL: "MUL", + MUL_ZZ: "MUL.ZZ", + MUL_S_EQ: "MUL.S.EQ", + MUL_S_NE: "MUL.S.NE", + MUL_S_CS: "MUL.S.CS", + MUL_S_CC: "MUL.S.CC", + MUL_S_MI: "MUL.S.MI", + MUL_S_PL: "MUL.S.PL", + MUL_S_VS: "MUL.S.VS", + MUL_S_VC: "MUL.S.VC", + MUL_S_HI: "MUL.S.HI", + MUL_S_LS: "MUL.S.LS", + MUL_S_GE: "MUL.S.GE", + MUL_S_LT: "MUL.S.LT", + MUL_S_GT: "MUL.S.GT", + MUL_S_LE: "MUL.S.LE", + MUL_S: "MUL.S", + MUL_S_ZZ: "MUL.S.ZZ", + MVN_EQ: "MVN.EQ", + MVN_NE: "MVN.NE", + MVN_CS: "MVN.CS", + MVN_CC: "MVN.CC", + MVN_MI: "MVN.MI", + MVN_PL: "MVN.PL", + MVN_VS: "MVN.VS", + MVN_VC: "MVN.VC", + MVN_HI: "MVN.HI", + MVN_LS: "MVN.LS", + MVN_GE: "MVN.GE", + MVN_LT: "MVN.LT", + MVN_GT: "MVN.GT", + MVN_LE: "MVN.LE", + MVN: "MVN", + MVN_ZZ: "MVN.ZZ", + MVN_S_EQ: "MVN.S.EQ", + MVN_S_NE: "MVN.S.NE", + MVN_S_CS: "MVN.S.CS", + MVN_S_CC: "MVN.S.CC", + MVN_S_MI: "MVN.S.MI", + MVN_S_PL: "MVN.S.PL", + MVN_S_VS: "MVN.S.VS", + MVN_S_VC: "MVN.S.VC", + MVN_S_HI: "MVN.S.HI", + MVN_S_LS: "MVN.S.LS", + MVN_S_GE: "MVN.S.GE", + MVN_S_LT: "MVN.S.LT", + MVN_S_GT: "MVN.S.GT", + MVN_S_LE: "MVN.S.LE", + MVN_S: "MVN.S", + MVN_S_ZZ: "MVN.S.ZZ", + NOP_EQ: "NOP.EQ", + NOP_NE: "NOP.NE", + NOP_CS: "NOP.CS", + NOP_CC: "NOP.CC", + NOP_MI: "NOP.MI", + NOP_PL: "NOP.PL", + NOP_VS: "NOP.VS", + NOP_VC: "NOP.VC", + NOP_HI: "NOP.HI", + NOP_LS: "NOP.LS", + NOP_GE: "NOP.GE", + NOP_LT: "NOP.LT", + NOP_GT: "NOP.GT", + NOP_LE: "NOP.LE", + NOP: "NOP", + NOP_ZZ: "NOP.ZZ", + ORR_EQ: "ORR.EQ", + ORR_NE: "ORR.NE", + ORR_CS: "ORR.CS", + ORR_CC: "ORR.CC", + ORR_MI: "ORR.MI", + ORR_PL: "ORR.PL", + ORR_VS: "ORR.VS", + ORR_VC: "ORR.VC", + ORR_HI: "ORR.HI", + ORR_LS: "ORR.LS", + ORR_GE: "ORR.GE", + ORR_LT: "ORR.LT", + ORR_GT: "ORR.GT", + ORR_LE: "ORR.LE", + ORR: "ORR", + ORR_ZZ: "ORR.ZZ", + ORR_S_EQ: "ORR.S.EQ", + ORR_S_NE: "ORR.S.NE", + ORR_S_CS: "ORR.S.CS", + ORR_S_CC: "ORR.S.CC", + ORR_S_MI: "ORR.S.MI", + ORR_S_PL: "ORR.S.PL", + ORR_S_VS: "ORR.S.VS", + ORR_S_VC: "ORR.S.VC", + ORR_S_HI: "ORR.S.HI", + ORR_S_LS: "ORR.S.LS", + ORR_S_GE: "ORR.S.GE", + ORR_S_LT: "ORR.S.LT", + ORR_S_GT: "ORR.S.GT", + ORR_S_LE: "ORR.S.LE", + ORR_S: "ORR.S", + ORR_S_ZZ: "ORR.S.ZZ", + PKHBT_EQ: "PKHBT.EQ", + PKHBT_NE: "PKHBT.NE", + PKHBT_CS: "PKHBT.CS", + PKHBT_CC: "PKHBT.CC", + PKHBT_MI: "PKHBT.MI", + PKHBT_PL: "PKHBT.PL", + PKHBT_VS: "PKHBT.VS", + PKHBT_VC: "PKHBT.VC", + PKHBT_HI: "PKHBT.HI", + PKHBT_LS: "PKHBT.LS", + PKHBT_GE: "PKHBT.GE", + PKHBT_LT: "PKHBT.LT", + PKHBT_GT: "PKHBT.GT", + PKHBT_LE: "PKHBT.LE", + PKHBT: "PKHBT", + PKHBT_ZZ: "PKHBT.ZZ", + PKHTB_EQ: "PKHTB.EQ", + PKHTB_NE: "PKHTB.NE", + PKHTB_CS: "PKHTB.CS", + PKHTB_CC: "PKHTB.CC", + PKHTB_MI: "PKHTB.MI", + PKHTB_PL: "PKHTB.PL", + PKHTB_VS: "PKHTB.VS", + PKHTB_VC: "PKHTB.VC", + PKHTB_HI: "PKHTB.HI", + PKHTB_LS: "PKHTB.LS", + PKHTB_GE: "PKHTB.GE", + PKHTB_LT: "PKHTB.LT", + PKHTB_GT: "PKHTB.GT", + PKHTB_LE: "PKHTB.LE", + PKHTB: "PKHTB", + PKHTB_ZZ: "PKHTB.ZZ", + PLD_W: "PLD.W", + PLD: "PLD", + PLI: "PLI", + POP_EQ: "POP.EQ", + POP_NE: "POP.NE", + POP_CS: "POP.CS", + POP_CC: "POP.CC", + POP_MI: "POP.MI", + POP_PL: "POP.PL", + POP_VS: "POP.VS", + POP_VC: "POP.VC", + POP_HI: "POP.HI", + POP_LS: "POP.LS", + POP_GE: "POP.GE", + POP_LT: "POP.LT", + POP_GT: "POP.GT", + POP_LE: "POP.LE", + POP: "POP", + POP_ZZ: "POP.ZZ", + PUSH_EQ: "PUSH.EQ", + PUSH_NE: "PUSH.NE", + PUSH_CS: "PUSH.CS", + PUSH_CC: "PUSH.CC", + PUSH_MI: "PUSH.MI", + PUSH_PL: "PUSH.PL", + PUSH_VS: "PUSH.VS", + PUSH_VC: "PUSH.VC", + PUSH_HI: "PUSH.HI", + PUSH_LS: "PUSH.LS", + PUSH_GE: "PUSH.GE", + PUSH_LT: "PUSH.LT", + PUSH_GT: "PUSH.GT", + PUSH_LE: "PUSH.LE", + PUSH: "PUSH", + PUSH_ZZ: "PUSH.ZZ", + QADD_EQ: "QADD.EQ", + QADD_NE: "QADD.NE", + QADD_CS: "QADD.CS", + QADD_CC: "QADD.CC", + QADD_MI: "QADD.MI", + QADD_PL: "QADD.PL", + QADD_VS: "QADD.VS", + QADD_VC: "QADD.VC", + QADD_HI: "QADD.HI", + QADD_LS: "QADD.LS", + QADD_GE: "QADD.GE", + QADD_LT: "QADD.LT", + QADD_GT: "QADD.GT", + QADD_LE: "QADD.LE", + QADD: "QADD", + QADD_ZZ: "QADD.ZZ", + QADD16_EQ: "QADD16.EQ", + QADD16_NE: "QADD16.NE", + QADD16_CS: "QADD16.CS", + QADD16_CC: "QADD16.CC", + QADD16_MI: "QADD16.MI", + QADD16_PL: "QADD16.PL", + QADD16_VS: "QADD16.VS", + QADD16_VC: "QADD16.VC", + QADD16_HI: "QADD16.HI", + QADD16_LS: "QADD16.LS", + QADD16_GE: "QADD16.GE", + QADD16_LT: "QADD16.LT", + QADD16_GT: "QADD16.GT", + QADD16_LE: "QADD16.LE", + QADD16: "QADD16", + QADD16_ZZ: "QADD16.ZZ", + QADD8_EQ: "QADD8.EQ", + QADD8_NE: "QADD8.NE", + QADD8_CS: "QADD8.CS", + QADD8_CC: "QADD8.CC", + QADD8_MI: "QADD8.MI", + QADD8_PL: "QADD8.PL", + QADD8_VS: "QADD8.VS", + QADD8_VC: "QADD8.VC", + QADD8_HI: "QADD8.HI", + QADD8_LS: "QADD8.LS", + QADD8_GE: "QADD8.GE", + QADD8_LT: "QADD8.LT", + QADD8_GT: "QADD8.GT", + QADD8_LE: "QADD8.LE", + QADD8: "QADD8", + QADD8_ZZ: "QADD8.ZZ", + QASX_EQ: "QASX.EQ", + QASX_NE: "QASX.NE", + QASX_CS: "QASX.CS", + QASX_CC: "QASX.CC", + QASX_MI: "QASX.MI", + QASX_PL: "QASX.PL", + QASX_VS: "QASX.VS", + QASX_VC: "QASX.VC", + QASX_HI: "QASX.HI", + QASX_LS: "QASX.LS", + QASX_GE: "QASX.GE", + QASX_LT: "QASX.LT", + QASX_GT: "QASX.GT", + QASX_LE: "QASX.LE", + QASX: "QASX", + QASX_ZZ: "QASX.ZZ", + QDADD_EQ: "QDADD.EQ", + QDADD_NE: "QDADD.NE", + QDADD_CS: "QDADD.CS", + QDADD_CC: "QDADD.CC", + QDADD_MI: "QDADD.MI", + QDADD_PL: "QDADD.PL", + QDADD_VS: "QDADD.VS", + QDADD_VC: "QDADD.VC", + QDADD_HI: "QDADD.HI", + QDADD_LS: "QDADD.LS", + QDADD_GE: "QDADD.GE", + QDADD_LT: "QDADD.LT", + QDADD_GT: "QDADD.GT", + QDADD_LE: "QDADD.LE", + QDADD: "QDADD", + QDADD_ZZ: "QDADD.ZZ", + QDSUB_EQ: "QDSUB.EQ", + QDSUB_NE: "QDSUB.NE", + QDSUB_CS: "QDSUB.CS", + QDSUB_CC: "QDSUB.CC", + QDSUB_MI: "QDSUB.MI", + QDSUB_PL: "QDSUB.PL", + QDSUB_VS: "QDSUB.VS", + QDSUB_VC: "QDSUB.VC", + QDSUB_HI: "QDSUB.HI", + QDSUB_LS: "QDSUB.LS", + QDSUB_GE: "QDSUB.GE", + QDSUB_LT: "QDSUB.LT", + QDSUB_GT: "QDSUB.GT", + QDSUB_LE: "QDSUB.LE", + QDSUB: "QDSUB", + QDSUB_ZZ: "QDSUB.ZZ", + QSAX_EQ: "QSAX.EQ", + QSAX_NE: "QSAX.NE", + QSAX_CS: "QSAX.CS", + QSAX_CC: "QSAX.CC", + QSAX_MI: "QSAX.MI", + QSAX_PL: "QSAX.PL", + QSAX_VS: "QSAX.VS", + QSAX_VC: "QSAX.VC", + QSAX_HI: "QSAX.HI", + QSAX_LS: "QSAX.LS", + QSAX_GE: "QSAX.GE", + QSAX_LT: "QSAX.LT", + QSAX_GT: "QSAX.GT", + QSAX_LE: "QSAX.LE", + QSAX: "QSAX", + QSAX_ZZ: "QSAX.ZZ", + QSUB_EQ: "QSUB.EQ", + QSUB_NE: "QSUB.NE", + QSUB_CS: "QSUB.CS", + QSUB_CC: "QSUB.CC", + QSUB_MI: "QSUB.MI", + QSUB_PL: "QSUB.PL", + QSUB_VS: "QSUB.VS", + QSUB_VC: "QSUB.VC", + QSUB_HI: "QSUB.HI", + QSUB_LS: "QSUB.LS", + QSUB_GE: "QSUB.GE", + QSUB_LT: "QSUB.LT", + QSUB_GT: "QSUB.GT", + QSUB_LE: "QSUB.LE", + QSUB: "QSUB", + QSUB_ZZ: "QSUB.ZZ", + QSUB16_EQ: "QSUB16.EQ", + QSUB16_NE: "QSUB16.NE", + QSUB16_CS: "QSUB16.CS", + QSUB16_CC: "QSUB16.CC", + QSUB16_MI: "QSUB16.MI", + QSUB16_PL: "QSUB16.PL", + QSUB16_VS: "QSUB16.VS", + QSUB16_VC: "QSUB16.VC", + QSUB16_HI: "QSUB16.HI", + QSUB16_LS: "QSUB16.LS", + QSUB16_GE: "QSUB16.GE", + QSUB16_LT: "QSUB16.LT", + QSUB16_GT: "QSUB16.GT", + QSUB16_LE: "QSUB16.LE", + QSUB16: "QSUB16", + QSUB16_ZZ: "QSUB16.ZZ", + QSUB8_EQ: "QSUB8.EQ", + QSUB8_NE: "QSUB8.NE", + QSUB8_CS: "QSUB8.CS", + QSUB8_CC: "QSUB8.CC", + QSUB8_MI: "QSUB8.MI", + QSUB8_PL: "QSUB8.PL", + QSUB8_VS: "QSUB8.VS", + QSUB8_VC: "QSUB8.VC", + QSUB8_HI: "QSUB8.HI", + QSUB8_LS: "QSUB8.LS", + QSUB8_GE: "QSUB8.GE", + QSUB8_LT: "QSUB8.LT", + QSUB8_GT: "QSUB8.GT", + QSUB8_LE: "QSUB8.LE", + QSUB8: "QSUB8", + QSUB8_ZZ: "QSUB8.ZZ", + RBIT_EQ: "RBIT.EQ", + RBIT_NE: "RBIT.NE", + RBIT_CS: "RBIT.CS", + RBIT_CC: "RBIT.CC", + RBIT_MI: "RBIT.MI", + RBIT_PL: "RBIT.PL", + RBIT_VS: "RBIT.VS", + RBIT_VC: "RBIT.VC", + RBIT_HI: "RBIT.HI", + RBIT_LS: "RBIT.LS", + RBIT_GE: "RBIT.GE", + RBIT_LT: "RBIT.LT", + RBIT_GT: "RBIT.GT", + RBIT_LE: "RBIT.LE", + RBIT: "RBIT", + RBIT_ZZ: "RBIT.ZZ", + REV_EQ: "REV.EQ", + REV_NE: "REV.NE", + REV_CS: "REV.CS", + REV_CC: "REV.CC", + REV_MI: "REV.MI", + REV_PL: "REV.PL", + REV_VS: "REV.VS", + REV_VC: "REV.VC", + REV_HI: "REV.HI", + REV_LS: "REV.LS", + REV_GE: "REV.GE", + REV_LT: "REV.LT", + REV_GT: "REV.GT", + REV_LE: "REV.LE", + REV: "REV", + REV_ZZ: "REV.ZZ", + REV16_EQ: "REV16.EQ", + REV16_NE: "REV16.NE", + REV16_CS: "REV16.CS", + REV16_CC: "REV16.CC", + REV16_MI: "REV16.MI", + REV16_PL: "REV16.PL", + REV16_VS: "REV16.VS", + REV16_VC: "REV16.VC", + REV16_HI: "REV16.HI", + REV16_LS: "REV16.LS", + REV16_GE: "REV16.GE", + REV16_LT: "REV16.LT", + REV16_GT: "REV16.GT", + REV16_LE: "REV16.LE", + REV16: "REV16", + REV16_ZZ: "REV16.ZZ", + REVSH_EQ: "REVSH.EQ", + REVSH_NE: "REVSH.NE", + REVSH_CS: "REVSH.CS", + REVSH_CC: "REVSH.CC", + REVSH_MI: "REVSH.MI", + REVSH_PL: "REVSH.PL", + REVSH_VS: "REVSH.VS", + REVSH_VC: "REVSH.VC", + REVSH_HI: "REVSH.HI", + REVSH_LS: "REVSH.LS", + REVSH_GE: "REVSH.GE", + REVSH_LT: "REVSH.LT", + REVSH_GT: "REVSH.GT", + REVSH_LE: "REVSH.LE", + REVSH: "REVSH", + REVSH_ZZ: "REVSH.ZZ", + ROR_EQ: "ROR.EQ", + ROR_NE: "ROR.NE", + ROR_CS: "ROR.CS", + ROR_CC: "ROR.CC", + ROR_MI: "ROR.MI", + ROR_PL: "ROR.PL", + ROR_VS: "ROR.VS", + ROR_VC: "ROR.VC", + ROR_HI: "ROR.HI", + ROR_LS: "ROR.LS", + ROR_GE: "ROR.GE", + ROR_LT: "ROR.LT", + ROR_GT: "ROR.GT", + ROR_LE: "ROR.LE", + ROR: "ROR", + ROR_ZZ: "ROR.ZZ", + ROR_S_EQ: "ROR.S.EQ", + ROR_S_NE: "ROR.S.NE", + ROR_S_CS: "ROR.S.CS", + ROR_S_CC: "ROR.S.CC", + ROR_S_MI: "ROR.S.MI", + ROR_S_PL: "ROR.S.PL", + ROR_S_VS: "ROR.S.VS", + ROR_S_VC: "ROR.S.VC", + ROR_S_HI: "ROR.S.HI", + ROR_S_LS: "ROR.S.LS", + ROR_S_GE: "ROR.S.GE", + ROR_S_LT: "ROR.S.LT", + ROR_S_GT: "ROR.S.GT", + ROR_S_LE: "ROR.S.LE", + ROR_S: "ROR.S", + ROR_S_ZZ: "ROR.S.ZZ", + RRX_EQ: "RRX.EQ", + RRX_NE: "RRX.NE", + RRX_CS: "RRX.CS", + RRX_CC: "RRX.CC", + RRX_MI: "RRX.MI", + RRX_PL: "RRX.PL", + RRX_VS: "RRX.VS", + RRX_VC: "RRX.VC", + RRX_HI: "RRX.HI", + RRX_LS: "RRX.LS", + RRX_GE: "RRX.GE", + RRX_LT: "RRX.LT", + RRX_GT: "RRX.GT", + RRX_LE: "RRX.LE", + RRX: "RRX", + RRX_ZZ: "RRX.ZZ", + RRX_S_EQ: "RRX.S.EQ", + RRX_S_NE: "RRX.S.NE", + RRX_S_CS: "RRX.S.CS", + RRX_S_CC: "RRX.S.CC", + RRX_S_MI: "RRX.S.MI", + RRX_S_PL: "RRX.S.PL", + RRX_S_VS: "RRX.S.VS", + RRX_S_VC: "RRX.S.VC", + RRX_S_HI: "RRX.S.HI", + RRX_S_LS: "RRX.S.LS", + RRX_S_GE: "RRX.S.GE", + RRX_S_LT: "RRX.S.LT", + RRX_S_GT: "RRX.S.GT", + RRX_S_LE: "RRX.S.LE", + RRX_S: "RRX.S", + RRX_S_ZZ: "RRX.S.ZZ", + RSB_EQ: "RSB.EQ", + RSB_NE: "RSB.NE", + RSB_CS: "RSB.CS", + RSB_CC: "RSB.CC", + RSB_MI: "RSB.MI", + RSB_PL: "RSB.PL", + RSB_VS: "RSB.VS", + RSB_VC: "RSB.VC", + RSB_HI: "RSB.HI", + RSB_LS: "RSB.LS", + RSB_GE: "RSB.GE", + RSB_LT: "RSB.LT", + RSB_GT: "RSB.GT", + RSB_LE: "RSB.LE", + RSB: "RSB", + RSB_ZZ: "RSB.ZZ", + RSB_S_EQ: "RSB.S.EQ", + RSB_S_NE: "RSB.S.NE", + RSB_S_CS: "RSB.S.CS", + RSB_S_CC: "RSB.S.CC", + RSB_S_MI: "RSB.S.MI", + RSB_S_PL: "RSB.S.PL", + RSB_S_VS: "RSB.S.VS", + RSB_S_VC: "RSB.S.VC", + RSB_S_HI: "RSB.S.HI", + RSB_S_LS: "RSB.S.LS", + RSB_S_GE: "RSB.S.GE", + RSB_S_LT: "RSB.S.LT", + RSB_S_GT: "RSB.S.GT", + RSB_S_LE: "RSB.S.LE", + RSB_S: "RSB.S", + RSB_S_ZZ: "RSB.S.ZZ", + RSC_EQ: "RSC.EQ", + RSC_NE: "RSC.NE", + RSC_CS: "RSC.CS", + RSC_CC: "RSC.CC", + RSC_MI: "RSC.MI", + RSC_PL: "RSC.PL", + RSC_VS: "RSC.VS", + RSC_VC: "RSC.VC", + RSC_HI: "RSC.HI", + RSC_LS: "RSC.LS", + RSC_GE: "RSC.GE", + RSC_LT: "RSC.LT", + RSC_GT: "RSC.GT", + RSC_LE: "RSC.LE", + RSC: "RSC", + RSC_ZZ: "RSC.ZZ", + RSC_S_EQ: "RSC.S.EQ", + RSC_S_NE: "RSC.S.NE", + RSC_S_CS: "RSC.S.CS", + RSC_S_CC: "RSC.S.CC", + RSC_S_MI: "RSC.S.MI", + RSC_S_PL: "RSC.S.PL", + RSC_S_VS: "RSC.S.VS", + RSC_S_VC: "RSC.S.VC", + RSC_S_HI: "RSC.S.HI", + RSC_S_LS: "RSC.S.LS", + RSC_S_GE: "RSC.S.GE", + RSC_S_LT: "RSC.S.LT", + RSC_S_GT: "RSC.S.GT", + RSC_S_LE: "RSC.S.LE", + RSC_S: "RSC.S", + RSC_S_ZZ: "RSC.S.ZZ", + SADD16_EQ: "SADD16.EQ", + SADD16_NE: "SADD16.NE", + SADD16_CS: "SADD16.CS", + SADD16_CC: "SADD16.CC", + SADD16_MI: "SADD16.MI", + SADD16_PL: "SADD16.PL", + SADD16_VS: "SADD16.VS", + SADD16_VC: "SADD16.VC", + SADD16_HI: "SADD16.HI", + SADD16_LS: "SADD16.LS", + SADD16_GE: "SADD16.GE", + SADD16_LT: "SADD16.LT", + SADD16_GT: "SADD16.GT", + SADD16_LE: "SADD16.LE", + SADD16: "SADD16", + SADD16_ZZ: "SADD16.ZZ", + SADD8_EQ: "SADD8.EQ", + SADD8_NE: "SADD8.NE", + SADD8_CS: "SADD8.CS", + SADD8_CC: "SADD8.CC", + SADD8_MI: "SADD8.MI", + SADD8_PL: "SADD8.PL", + SADD8_VS: "SADD8.VS", + SADD8_VC: "SADD8.VC", + SADD8_HI: "SADD8.HI", + SADD8_LS: "SADD8.LS", + SADD8_GE: "SADD8.GE", + SADD8_LT: "SADD8.LT", + SADD8_GT: "SADD8.GT", + SADD8_LE: "SADD8.LE", + SADD8: "SADD8", + SADD8_ZZ: "SADD8.ZZ", + SASX_EQ: "SASX.EQ", + SASX_NE: "SASX.NE", + SASX_CS: "SASX.CS", + SASX_CC: "SASX.CC", + SASX_MI: "SASX.MI", + SASX_PL: "SASX.PL", + SASX_VS: "SASX.VS", + SASX_VC: "SASX.VC", + SASX_HI: "SASX.HI", + SASX_LS: "SASX.LS", + SASX_GE: "SASX.GE", + SASX_LT: "SASX.LT", + SASX_GT: "SASX.GT", + SASX_LE: "SASX.LE", + SASX: "SASX", + SASX_ZZ: "SASX.ZZ", + SBC_EQ: "SBC.EQ", + SBC_NE: "SBC.NE", + SBC_CS: "SBC.CS", + SBC_CC: "SBC.CC", + SBC_MI: "SBC.MI", + SBC_PL: "SBC.PL", + SBC_VS: "SBC.VS", + SBC_VC: "SBC.VC", + SBC_HI: "SBC.HI", + SBC_LS: "SBC.LS", + SBC_GE: "SBC.GE", + SBC_LT: "SBC.LT", + SBC_GT: "SBC.GT", + SBC_LE: "SBC.LE", + SBC: "SBC", + SBC_ZZ: "SBC.ZZ", + SBC_S_EQ: "SBC.S.EQ", + SBC_S_NE: "SBC.S.NE", + SBC_S_CS: "SBC.S.CS", + SBC_S_CC: "SBC.S.CC", + SBC_S_MI: "SBC.S.MI", + SBC_S_PL: "SBC.S.PL", + SBC_S_VS: "SBC.S.VS", + SBC_S_VC: "SBC.S.VC", + SBC_S_HI: "SBC.S.HI", + SBC_S_LS: "SBC.S.LS", + SBC_S_GE: "SBC.S.GE", + SBC_S_LT: "SBC.S.LT", + SBC_S_GT: "SBC.S.GT", + SBC_S_LE: "SBC.S.LE", + SBC_S: "SBC.S", + SBC_S_ZZ: "SBC.S.ZZ", + SBFX_EQ: "SBFX.EQ", + SBFX_NE: "SBFX.NE", + SBFX_CS: "SBFX.CS", + SBFX_CC: "SBFX.CC", + SBFX_MI: "SBFX.MI", + SBFX_PL: "SBFX.PL", + SBFX_VS: "SBFX.VS", + SBFX_VC: "SBFX.VC", + SBFX_HI: "SBFX.HI", + SBFX_LS: "SBFX.LS", + SBFX_GE: "SBFX.GE", + SBFX_LT: "SBFX.LT", + SBFX_GT: "SBFX.GT", + SBFX_LE: "SBFX.LE", + SBFX: "SBFX", + SBFX_ZZ: "SBFX.ZZ", + SEL_EQ: "SEL.EQ", + SEL_NE: "SEL.NE", + SEL_CS: "SEL.CS", + SEL_CC: "SEL.CC", + SEL_MI: "SEL.MI", + SEL_PL: "SEL.PL", + SEL_VS: "SEL.VS", + SEL_VC: "SEL.VC", + SEL_HI: "SEL.HI", + SEL_LS: "SEL.LS", + SEL_GE: "SEL.GE", + SEL_LT: "SEL.LT", + SEL_GT: "SEL.GT", + SEL_LE: "SEL.LE", + SEL: "SEL", + SEL_ZZ: "SEL.ZZ", + SETEND: "SETEND", + SEV_EQ: "SEV.EQ", + SEV_NE: "SEV.NE", + SEV_CS: "SEV.CS", + SEV_CC: "SEV.CC", + SEV_MI: "SEV.MI", + SEV_PL: "SEV.PL", + SEV_VS: "SEV.VS", + SEV_VC: "SEV.VC", + SEV_HI: "SEV.HI", + SEV_LS: "SEV.LS", + SEV_GE: "SEV.GE", + SEV_LT: "SEV.LT", + SEV_GT: "SEV.GT", + SEV_LE: "SEV.LE", + SEV: "SEV", + SEV_ZZ: "SEV.ZZ", + SHADD16_EQ: "SHADD16.EQ", + SHADD16_NE: "SHADD16.NE", + SHADD16_CS: "SHADD16.CS", + SHADD16_CC: "SHADD16.CC", + SHADD16_MI: "SHADD16.MI", + SHADD16_PL: "SHADD16.PL", + SHADD16_VS: "SHADD16.VS", + SHADD16_VC: "SHADD16.VC", + SHADD16_HI: "SHADD16.HI", + SHADD16_LS: "SHADD16.LS", + SHADD16_GE: "SHADD16.GE", + SHADD16_LT: "SHADD16.LT", + SHADD16_GT: "SHADD16.GT", + SHADD16_LE: "SHADD16.LE", + SHADD16: "SHADD16", + SHADD16_ZZ: "SHADD16.ZZ", + SHADD8_EQ: "SHADD8.EQ", + SHADD8_NE: "SHADD8.NE", + SHADD8_CS: "SHADD8.CS", + SHADD8_CC: "SHADD8.CC", + SHADD8_MI: "SHADD8.MI", + SHADD8_PL: "SHADD8.PL", + SHADD8_VS: "SHADD8.VS", + SHADD8_VC: "SHADD8.VC", + SHADD8_HI: "SHADD8.HI", + SHADD8_LS: "SHADD8.LS", + SHADD8_GE: "SHADD8.GE", + SHADD8_LT: "SHADD8.LT", + SHADD8_GT: "SHADD8.GT", + SHADD8_LE: "SHADD8.LE", + SHADD8: "SHADD8", + SHADD8_ZZ: "SHADD8.ZZ", + SHASX_EQ: "SHASX.EQ", + SHASX_NE: "SHASX.NE", + SHASX_CS: "SHASX.CS", + SHASX_CC: "SHASX.CC", + SHASX_MI: "SHASX.MI", + SHASX_PL: "SHASX.PL", + SHASX_VS: "SHASX.VS", + SHASX_VC: "SHASX.VC", + SHASX_HI: "SHASX.HI", + SHASX_LS: "SHASX.LS", + SHASX_GE: "SHASX.GE", + SHASX_LT: "SHASX.LT", + SHASX_GT: "SHASX.GT", + SHASX_LE: "SHASX.LE", + SHASX: "SHASX", + SHASX_ZZ: "SHASX.ZZ", + SHSAX_EQ: "SHSAX.EQ", + SHSAX_NE: "SHSAX.NE", + SHSAX_CS: "SHSAX.CS", + SHSAX_CC: "SHSAX.CC", + SHSAX_MI: "SHSAX.MI", + SHSAX_PL: "SHSAX.PL", + SHSAX_VS: "SHSAX.VS", + SHSAX_VC: "SHSAX.VC", + SHSAX_HI: "SHSAX.HI", + SHSAX_LS: "SHSAX.LS", + SHSAX_GE: "SHSAX.GE", + SHSAX_LT: "SHSAX.LT", + SHSAX_GT: "SHSAX.GT", + SHSAX_LE: "SHSAX.LE", + SHSAX: "SHSAX", + SHSAX_ZZ: "SHSAX.ZZ", + SHSUB16_EQ: "SHSUB16.EQ", + SHSUB16_NE: "SHSUB16.NE", + SHSUB16_CS: "SHSUB16.CS", + SHSUB16_CC: "SHSUB16.CC", + SHSUB16_MI: "SHSUB16.MI", + SHSUB16_PL: "SHSUB16.PL", + SHSUB16_VS: "SHSUB16.VS", + SHSUB16_VC: "SHSUB16.VC", + SHSUB16_HI: "SHSUB16.HI", + SHSUB16_LS: "SHSUB16.LS", + SHSUB16_GE: "SHSUB16.GE", + SHSUB16_LT: "SHSUB16.LT", + SHSUB16_GT: "SHSUB16.GT", + SHSUB16_LE: "SHSUB16.LE", + SHSUB16: "SHSUB16", + SHSUB16_ZZ: "SHSUB16.ZZ", + SHSUB8_EQ: "SHSUB8.EQ", + SHSUB8_NE: "SHSUB8.NE", + SHSUB8_CS: "SHSUB8.CS", + SHSUB8_CC: "SHSUB8.CC", + SHSUB8_MI: "SHSUB8.MI", + SHSUB8_PL: "SHSUB8.PL", + SHSUB8_VS: "SHSUB8.VS", + SHSUB8_VC: "SHSUB8.VC", + SHSUB8_HI: "SHSUB8.HI", + SHSUB8_LS: "SHSUB8.LS", + SHSUB8_GE: "SHSUB8.GE", + SHSUB8_LT: "SHSUB8.LT", + SHSUB8_GT: "SHSUB8.GT", + SHSUB8_LE: "SHSUB8.LE", + SHSUB8: "SHSUB8", + SHSUB8_ZZ: "SHSUB8.ZZ", + SMLABB_EQ: "SMLABB.EQ", + SMLABB_NE: "SMLABB.NE", + SMLABB_CS: "SMLABB.CS", + SMLABB_CC: "SMLABB.CC", + SMLABB_MI: "SMLABB.MI", + SMLABB_PL: "SMLABB.PL", + SMLABB_VS: "SMLABB.VS", + SMLABB_VC: "SMLABB.VC", + SMLABB_HI: "SMLABB.HI", + SMLABB_LS: "SMLABB.LS", + SMLABB_GE: "SMLABB.GE", + SMLABB_LT: "SMLABB.LT", + SMLABB_GT: "SMLABB.GT", + SMLABB_LE: "SMLABB.LE", + SMLABB: "SMLABB", + SMLABB_ZZ: "SMLABB.ZZ", + SMLABT_EQ: "SMLABT.EQ", + SMLABT_NE: "SMLABT.NE", + SMLABT_CS: "SMLABT.CS", + SMLABT_CC: "SMLABT.CC", + SMLABT_MI: "SMLABT.MI", + SMLABT_PL: "SMLABT.PL", + SMLABT_VS: "SMLABT.VS", + SMLABT_VC: "SMLABT.VC", + SMLABT_HI: "SMLABT.HI", + SMLABT_LS: "SMLABT.LS", + SMLABT_GE: "SMLABT.GE", + SMLABT_LT: "SMLABT.LT", + SMLABT_GT: "SMLABT.GT", + SMLABT_LE: "SMLABT.LE", + SMLABT: "SMLABT", + SMLABT_ZZ: "SMLABT.ZZ", + SMLATB_EQ: "SMLATB.EQ", + SMLATB_NE: "SMLATB.NE", + SMLATB_CS: "SMLATB.CS", + SMLATB_CC: "SMLATB.CC", + SMLATB_MI: "SMLATB.MI", + SMLATB_PL: "SMLATB.PL", + SMLATB_VS: "SMLATB.VS", + SMLATB_VC: "SMLATB.VC", + SMLATB_HI: "SMLATB.HI", + SMLATB_LS: "SMLATB.LS", + SMLATB_GE: "SMLATB.GE", + SMLATB_LT: "SMLATB.LT", + SMLATB_GT: "SMLATB.GT", + SMLATB_LE: "SMLATB.LE", + SMLATB: "SMLATB", + SMLATB_ZZ: "SMLATB.ZZ", + SMLATT_EQ: "SMLATT.EQ", + SMLATT_NE: "SMLATT.NE", + SMLATT_CS: "SMLATT.CS", + SMLATT_CC: "SMLATT.CC", + SMLATT_MI: "SMLATT.MI", + SMLATT_PL: "SMLATT.PL", + SMLATT_VS: "SMLATT.VS", + SMLATT_VC: "SMLATT.VC", + SMLATT_HI: "SMLATT.HI", + SMLATT_LS: "SMLATT.LS", + SMLATT_GE: "SMLATT.GE", + SMLATT_LT: "SMLATT.LT", + SMLATT_GT: "SMLATT.GT", + SMLATT_LE: "SMLATT.LE", + SMLATT: "SMLATT", + SMLATT_ZZ: "SMLATT.ZZ", + SMLAD_EQ: "SMLAD.EQ", + SMLAD_NE: "SMLAD.NE", + SMLAD_CS: "SMLAD.CS", + SMLAD_CC: "SMLAD.CC", + SMLAD_MI: "SMLAD.MI", + SMLAD_PL: "SMLAD.PL", + SMLAD_VS: "SMLAD.VS", + SMLAD_VC: "SMLAD.VC", + SMLAD_HI: "SMLAD.HI", + SMLAD_LS: "SMLAD.LS", + SMLAD_GE: "SMLAD.GE", + SMLAD_LT: "SMLAD.LT", + SMLAD_GT: "SMLAD.GT", + SMLAD_LE: "SMLAD.LE", + SMLAD: "SMLAD", + SMLAD_ZZ: "SMLAD.ZZ", + SMLAD_X_EQ: "SMLAD.X.EQ", + SMLAD_X_NE: "SMLAD.X.NE", + SMLAD_X_CS: "SMLAD.X.CS", + SMLAD_X_CC: "SMLAD.X.CC", + SMLAD_X_MI: "SMLAD.X.MI", + SMLAD_X_PL: "SMLAD.X.PL", + SMLAD_X_VS: "SMLAD.X.VS", + SMLAD_X_VC: "SMLAD.X.VC", + SMLAD_X_HI: "SMLAD.X.HI", + SMLAD_X_LS: "SMLAD.X.LS", + SMLAD_X_GE: "SMLAD.X.GE", + SMLAD_X_LT: "SMLAD.X.LT", + SMLAD_X_GT: "SMLAD.X.GT", + SMLAD_X_LE: "SMLAD.X.LE", + SMLAD_X: "SMLAD.X", + SMLAD_X_ZZ: "SMLAD.X.ZZ", + SMLAL_EQ: "SMLAL.EQ", + SMLAL_NE: "SMLAL.NE", + SMLAL_CS: "SMLAL.CS", + SMLAL_CC: "SMLAL.CC", + SMLAL_MI: "SMLAL.MI", + SMLAL_PL: "SMLAL.PL", + SMLAL_VS: "SMLAL.VS", + SMLAL_VC: "SMLAL.VC", + SMLAL_HI: "SMLAL.HI", + SMLAL_LS: "SMLAL.LS", + SMLAL_GE: "SMLAL.GE", + SMLAL_LT: "SMLAL.LT", + SMLAL_GT: "SMLAL.GT", + SMLAL_LE: "SMLAL.LE", + SMLAL: "SMLAL", + SMLAL_ZZ: "SMLAL.ZZ", + SMLAL_S_EQ: "SMLAL.S.EQ", + SMLAL_S_NE: "SMLAL.S.NE", + SMLAL_S_CS: "SMLAL.S.CS", + SMLAL_S_CC: "SMLAL.S.CC", + SMLAL_S_MI: "SMLAL.S.MI", + SMLAL_S_PL: "SMLAL.S.PL", + SMLAL_S_VS: "SMLAL.S.VS", + SMLAL_S_VC: "SMLAL.S.VC", + SMLAL_S_HI: "SMLAL.S.HI", + SMLAL_S_LS: "SMLAL.S.LS", + SMLAL_S_GE: "SMLAL.S.GE", + SMLAL_S_LT: "SMLAL.S.LT", + SMLAL_S_GT: "SMLAL.S.GT", + SMLAL_S_LE: "SMLAL.S.LE", + SMLAL_S: "SMLAL.S", + SMLAL_S_ZZ: "SMLAL.S.ZZ", + SMLALBB_EQ: "SMLALBB.EQ", + SMLALBB_NE: "SMLALBB.NE", + SMLALBB_CS: "SMLALBB.CS", + SMLALBB_CC: "SMLALBB.CC", + SMLALBB_MI: "SMLALBB.MI", + SMLALBB_PL: "SMLALBB.PL", + SMLALBB_VS: "SMLALBB.VS", + SMLALBB_VC: "SMLALBB.VC", + SMLALBB_HI: "SMLALBB.HI", + SMLALBB_LS: "SMLALBB.LS", + SMLALBB_GE: "SMLALBB.GE", + SMLALBB_LT: "SMLALBB.LT", + SMLALBB_GT: "SMLALBB.GT", + SMLALBB_LE: "SMLALBB.LE", + SMLALBB: "SMLALBB", + SMLALBB_ZZ: "SMLALBB.ZZ", + SMLALBT_EQ: "SMLALBT.EQ", + SMLALBT_NE: "SMLALBT.NE", + SMLALBT_CS: "SMLALBT.CS", + SMLALBT_CC: "SMLALBT.CC", + SMLALBT_MI: "SMLALBT.MI", + SMLALBT_PL: "SMLALBT.PL", + SMLALBT_VS: "SMLALBT.VS", + SMLALBT_VC: "SMLALBT.VC", + SMLALBT_HI: "SMLALBT.HI", + SMLALBT_LS: "SMLALBT.LS", + SMLALBT_GE: "SMLALBT.GE", + SMLALBT_LT: "SMLALBT.LT", + SMLALBT_GT: "SMLALBT.GT", + SMLALBT_LE: "SMLALBT.LE", + SMLALBT: "SMLALBT", + SMLALBT_ZZ: "SMLALBT.ZZ", + SMLALTB_EQ: "SMLALTB.EQ", + SMLALTB_NE: "SMLALTB.NE", + SMLALTB_CS: "SMLALTB.CS", + SMLALTB_CC: "SMLALTB.CC", + SMLALTB_MI: "SMLALTB.MI", + SMLALTB_PL: "SMLALTB.PL", + SMLALTB_VS: "SMLALTB.VS", + SMLALTB_VC: "SMLALTB.VC", + SMLALTB_HI: "SMLALTB.HI", + SMLALTB_LS: "SMLALTB.LS", + SMLALTB_GE: "SMLALTB.GE", + SMLALTB_LT: "SMLALTB.LT", + SMLALTB_GT: "SMLALTB.GT", + SMLALTB_LE: "SMLALTB.LE", + SMLALTB: "SMLALTB", + SMLALTB_ZZ: "SMLALTB.ZZ", + SMLALTT_EQ: "SMLALTT.EQ", + SMLALTT_NE: "SMLALTT.NE", + SMLALTT_CS: "SMLALTT.CS", + SMLALTT_CC: "SMLALTT.CC", + SMLALTT_MI: "SMLALTT.MI", + SMLALTT_PL: "SMLALTT.PL", + SMLALTT_VS: "SMLALTT.VS", + SMLALTT_VC: "SMLALTT.VC", + SMLALTT_HI: "SMLALTT.HI", + SMLALTT_LS: "SMLALTT.LS", + SMLALTT_GE: "SMLALTT.GE", + SMLALTT_LT: "SMLALTT.LT", + SMLALTT_GT: "SMLALTT.GT", + SMLALTT_LE: "SMLALTT.LE", + SMLALTT: "SMLALTT", + SMLALTT_ZZ: "SMLALTT.ZZ", + SMLALD_EQ: "SMLALD.EQ", + SMLALD_NE: "SMLALD.NE", + SMLALD_CS: "SMLALD.CS", + SMLALD_CC: "SMLALD.CC", + SMLALD_MI: "SMLALD.MI", + SMLALD_PL: "SMLALD.PL", + SMLALD_VS: "SMLALD.VS", + SMLALD_VC: "SMLALD.VC", + SMLALD_HI: "SMLALD.HI", + SMLALD_LS: "SMLALD.LS", + SMLALD_GE: "SMLALD.GE", + SMLALD_LT: "SMLALD.LT", + SMLALD_GT: "SMLALD.GT", + SMLALD_LE: "SMLALD.LE", + SMLALD: "SMLALD", + SMLALD_ZZ: "SMLALD.ZZ", + SMLALD_X_EQ: "SMLALD.X.EQ", + SMLALD_X_NE: "SMLALD.X.NE", + SMLALD_X_CS: "SMLALD.X.CS", + SMLALD_X_CC: "SMLALD.X.CC", + SMLALD_X_MI: "SMLALD.X.MI", + SMLALD_X_PL: "SMLALD.X.PL", + SMLALD_X_VS: "SMLALD.X.VS", + SMLALD_X_VC: "SMLALD.X.VC", + SMLALD_X_HI: "SMLALD.X.HI", + SMLALD_X_LS: "SMLALD.X.LS", + SMLALD_X_GE: "SMLALD.X.GE", + SMLALD_X_LT: "SMLALD.X.LT", + SMLALD_X_GT: "SMLALD.X.GT", + SMLALD_X_LE: "SMLALD.X.LE", + SMLALD_X: "SMLALD.X", + SMLALD_X_ZZ: "SMLALD.X.ZZ", + SMLAWB_EQ: "SMLAWB.EQ", + SMLAWB_NE: "SMLAWB.NE", + SMLAWB_CS: "SMLAWB.CS", + SMLAWB_CC: "SMLAWB.CC", + SMLAWB_MI: "SMLAWB.MI", + SMLAWB_PL: "SMLAWB.PL", + SMLAWB_VS: "SMLAWB.VS", + SMLAWB_VC: "SMLAWB.VC", + SMLAWB_HI: "SMLAWB.HI", + SMLAWB_LS: "SMLAWB.LS", + SMLAWB_GE: "SMLAWB.GE", + SMLAWB_LT: "SMLAWB.LT", + SMLAWB_GT: "SMLAWB.GT", + SMLAWB_LE: "SMLAWB.LE", + SMLAWB: "SMLAWB", + SMLAWB_ZZ: "SMLAWB.ZZ", + SMLAWT_EQ: "SMLAWT.EQ", + SMLAWT_NE: "SMLAWT.NE", + SMLAWT_CS: "SMLAWT.CS", + SMLAWT_CC: "SMLAWT.CC", + SMLAWT_MI: "SMLAWT.MI", + SMLAWT_PL: "SMLAWT.PL", + SMLAWT_VS: "SMLAWT.VS", + SMLAWT_VC: "SMLAWT.VC", + SMLAWT_HI: "SMLAWT.HI", + SMLAWT_LS: "SMLAWT.LS", + SMLAWT_GE: "SMLAWT.GE", + SMLAWT_LT: "SMLAWT.LT", + SMLAWT_GT: "SMLAWT.GT", + SMLAWT_LE: "SMLAWT.LE", + SMLAWT: "SMLAWT", + SMLAWT_ZZ: "SMLAWT.ZZ", + SMLSD_EQ: "SMLSD.EQ", + SMLSD_NE: "SMLSD.NE", + SMLSD_CS: "SMLSD.CS", + SMLSD_CC: "SMLSD.CC", + SMLSD_MI: "SMLSD.MI", + SMLSD_PL: "SMLSD.PL", + SMLSD_VS: "SMLSD.VS", + SMLSD_VC: "SMLSD.VC", + SMLSD_HI: "SMLSD.HI", + SMLSD_LS: "SMLSD.LS", + SMLSD_GE: "SMLSD.GE", + SMLSD_LT: "SMLSD.LT", + SMLSD_GT: "SMLSD.GT", + SMLSD_LE: "SMLSD.LE", + SMLSD: "SMLSD", + SMLSD_ZZ: "SMLSD.ZZ", + SMLSD_X_EQ: "SMLSD.X.EQ", + SMLSD_X_NE: "SMLSD.X.NE", + SMLSD_X_CS: "SMLSD.X.CS", + SMLSD_X_CC: "SMLSD.X.CC", + SMLSD_X_MI: "SMLSD.X.MI", + SMLSD_X_PL: "SMLSD.X.PL", + SMLSD_X_VS: "SMLSD.X.VS", + SMLSD_X_VC: "SMLSD.X.VC", + SMLSD_X_HI: "SMLSD.X.HI", + SMLSD_X_LS: "SMLSD.X.LS", + SMLSD_X_GE: "SMLSD.X.GE", + SMLSD_X_LT: "SMLSD.X.LT", + SMLSD_X_GT: "SMLSD.X.GT", + SMLSD_X_LE: "SMLSD.X.LE", + SMLSD_X: "SMLSD.X", + SMLSD_X_ZZ: "SMLSD.X.ZZ", + SMLSLD_EQ: "SMLSLD.EQ", + SMLSLD_NE: "SMLSLD.NE", + SMLSLD_CS: "SMLSLD.CS", + SMLSLD_CC: "SMLSLD.CC", + SMLSLD_MI: "SMLSLD.MI", + SMLSLD_PL: "SMLSLD.PL", + SMLSLD_VS: "SMLSLD.VS", + SMLSLD_VC: "SMLSLD.VC", + SMLSLD_HI: "SMLSLD.HI", + SMLSLD_LS: "SMLSLD.LS", + SMLSLD_GE: "SMLSLD.GE", + SMLSLD_LT: "SMLSLD.LT", + SMLSLD_GT: "SMLSLD.GT", + SMLSLD_LE: "SMLSLD.LE", + SMLSLD: "SMLSLD", + SMLSLD_ZZ: "SMLSLD.ZZ", + SMLSLD_X_EQ: "SMLSLD.X.EQ", + SMLSLD_X_NE: "SMLSLD.X.NE", + SMLSLD_X_CS: "SMLSLD.X.CS", + SMLSLD_X_CC: "SMLSLD.X.CC", + SMLSLD_X_MI: "SMLSLD.X.MI", + SMLSLD_X_PL: "SMLSLD.X.PL", + SMLSLD_X_VS: "SMLSLD.X.VS", + SMLSLD_X_VC: "SMLSLD.X.VC", + SMLSLD_X_HI: "SMLSLD.X.HI", + SMLSLD_X_LS: "SMLSLD.X.LS", + SMLSLD_X_GE: "SMLSLD.X.GE", + SMLSLD_X_LT: "SMLSLD.X.LT", + SMLSLD_X_GT: "SMLSLD.X.GT", + SMLSLD_X_LE: "SMLSLD.X.LE", + SMLSLD_X: "SMLSLD.X", + SMLSLD_X_ZZ: "SMLSLD.X.ZZ", + SMMLA_EQ: "SMMLA.EQ", + SMMLA_NE: "SMMLA.NE", + SMMLA_CS: "SMMLA.CS", + SMMLA_CC: "SMMLA.CC", + SMMLA_MI: "SMMLA.MI", + SMMLA_PL: "SMMLA.PL", + SMMLA_VS: "SMMLA.VS", + SMMLA_VC: "SMMLA.VC", + SMMLA_HI: "SMMLA.HI", + SMMLA_LS: "SMMLA.LS", + SMMLA_GE: "SMMLA.GE", + SMMLA_LT: "SMMLA.LT", + SMMLA_GT: "SMMLA.GT", + SMMLA_LE: "SMMLA.LE", + SMMLA: "SMMLA", + SMMLA_ZZ: "SMMLA.ZZ", + SMMLA_R_EQ: "SMMLA.R.EQ", + SMMLA_R_NE: "SMMLA.R.NE", + SMMLA_R_CS: "SMMLA.R.CS", + SMMLA_R_CC: "SMMLA.R.CC", + SMMLA_R_MI: "SMMLA.R.MI", + SMMLA_R_PL: "SMMLA.R.PL", + SMMLA_R_VS: "SMMLA.R.VS", + SMMLA_R_VC: "SMMLA.R.VC", + SMMLA_R_HI: "SMMLA.R.HI", + SMMLA_R_LS: "SMMLA.R.LS", + SMMLA_R_GE: "SMMLA.R.GE", + SMMLA_R_LT: "SMMLA.R.LT", + SMMLA_R_GT: "SMMLA.R.GT", + SMMLA_R_LE: "SMMLA.R.LE", + SMMLA_R: "SMMLA.R", + SMMLA_R_ZZ: "SMMLA.R.ZZ", + SMMLS_EQ: "SMMLS.EQ", + SMMLS_NE: "SMMLS.NE", + SMMLS_CS: "SMMLS.CS", + SMMLS_CC: "SMMLS.CC", + SMMLS_MI: "SMMLS.MI", + SMMLS_PL: "SMMLS.PL", + SMMLS_VS: "SMMLS.VS", + SMMLS_VC: "SMMLS.VC", + SMMLS_HI: "SMMLS.HI", + SMMLS_LS: "SMMLS.LS", + SMMLS_GE: "SMMLS.GE", + SMMLS_LT: "SMMLS.LT", + SMMLS_GT: "SMMLS.GT", + SMMLS_LE: "SMMLS.LE", + SMMLS: "SMMLS", + SMMLS_ZZ: "SMMLS.ZZ", + SMMLS_R_EQ: "SMMLS.R.EQ", + SMMLS_R_NE: "SMMLS.R.NE", + SMMLS_R_CS: "SMMLS.R.CS", + SMMLS_R_CC: "SMMLS.R.CC", + SMMLS_R_MI: "SMMLS.R.MI", + SMMLS_R_PL: "SMMLS.R.PL", + SMMLS_R_VS: "SMMLS.R.VS", + SMMLS_R_VC: "SMMLS.R.VC", + SMMLS_R_HI: "SMMLS.R.HI", + SMMLS_R_LS: "SMMLS.R.LS", + SMMLS_R_GE: "SMMLS.R.GE", + SMMLS_R_LT: "SMMLS.R.LT", + SMMLS_R_GT: "SMMLS.R.GT", + SMMLS_R_LE: "SMMLS.R.LE", + SMMLS_R: "SMMLS.R", + SMMLS_R_ZZ: "SMMLS.R.ZZ", + SMMUL_EQ: "SMMUL.EQ", + SMMUL_NE: "SMMUL.NE", + SMMUL_CS: "SMMUL.CS", + SMMUL_CC: "SMMUL.CC", + SMMUL_MI: "SMMUL.MI", + SMMUL_PL: "SMMUL.PL", + SMMUL_VS: "SMMUL.VS", + SMMUL_VC: "SMMUL.VC", + SMMUL_HI: "SMMUL.HI", + SMMUL_LS: "SMMUL.LS", + SMMUL_GE: "SMMUL.GE", + SMMUL_LT: "SMMUL.LT", + SMMUL_GT: "SMMUL.GT", + SMMUL_LE: "SMMUL.LE", + SMMUL: "SMMUL", + SMMUL_ZZ: "SMMUL.ZZ", + SMMUL_R_EQ: "SMMUL.R.EQ", + SMMUL_R_NE: "SMMUL.R.NE", + SMMUL_R_CS: "SMMUL.R.CS", + SMMUL_R_CC: "SMMUL.R.CC", + SMMUL_R_MI: "SMMUL.R.MI", + SMMUL_R_PL: "SMMUL.R.PL", + SMMUL_R_VS: "SMMUL.R.VS", + SMMUL_R_VC: "SMMUL.R.VC", + SMMUL_R_HI: "SMMUL.R.HI", + SMMUL_R_LS: "SMMUL.R.LS", + SMMUL_R_GE: "SMMUL.R.GE", + SMMUL_R_LT: "SMMUL.R.LT", + SMMUL_R_GT: "SMMUL.R.GT", + SMMUL_R_LE: "SMMUL.R.LE", + SMMUL_R: "SMMUL.R", + SMMUL_R_ZZ: "SMMUL.R.ZZ", + SMUAD_EQ: "SMUAD.EQ", + SMUAD_NE: "SMUAD.NE", + SMUAD_CS: "SMUAD.CS", + SMUAD_CC: "SMUAD.CC", + SMUAD_MI: "SMUAD.MI", + SMUAD_PL: "SMUAD.PL", + SMUAD_VS: "SMUAD.VS", + SMUAD_VC: "SMUAD.VC", + SMUAD_HI: "SMUAD.HI", + SMUAD_LS: "SMUAD.LS", + SMUAD_GE: "SMUAD.GE", + SMUAD_LT: "SMUAD.LT", + SMUAD_GT: "SMUAD.GT", + SMUAD_LE: "SMUAD.LE", + SMUAD: "SMUAD", + SMUAD_ZZ: "SMUAD.ZZ", + SMUAD_X_EQ: "SMUAD.X.EQ", + SMUAD_X_NE: "SMUAD.X.NE", + SMUAD_X_CS: "SMUAD.X.CS", + SMUAD_X_CC: "SMUAD.X.CC", + SMUAD_X_MI: "SMUAD.X.MI", + SMUAD_X_PL: "SMUAD.X.PL", + SMUAD_X_VS: "SMUAD.X.VS", + SMUAD_X_VC: "SMUAD.X.VC", + SMUAD_X_HI: "SMUAD.X.HI", + SMUAD_X_LS: "SMUAD.X.LS", + SMUAD_X_GE: "SMUAD.X.GE", + SMUAD_X_LT: "SMUAD.X.LT", + SMUAD_X_GT: "SMUAD.X.GT", + SMUAD_X_LE: "SMUAD.X.LE", + SMUAD_X: "SMUAD.X", + SMUAD_X_ZZ: "SMUAD.X.ZZ", + SMULBB_EQ: "SMULBB.EQ", + SMULBB_NE: "SMULBB.NE", + SMULBB_CS: "SMULBB.CS", + SMULBB_CC: "SMULBB.CC", + SMULBB_MI: "SMULBB.MI", + SMULBB_PL: "SMULBB.PL", + SMULBB_VS: "SMULBB.VS", + SMULBB_VC: "SMULBB.VC", + SMULBB_HI: "SMULBB.HI", + SMULBB_LS: "SMULBB.LS", + SMULBB_GE: "SMULBB.GE", + SMULBB_LT: "SMULBB.LT", + SMULBB_GT: "SMULBB.GT", + SMULBB_LE: "SMULBB.LE", + SMULBB: "SMULBB", + SMULBB_ZZ: "SMULBB.ZZ", + SMULBT_EQ: "SMULBT.EQ", + SMULBT_NE: "SMULBT.NE", + SMULBT_CS: "SMULBT.CS", + SMULBT_CC: "SMULBT.CC", + SMULBT_MI: "SMULBT.MI", + SMULBT_PL: "SMULBT.PL", + SMULBT_VS: "SMULBT.VS", + SMULBT_VC: "SMULBT.VC", + SMULBT_HI: "SMULBT.HI", + SMULBT_LS: "SMULBT.LS", + SMULBT_GE: "SMULBT.GE", + SMULBT_LT: "SMULBT.LT", + SMULBT_GT: "SMULBT.GT", + SMULBT_LE: "SMULBT.LE", + SMULBT: "SMULBT", + SMULBT_ZZ: "SMULBT.ZZ", + SMULTB_EQ: "SMULTB.EQ", + SMULTB_NE: "SMULTB.NE", + SMULTB_CS: "SMULTB.CS", + SMULTB_CC: "SMULTB.CC", + SMULTB_MI: "SMULTB.MI", + SMULTB_PL: "SMULTB.PL", + SMULTB_VS: "SMULTB.VS", + SMULTB_VC: "SMULTB.VC", + SMULTB_HI: "SMULTB.HI", + SMULTB_LS: "SMULTB.LS", + SMULTB_GE: "SMULTB.GE", + SMULTB_LT: "SMULTB.LT", + SMULTB_GT: "SMULTB.GT", + SMULTB_LE: "SMULTB.LE", + SMULTB: "SMULTB", + SMULTB_ZZ: "SMULTB.ZZ", + SMULTT_EQ: "SMULTT.EQ", + SMULTT_NE: "SMULTT.NE", + SMULTT_CS: "SMULTT.CS", + SMULTT_CC: "SMULTT.CC", + SMULTT_MI: "SMULTT.MI", + SMULTT_PL: "SMULTT.PL", + SMULTT_VS: "SMULTT.VS", + SMULTT_VC: "SMULTT.VC", + SMULTT_HI: "SMULTT.HI", + SMULTT_LS: "SMULTT.LS", + SMULTT_GE: "SMULTT.GE", + SMULTT_LT: "SMULTT.LT", + SMULTT_GT: "SMULTT.GT", + SMULTT_LE: "SMULTT.LE", + SMULTT: "SMULTT", + SMULTT_ZZ: "SMULTT.ZZ", + SMULL_EQ: "SMULL.EQ", + SMULL_NE: "SMULL.NE", + SMULL_CS: "SMULL.CS", + SMULL_CC: "SMULL.CC", + SMULL_MI: "SMULL.MI", + SMULL_PL: "SMULL.PL", + SMULL_VS: "SMULL.VS", + SMULL_VC: "SMULL.VC", + SMULL_HI: "SMULL.HI", + SMULL_LS: "SMULL.LS", + SMULL_GE: "SMULL.GE", + SMULL_LT: "SMULL.LT", + SMULL_GT: "SMULL.GT", + SMULL_LE: "SMULL.LE", + SMULL: "SMULL", + SMULL_ZZ: "SMULL.ZZ", + SMULL_S_EQ: "SMULL.S.EQ", + SMULL_S_NE: "SMULL.S.NE", + SMULL_S_CS: "SMULL.S.CS", + SMULL_S_CC: "SMULL.S.CC", + SMULL_S_MI: "SMULL.S.MI", + SMULL_S_PL: "SMULL.S.PL", + SMULL_S_VS: "SMULL.S.VS", + SMULL_S_VC: "SMULL.S.VC", + SMULL_S_HI: "SMULL.S.HI", + SMULL_S_LS: "SMULL.S.LS", + SMULL_S_GE: "SMULL.S.GE", + SMULL_S_LT: "SMULL.S.LT", + SMULL_S_GT: "SMULL.S.GT", + SMULL_S_LE: "SMULL.S.LE", + SMULL_S: "SMULL.S", + SMULL_S_ZZ: "SMULL.S.ZZ", + SMULWB_EQ: "SMULWB.EQ", + SMULWB_NE: "SMULWB.NE", + SMULWB_CS: "SMULWB.CS", + SMULWB_CC: "SMULWB.CC", + SMULWB_MI: "SMULWB.MI", + SMULWB_PL: "SMULWB.PL", + SMULWB_VS: "SMULWB.VS", + SMULWB_VC: "SMULWB.VC", + SMULWB_HI: "SMULWB.HI", + SMULWB_LS: "SMULWB.LS", + SMULWB_GE: "SMULWB.GE", + SMULWB_LT: "SMULWB.LT", + SMULWB_GT: "SMULWB.GT", + SMULWB_LE: "SMULWB.LE", + SMULWB: "SMULWB", + SMULWB_ZZ: "SMULWB.ZZ", + SMULWT_EQ: "SMULWT.EQ", + SMULWT_NE: "SMULWT.NE", + SMULWT_CS: "SMULWT.CS", + SMULWT_CC: "SMULWT.CC", + SMULWT_MI: "SMULWT.MI", + SMULWT_PL: "SMULWT.PL", + SMULWT_VS: "SMULWT.VS", + SMULWT_VC: "SMULWT.VC", + SMULWT_HI: "SMULWT.HI", + SMULWT_LS: "SMULWT.LS", + SMULWT_GE: "SMULWT.GE", + SMULWT_LT: "SMULWT.LT", + SMULWT_GT: "SMULWT.GT", + SMULWT_LE: "SMULWT.LE", + SMULWT: "SMULWT", + SMULWT_ZZ: "SMULWT.ZZ", + SMUSD_EQ: "SMUSD.EQ", + SMUSD_NE: "SMUSD.NE", + SMUSD_CS: "SMUSD.CS", + SMUSD_CC: "SMUSD.CC", + SMUSD_MI: "SMUSD.MI", + SMUSD_PL: "SMUSD.PL", + SMUSD_VS: "SMUSD.VS", + SMUSD_VC: "SMUSD.VC", + SMUSD_HI: "SMUSD.HI", + SMUSD_LS: "SMUSD.LS", + SMUSD_GE: "SMUSD.GE", + SMUSD_LT: "SMUSD.LT", + SMUSD_GT: "SMUSD.GT", + SMUSD_LE: "SMUSD.LE", + SMUSD: "SMUSD", + SMUSD_ZZ: "SMUSD.ZZ", + SMUSD_X_EQ: "SMUSD.X.EQ", + SMUSD_X_NE: "SMUSD.X.NE", + SMUSD_X_CS: "SMUSD.X.CS", + SMUSD_X_CC: "SMUSD.X.CC", + SMUSD_X_MI: "SMUSD.X.MI", + SMUSD_X_PL: "SMUSD.X.PL", + SMUSD_X_VS: "SMUSD.X.VS", + SMUSD_X_VC: "SMUSD.X.VC", + SMUSD_X_HI: "SMUSD.X.HI", + SMUSD_X_LS: "SMUSD.X.LS", + SMUSD_X_GE: "SMUSD.X.GE", + SMUSD_X_LT: "SMUSD.X.LT", + SMUSD_X_GT: "SMUSD.X.GT", + SMUSD_X_LE: "SMUSD.X.LE", + SMUSD_X: "SMUSD.X", + SMUSD_X_ZZ: "SMUSD.X.ZZ", + SSAT_EQ: "SSAT.EQ", + SSAT_NE: "SSAT.NE", + SSAT_CS: "SSAT.CS", + SSAT_CC: "SSAT.CC", + SSAT_MI: "SSAT.MI", + SSAT_PL: "SSAT.PL", + SSAT_VS: "SSAT.VS", + SSAT_VC: "SSAT.VC", + SSAT_HI: "SSAT.HI", + SSAT_LS: "SSAT.LS", + SSAT_GE: "SSAT.GE", + SSAT_LT: "SSAT.LT", + SSAT_GT: "SSAT.GT", + SSAT_LE: "SSAT.LE", + SSAT: "SSAT", + SSAT_ZZ: "SSAT.ZZ", + SSAT16_EQ: "SSAT16.EQ", + SSAT16_NE: "SSAT16.NE", + SSAT16_CS: "SSAT16.CS", + SSAT16_CC: "SSAT16.CC", + SSAT16_MI: "SSAT16.MI", + SSAT16_PL: "SSAT16.PL", + SSAT16_VS: "SSAT16.VS", + SSAT16_VC: "SSAT16.VC", + SSAT16_HI: "SSAT16.HI", + SSAT16_LS: "SSAT16.LS", + SSAT16_GE: "SSAT16.GE", + SSAT16_LT: "SSAT16.LT", + SSAT16_GT: "SSAT16.GT", + SSAT16_LE: "SSAT16.LE", + SSAT16: "SSAT16", + SSAT16_ZZ: "SSAT16.ZZ", + SSAX_EQ: "SSAX.EQ", + SSAX_NE: "SSAX.NE", + SSAX_CS: "SSAX.CS", + SSAX_CC: "SSAX.CC", + SSAX_MI: "SSAX.MI", + SSAX_PL: "SSAX.PL", + SSAX_VS: "SSAX.VS", + SSAX_VC: "SSAX.VC", + SSAX_HI: "SSAX.HI", + SSAX_LS: "SSAX.LS", + SSAX_GE: "SSAX.GE", + SSAX_LT: "SSAX.LT", + SSAX_GT: "SSAX.GT", + SSAX_LE: "SSAX.LE", + SSAX: "SSAX", + SSAX_ZZ: "SSAX.ZZ", + SSUB16_EQ: "SSUB16.EQ", + SSUB16_NE: "SSUB16.NE", + SSUB16_CS: "SSUB16.CS", + SSUB16_CC: "SSUB16.CC", + SSUB16_MI: "SSUB16.MI", + SSUB16_PL: "SSUB16.PL", + SSUB16_VS: "SSUB16.VS", + SSUB16_VC: "SSUB16.VC", + SSUB16_HI: "SSUB16.HI", + SSUB16_LS: "SSUB16.LS", + SSUB16_GE: "SSUB16.GE", + SSUB16_LT: "SSUB16.LT", + SSUB16_GT: "SSUB16.GT", + SSUB16_LE: "SSUB16.LE", + SSUB16: "SSUB16", + SSUB16_ZZ: "SSUB16.ZZ", + SSUB8_EQ: "SSUB8.EQ", + SSUB8_NE: "SSUB8.NE", + SSUB8_CS: "SSUB8.CS", + SSUB8_CC: "SSUB8.CC", + SSUB8_MI: "SSUB8.MI", + SSUB8_PL: "SSUB8.PL", + SSUB8_VS: "SSUB8.VS", + SSUB8_VC: "SSUB8.VC", + SSUB8_HI: "SSUB8.HI", + SSUB8_LS: "SSUB8.LS", + SSUB8_GE: "SSUB8.GE", + SSUB8_LT: "SSUB8.LT", + SSUB8_GT: "SSUB8.GT", + SSUB8_LE: "SSUB8.LE", + SSUB8: "SSUB8", + SSUB8_ZZ: "SSUB8.ZZ", + STM_EQ: "STM.EQ", + STM_NE: "STM.NE", + STM_CS: "STM.CS", + STM_CC: "STM.CC", + STM_MI: "STM.MI", + STM_PL: "STM.PL", + STM_VS: "STM.VS", + STM_VC: "STM.VC", + STM_HI: "STM.HI", + STM_LS: "STM.LS", + STM_GE: "STM.GE", + STM_LT: "STM.LT", + STM_GT: "STM.GT", + STM_LE: "STM.LE", + STM: "STM", + STM_ZZ: "STM.ZZ", + STMDA_EQ: "STMDA.EQ", + STMDA_NE: "STMDA.NE", + STMDA_CS: "STMDA.CS", + STMDA_CC: "STMDA.CC", + STMDA_MI: "STMDA.MI", + STMDA_PL: "STMDA.PL", + STMDA_VS: "STMDA.VS", + STMDA_VC: "STMDA.VC", + STMDA_HI: "STMDA.HI", + STMDA_LS: "STMDA.LS", + STMDA_GE: "STMDA.GE", + STMDA_LT: "STMDA.LT", + STMDA_GT: "STMDA.GT", + STMDA_LE: "STMDA.LE", + STMDA: "STMDA", + STMDA_ZZ: "STMDA.ZZ", + STMDB_EQ: "STMDB.EQ", + STMDB_NE: "STMDB.NE", + STMDB_CS: "STMDB.CS", + STMDB_CC: "STMDB.CC", + STMDB_MI: "STMDB.MI", + STMDB_PL: "STMDB.PL", + STMDB_VS: "STMDB.VS", + STMDB_VC: "STMDB.VC", + STMDB_HI: "STMDB.HI", + STMDB_LS: "STMDB.LS", + STMDB_GE: "STMDB.GE", + STMDB_LT: "STMDB.LT", + STMDB_GT: "STMDB.GT", + STMDB_LE: "STMDB.LE", + STMDB: "STMDB", + STMDB_ZZ: "STMDB.ZZ", + STMIB_EQ: "STMIB.EQ", + STMIB_NE: "STMIB.NE", + STMIB_CS: "STMIB.CS", + STMIB_CC: "STMIB.CC", + STMIB_MI: "STMIB.MI", + STMIB_PL: "STMIB.PL", + STMIB_VS: "STMIB.VS", + STMIB_VC: "STMIB.VC", + STMIB_HI: "STMIB.HI", + STMIB_LS: "STMIB.LS", + STMIB_GE: "STMIB.GE", + STMIB_LT: "STMIB.LT", + STMIB_GT: "STMIB.GT", + STMIB_LE: "STMIB.LE", + STMIB: "STMIB", + STMIB_ZZ: "STMIB.ZZ", + STR_EQ: "STR.EQ", + STR_NE: "STR.NE", + STR_CS: "STR.CS", + STR_CC: "STR.CC", + STR_MI: "STR.MI", + STR_PL: "STR.PL", + STR_VS: "STR.VS", + STR_VC: "STR.VC", + STR_HI: "STR.HI", + STR_LS: "STR.LS", + STR_GE: "STR.GE", + STR_LT: "STR.LT", + STR_GT: "STR.GT", + STR_LE: "STR.LE", + STR: "STR", + STR_ZZ: "STR.ZZ", + STRB_EQ: "STRB.EQ", + STRB_NE: "STRB.NE", + STRB_CS: "STRB.CS", + STRB_CC: "STRB.CC", + STRB_MI: "STRB.MI", + STRB_PL: "STRB.PL", + STRB_VS: "STRB.VS", + STRB_VC: "STRB.VC", + STRB_HI: "STRB.HI", + STRB_LS: "STRB.LS", + STRB_GE: "STRB.GE", + STRB_LT: "STRB.LT", + STRB_GT: "STRB.GT", + STRB_LE: "STRB.LE", + STRB: "STRB", + STRB_ZZ: "STRB.ZZ", + STRBT_EQ: "STRBT.EQ", + STRBT_NE: "STRBT.NE", + STRBT_CS: "STRBT.CS", + STRBT_CC: "STRBT.CC", + STRBT_MI: "STRBT.MI", + STRBT_PL: "STRBT.PL", + STRBT_VS: "STRBT.VS", + STRBT_VC: "STRBT.VC", + STRBT_HI: "STRBT.HI", + STRBT_LS: "STRBT.LS", + STRBT_GE: "STRBT.GE", + STRBT_LT: "STRBT.LT", + STRBT_GT: "STRBT.GT", + STRBT_LE: "STRBT.LE", + STRBT: "STRBT", + STRBT_ZZ: "STRBT.ZZ", + STRD_EQ: "STRD.EQ", + STRD_NE: "STRD.NE", + STRD_CS: "STRD.CS", + STRD_CC: "STRD.CC", + STRD_MI: "STRD.MI", + STRD_PL: "STRD.PL", + STRD_VS: "STRD.VS", + STRD_VC: "STRD.VC", + STRD_HI: "STRD.HI", + STRD_LS: "STRD.LS", + STRD_GE: "STRD.GE", + STRD_LT: "STRD.LT", + STRD_GT: "STRD.GT", + STRD_LE: "STRD.LE", + STRD: "STRD", + STRD_ZZ: "STRD.ZZ", + STREX_EQ: "STREX.EQ", + STREX_NE: "STREX.NE", + STREX_CS: "STREX.CS", + STREX_CC: "STREX.CC", + STREX_MI: "STREX.MI", + STREX_PL: "STREX.PL", + STREX_VS: "STREX.VS", + STREX_VC: "STREX.VC", + STREX_HI: "STREX.HI", + STREX_LS: "STREX.LS", + STREX_GE: "STREX.GE", + STREX_LT: "STREX.LT", + STREX_GT: "STREX.GT", + STREX_LE: "STREX.LE", + STREX: "STREX", + STREX_ZZ: "STREX.ZZ", + STREXB_EQ: "STREXB.EQ", + STREXB_NE: "STREXB.NE", + STREXB_CS: "STREXB.CS", + STREXB_CC: "STREXB.CC", + STREXB_MI: "STREXB.MI", + STREXB_PL: "STREXB.PL", + STREXB_VS: "STREXB.VS", + STREXB_VC: "STREXB.VC", + STREXB_HI: "STREXB.HI", + STREXB_LS: "STREXB.LS", + STREXB_GE: "STREXB.GE", + STREXB_LT: "STREXB.LT", + STREXB_GT: "STREXB.GT", + STREXB_LE: "STREXB.LE", + STREXB: "STREXB", + STREXB_ZZ: "STREXB.ZZ", + STREXD_EQ: "STREXD.EQ", + STREXD_NE: "STREXD.NE", + STREXD_CS: "STREXD.CS", + STREXD_CC: "STREXD.CC", + STREXD_MI: "STREXD.MI", + STREXD_PL: "STREXD.PL", + STREXD_VS: "STREXD.VS", + STREXD_VC: "STREXD.VC", + STREXD_HI: "STREXD.HI", + STREXD_LS: "STREXD.LS", + STREXD_GE: "STREXD.GE", + STREXD_LT: "STREXD.LT", + STREXD_GT: "STREXD.GT", + STREXD_LE: "STREXD.LE", + STREXD: "STREXD", + STREXD_ZZ: "STREXD.ZZ", + STREXH_EQ: "STREXH.EQ", + STREXH_NE: "STREXH.NE", + STREXH_CS: "STREXH.CS", + STREXH_CC: "STREXH.CC", + STREXH_MI: "STREXH.MI", + STREXH_PL: "STREXH.PL", + STREXH_VS: "STREXH.VS", + STREXH_VC: "STREXH.VC", + STREXH_HI: "STREXH.HI", + STREXH_LS: "STREXH.LS", + STREXH_GE: "STREXH.GE", + STREXH_LT: "STREXH.LT", + STREXH_GT: "STREXH.GT", + STREXH_LE: "STREXH.LE", + STREXH: "STREXH", + STREXH_ZZ: "STREXH.ZZ", + STRH_EQ: "STRH.EQ", + STRH_NE: "STRH.NE", + STRH_CS: "STRH.CS", + STRH_CC: "STRH.CC", + STRH_MI: "STRH.MI", + STRH_PL: "STRH.PL", + STRH_VS: "STRH.VS", + STRH_VC: "STRH.VC", + STRH_HI: "STRH.HI", + STRH_LS: "STRH.LS", + STRH_GE: "STRH.GE", + STRH_LT: "STRH.LT", + STRH_GT: "STRH.GT", + STRH_LE: "STRH.LE", + STRH: "STRH", + STRH_ZZ: "STRH.ZZ", + STRHT_EQ: "STRHT.EQ", + STRHT_NE: "STRHT.NE", + STRHT_CS: "STRHT.CS", + STRHT_CC: "STRHT.CC", + STRHT_MI: "STRHT.MI", + STRHT_PL: "STRHT.PL", + STRHT_VS: "STRHT.VS", + STRHT_VC: "STRHT.VC", + STRHT_HI: "STRHT.HI", + STRHT_LS: "STRHT.LS", + STRHT_GE: "STRHT.GE", + STRHT_LT: "STRHT.LT", + STRHT_GT: "STRHT.GT", + STRHT_LE: "STRHT.LE", + STRHT: "STRHT", + STRHT_ZZ: "STRHT.ZZ", + STRT_EQ: "STRT.EQ", + STRT_NE: "STRT.NE", + STRT_CS: "STRT.CS", + STRT_CC: "STRT.CC", + STRT_MI: "STRT.MI", + STRT_PL: "STRT.PL", + STRT_VS: "STRT.VS", + STRT_VC: "STRT.VC", + STRT_HI: "STRT.HI", + STRT_LS: "STRT.LS", + STRT_GE: "STRT.GE", + STRT_LT: "STRT.LT", + STRT_GT: "STRT.GT", + STRT_LE: "STRT.LE", + STRT: "STRT", + STRT_ZZ: "STRT.ZZ", + SUB_EQ: "SUB.EQ", + SUB_NE: "SUB.NE", + SUB_CS: "SUB.CS", + SUB_CC: "SUB.CC", + SUB_MI: "SUB.MI", + SUB_PL: "SUB.PL", + SUB_VS: "SUB.VS", + SUB_VC: "SUB.VC", + SUB_HI: "SUB.HI", + SUB_LS: "SUB.LS", + SUB_GE: "SUB.GE", + SUB_LT: "SUB.LT", + SUB_GT: "SUB.GT", + SUB_LE: "SUB.LE", + SUB: "SUB", + SUB_ZZ: "SUB.ZZ", + SUB_S_EQ: "SUB.S.EQ", + SUB_S_NE: "SUB.S.NE", + SUB_S_CS: "SUB.S.CS", + SUB_S_CC: "SUB.S.CC", + SUB_S_MI: "SUB.S.MI", + SUB_S_PL: "SUB.S.PL", + SUB_S_VS: "SUB.S.VS", + SUB_S_VC: "SUB.S.VC", + SUB_S_HI: "SUB.S.HI", + SUB_S_LS: "SUB.S.LS", + SUB_S_GE: "SUB.S.GE", + SUB_S_LT: "SUB.S.LT", + SUB_S_GT: "SUB.S.GT", + SUB_S_LE: "SUB.S.LE", + SUB_S: "SUB.S", + SUB_S_ZZ: "SUB.S.ZZ", + SVC_EQ: "SVC.EQ", + SVC_NE: "SVC.NE", + SVC_CS: "SVC.CS", + SVC_CC: "SVC.CC", + SVC_MI: "SVC.MI", + SVC_PL: "SVC.PL", + SVC_VS: "SVC.VS", + SVC_VC: "SVC.VC", + SVC_HI: "SVC.HI", + SVC_LS: "SVC.LS", + SVC_GE: "SVC.GE", + SVC_LT: "SVC.LT", + SVC_GT: "SVC.GT", + SVC_LE: "SVC.LE", + SVC: "SVC", + SVC_ZZ: "SVC.ZZ", + SWP_EQ: "SWP.EQ", + SWP_NE: "SWP.NE", + SWP_CS: "SWP.CS", + SWP_CC: "SWP.CC", + SWP_MI: "SWP.MI", + SWP_PL: "SWP.PL", + SWP_VS: "SWP.VS", + SWP_VC: "SWP.VC", + SWP_HI: "SWP.HI", + SWP_LS: "SWP.LS", + SWP_GE: "SWP.GE", + SWP_LT: "SWP.LT", + SWP_GT: "SWP.GT", + SWP_LE: "SWP.LE", + SWP: "SWP", + SWP_ZZ: "SWP.ZZ", + SWP_B_EQ: "SWP.B.EQ", + SWP_B_NE: "SWP.B.NE", + SWP_B_CS: "SWP.B.CS", + SWP_B_CC: "SWP.B.CC", + SWP_B_MI: "SWP.B.MI", + SWP_B_PL: "SWP.B.PL", + SWP_B_VS: "SWP.B.VS", + SWP_B_VC: "SWP.B.VC", + SWP_B_HI: "SWP.B.HI", + SWP_B_LS: "SWP.B.LS", + SWP_B_GE: "SWP.B.GE", + SWP_B_LT: "SWP.B.LT", + SWP_B_GT: "SWP.B.GT", + SWP_B_LE: "SWP.B.LE", + SWP_B: "SWP.B", + SWP_B_ZZ: "SWP.B.ZZ", + SXTAB_EQ: "SXTAB.EQ", + SXTAB_NE: "SXTAB.NE", + SXTAB_CS: "SXTAB.CS", + SXTAB_CC: "SXTAB.CC", + SXTAB_MI: "SXTAB.MI", + SXTAB_PL: "SXTAB.PL", + SXTAB_VS: "SXTAB.VS", + SXTAB_VC: "SXTAB.VC", + SXTAB_HI: "SXTAB.HI", + SXTAB_LS: "SXTAB.LS", + SXTAB_GE: "SXTAB.GE", + SXTAB_LT: "SXTAB.LT", + SXTAB_GT: "SXTAB.GT", + SXTAB_LE: "SXTAB.LE", + SXTAB: "SXTAB", + SXTAB_ZZ: "SXTAB.ZZ", + SXTAB16_EQ: "SXTAB16.EQ", + SXTAB16_NE: "SXTAB16.NE", + SXTAB16_CS: "SXTAB16.CS", + SXTAB16_CC: "SXTAB16.CC", + SXTAB16_MI: "SXTAB16.MI", + SXTAB16_PL: "SXTAB16.PL", + SXTAB16_VS: "SXTAB16.VS", + SXTAB16_VC: "SXTAB16.VC", + SXTAB16_HI: "SXTAB16.HI", + SXTAB16_LS: "SXTAB16.LS", + SXTAB16_GE: "SXTAB16.GE", + SXTAB16_LT: "SXTAB16.LT", + SXTAB16_GT: "SXTAB16.GT", + SXTAB16_LE: "SXTAB16.LE", + SXTAB16: "SXTAB16", + SXTAB16_ZZ: "SXTAB16.ZZ", + SXTAH_EQ: "SXTAH.EQ", + SXTAH_NE: "SXTAH.NE", + SXTAH_CS: "SXTAH.CS", + SXTAH_CC: "SXTAH.CC", + SXTAH_MI: "SXTAH.MI", + SXTAH_PL: "SXTAH.PL", + SXTAH_VS: "SXTAH.VS", + SXTAH_VC: "SXTAH.VC", + SXTAH_HI: "SXTAH.HI", + SXTAH_LS: "SXTAH.LS", + SXTAH_GE: "SXTAH.GE", + SXTAH_LT: "SXTAH.LT", + SXTAH_GT: "SXTAH.GT", + SXTAH_LE: "SXTAH.LE", + SXTAH: "SXTAH", + SXTAH_ZZ: "SXTAH.ZZ", + SXTB_EQ: "SXTB.EQ", + SXTB_NE: "SXTB.NE", + SXTB_CS: "SXTB.CS", + SXTB_CC: "SXTB.CC", + SXTB_MI: "SXTB.MI", + SXTB_PL: "SXTB.PL", + SXTB_VS: "SXTB.VS", + SXTB_VC: "SXTB.VC", + SXTB_HI: "SXTB.HI", + SXTB_LS: "SXTB.LS", + SXTB_GE: "SXTB.GE", + SXTB_LT: "SXTB.LT", + SXTB_GT: "SXTB.GT", + SXTB_LE: "SXTB.LE", + SXTB: "SXTB", + SXTB_ZZ: "SXTB.ZZ", + SXTB16_EQ: "SXTB16.EQ", + SXTB16_NE: "SXTB16.NE", + SXTB16_CS: "SXTB16.CS", + SXTB16_CC: "SXTB16.CC", + SXTB16_MI: "SXTB16.MI", + SXTB16_PL: "SXTB16.PL", + SXTB16_VS: "SXTB16.VS", + SXTB16_VC: "SXTB16.VC", + SXTB16_HI: "SXTB16.HI", + SXTB16_LS: "SXTB16.LS", + SXTB16_GE: "SXTB16.GE", + SXTB16_LT: "SXTB16.LT", + SXTB16_GT: "SXTB16.GT", + SXTB16_LE: "SXTB16.LE", + SXTB16: "SXTB16", + SXTB16_ZZ: "SXTB16.ZZ", + SXTH_EQ: "SXTH.EQ", + SXTH_NE: "SXTH.NE", + SXTH_CS: "SXTH.CS", + SXTH_CC: "SXTH.CC", + SXTH_MI: "SXTH.MI", + SXTH_PL: "SXTH.PL", + SXTH_VS: "SXTH.VS", + SXTH_VC: "SXTH.VC", + SXTH_HI: "SXTH.HI", + SXTH_LS: "SXTH.LS", + SXTH_GE: "SXTH.GE", + SXTH_LT: "SXTH.LT", + SXTH_GT: "SXTH.GT", + SXTH_LE: "SXTH.LE", + SXTH: "SXTH", + SXTH_ZZ: "SXTH.ZZ", + TEQ_EQ: "TEQ.EQ", + TEQ_NE: "TEQ.NE", + TEQ_CS: "TEQ.CS", + TEQ_CC: "TEQ.CC", + TEQ_MI: "TEQ.MI", + TEQ_PL: "TEQ.PL", + TEQ_VS: "TEQ.VS", + TEQ_VC: "TEQ.VC", + TEQ_HI: "TEQ.HI", + TEQ_LS: "TEQ.LS", + TEQ_GE: "TEQ.GE", + TEQ_LT: "TEQ.LT", + TEQ_GT: "TEQ.GT", + TEQ_LE: "TEQ.LE", + TEQ: "TEQ", + TEQ_ZZ: "TEQ.ZZ", + TST_EQ: "TST.EQ", + TST_NE: "TST.NE", + TST_CS: "TST.CS", + TST_CC: "TST.CC", + TST_MI: "TST.MI", + TST_PL: "TST.PL", + TST_VS: "TST.VS", + TST_VC: "TST.VC", + TST_HI: "TST.HI", + TST_LS: "TST.LS", + TST_GE: "TST.GE", + TST_LT: "TST.LT", + TST_GT: "TST.GT", + TST_LE: "TST.LE", + TST: "TST", + TST_ZZ: "TST.ZZ", + UADD16_EQ: "UADD16.EQ", + UADD16_NE: "UADD16.NE", + UADD16_CS: "UADD16.CS", + UADD16_CC: "UADD16.CC", + UADD16_MI: "UADD16.MI", + UADD16_PL: "UADD16.PL", + UADD16_VS: "UADD16.VS", + UADD16_VC: "UADD16.VC", + UADD16_HI: "UADD16.HI", + UADD16_LS: "UADD16.LS", + UADD16_GE: "UADD16.GE", + UADD16_LT: "UADD16.LT", + UADD16_GT: "UADD16.GT", + UADD16_LE: "UADD16.LE", + UADD16: "UADD16", + UADD16_ZZ: "UADD16.ZZ", + UADD8_EQ: "UADD8.EQ", + UADD8_NE: "UADD8.NE", + UADD8_CS: "UADD8.CS", + UADD8_CC: "UADD8.CC", + UADD8_MI: "UADD8.MI", + UADD8_PL: "UADD8.PL", + UADD8_VS: "UADD8.VS", + UADD8_VC: "UADD8.VC", + UADD8_HI: "UADD8.HI", + UADD8_LS: "UADD8.LS", + UADD8_GE: "UADD8.GE", + UADD8_LT: "UADD8.LT", + UADD8_GT: "UADD8.GT", + UADD8_LE: "UADD8.LE", + UADD8: "UADD8", + UADD8_ZZ: "UADD8.ZZ", + UASX_EQ: "UASX.EQ", + UASX_NE: "UASX.NE", + UASX_CS: "UASX.CS", + UASX_CC: "UASX.CC", + UASX_MI: "UASX.MI", + UASX_PL: "UASX.PL", + UASX_VS: "UASX.VS", + UASX_VC: "UASX.VC", + UASX_HI: "UASX.HI", + UASX_LS: "UASX.LS", + UASX_GE: "UASX.GE", + UASX_LT: "UASX.LT", + UASX_GT: "UASX.GT", + UASX_LE: "UASX.LE", + UASX: "UASX", + UASX_ZZ: "UASX.ZZ", + UBFX_EQ: "UBFX.EQ", + UBFX_NE: "UBFX.NE", + UBFX_CS: "UBFX.CS", + UBFX_CC: "UBFX.CC", + UBFX_MI: "UBFX.MI", + UBFX_PL: "UBFX.PL", + UBFX_VS: "UBFX.VS", + UBFX_VC: "UBFX.VC", + UBFX_HI: "UBFX.HI", + UBFX_LS: "UBFX.LS", + UBFX_GE: "UBFX.GE", + UBFX_LT: "UBFX.LT", + UBFX_GT: "UBFX.GT", + UBFX_LE: "UBFX.LE", + UBFX: "UBFX", + UBFX_ZZ: "UBFX.ZZ", + UHADD16_EQ: "UHADD16.EQ", + UHADD16_NE: "UHADD16.NE", + UHADD16_CS: "UHADD16.CS", + UHADD16_CC: "UHADD16.CC", + UHADD16_MI: "UHADD16.MI", + UHADD16_PL: "UHADD16.PL", + UHADD16_VS: "UHADD16.VS", + UHADD16_VC: "UHADD16.VC", + UHADD16_HI: "UHADD16.HI", + UHADD16_LS: "UHADD16.LS", + UHADD16_GE: "UHADD16.GE", + UHADD16_LT: "UHADD16.LT", + UHADD16_GT: "UHADD16.GT", + UHADD16_LE: "UHADD16.LE", + UHADD16: "UHADD16", + UHADD16_ZZ: "UHADD16.ZZ", + UHADD8_EQ: "UHADD8.EQ", + UHADD8_NE: "UHADD8.NE", + UHADD8_CS: "UHADD8.CS", + UHADD8_CC: "UHADD8.CC", + UHADD8_MI: "UHADD8.MI", + UHADD8_PL: "UHADD8.PL", + UHADD8_VS: "UHADD8.VS", + UHADD8_VC: "UHADD8.VC", + UHADD8_HI: "UHADD8.HI", + UHADD8_LS: "UHADD8.LS", + UHADD8_GE: "UHADD8.GE", + UHADD8_LT: "UHADD8.LT", + UHADD8_GT: "UHADD8.GT", + UHADD8_LE: "UHADD8.LE", + UHADD8: "UHADD8", + UHADD8_ZZ: "UHADD8.ZZ", + UHASX_EQ: "UHASX.EQ", + UHASX_NE: "UHASX.NE", + UHASX_CS: "UHASX.CS", + UHASX_CC: "UHASX.CC", + UHASX_MI: "UHASX.MI", + UHASX_PL: "UHASX.PL", + UHASX_VS: "UHASX.VS", + UHASX_VC: "UHASX.VC", + UHASX_HI: "UHASX.HI", + UHASX_LS: "UHASX.LS", + UHASX_GE: "UHASX.GE", + UHASX_LT: "UHASX.LT", + UHASX_GT: "UHASX.GT", + UHASX_LE: "UHASX.LE", + UHASX: "UHASX", + UHASX_ZZ: "UHASX.ZZ", + UHSAX_EQ: "UHSAX.EQ", + UHSAX_NE: "UHSAX.NE", + UHSAX_CS: "UHSAX.CS", + UHSAX_CC: "UHSAX.CC", + UHSAX_MI: "UHSAX.MI", + UHSAX_PL: "UHSAX.PL", + UHSAX_VS: "UHSAX.VS", + UHSAX_VC: "UHSAX.VC", + UHSAX_HI: "UHSAX.HI", + UHSAX_LS: "UHSAX.LS", + UHSAX_GE: "UHSAX.GE", + UHSAX_LT: "UHSAX.LT", + UHSAX_GT: "UHSAX.GT", + UHSAX_LE: "UHSAX.LE", + UHSAX: "UHSAX", + UHSAX_ZZ: "UHSAX.ZZ", + UHSUB16_EQ: "UHSUB16.EQ", + UHSUB16_NE: "UHSUB16.NE", + UHSUB16_CS: "UHSUB16.CS", + UHSUB16_CC: "UHSUB16.CC", + UHSUB16_MI: "UHSUB16.MI", + UHSUB16_PL: "UHSUB16.PL", + UHSUB16_VS: "UHSUB16.VS", + UHSUB16_VC: "UHSUB16.VC", + UHSUB16_HI: "UHSUB16.HI", + UHSUB16_LS: "UHSUB16.LS", + UHSUB16_GE: "UHSUB16.GE", + UHSUB16_LT: "UHSUB16.LT", + UHSUB16_GT: "UHSUB16.GT", + UHSUB16_LE: "UHSUB16.LE", + UHSUB16: "UHSUB16", + UHSUB16_ZZ: "UHSUB16.ZZ", + UHSUB8_EQ: "UHSUB8.EQ", + UHSUB8_NE: "UHSUB8.NE", + UHSUB8_CS: "UHSUB8.CS", + UHSUB8_CC: "UHSUB8.CC", + UHSUB8_MI: "UHSUB8.MI", + UHSUB8_PL: "UHSUB8.PL", + UHSUB8_VS: "UHSUB8.VS", + UHSUB8_VC: "UHSUB8.VC", + UHSUB8_HI: "UHSUB8.HI", + UHSUB8_LS: "UHSUB8.LS", + UHSUB8_GE: "UHSUB8.GE", + UHSUB8_LT: "UHSUB8.LT", + UHSUB8_GT: "UHSUB8.GT", + UHSUB8_LE: "UHSUB8.LE", + UHSUB8: "UHSUB8", + UHSUB8_ZZ: "UHSUB8.ZZ", + UMAAL_EQ: "UMAAL.EQ", + UMAAL_NE: "UMAAL.NE", + UMAAL_CS: "UMAAL.CS", + UMAAL_CC: "UMAAL.CC", + UMAAL_MI: "UMAAL.MI", + UMAAL_PL: "UMAAL.PL", + UMAAL_VS: "UMAAL.VS", + UMAAL_VC: "UMAAL.VC", + UMAAL_HI: "UMAAL.HI", + UMAAL_LS: "UMAAL.LS", + UMAAL_GE: "UMAAL.GE", + UMAAL_LT: "UMAAL.LT", + UMAAL_GT: "UMAAL.GT", + UMAAL_LE: "UMAAL.LE", + UMAAL: "UMAAL", + UMAAL_ZZ: "UMAAL.ZZ", + UMLAL_EQ: "UMLAL.EQ", + UMLAL_NE: "UMLAL.NE", + UMLAL_CS: "UMLAL.CS", + UMLAL_CC: "UMLAL.CC", + UMLAL_MI: "UMLAL.MI", + UMLAL_PL: "UMLAL.PL", + UMLAL_VS: "UMLAL.VS", + UMLAL_VC: "UMLAL.VC", + UMLAL_HI: "UMLAL.HI", + UMLAL_LS: "UMLAL.LS", + UMLAL_GE: "UMLAL.GE", + UMLAL_LT: "UMLAL.LT", + UMLAL_GT: "UMLAL.GT", + UMLAL_LE: "UMLAL.LE", + UMLAL: "UMLAL", + UMLAL_ZZ: "UMLAL.ZZ", + UMLAL_S_EQ: "UMLAL.S.EQ", + UMLAL_S_NE: "UMLAL.S.NE", + UMLAL_S_CS: "UMLAL.S.CS", + UMLAL_S_CC: "UMLAL.S.CC", + UMLAL_S_MI: "UMLAL.S.MI", + UMLAL_S_PL: "UMLAL.S.PL", + UMLAL_S_VS: "UMLAL.S.VS", + UMLAL_S_VC: "UMLAL.S.VC", + UMLAL_S_HI: "UMLAL.S.HI", + UMLAL_S_LS: "UMLAL.S.LS", + UMLAL_S_GE: "UMLAL.S.GE", + UMLAL_S_LT: "UMLAL.S.LT", + UMLAL_S_GT: "UMLAL.S.GT", + UMLAL_S_LE: "UMLAL.S.LE", + UMLAL_S: "UMLAL.S", + UMLAL_S_ZZ: "UMLAL.S.ZZ", + UMULL_EQ: "UMULL.EQ", + UMULL_NE: "UMULL.NE", + UMULL_CS: "UMULL.CS", + UMULL_CC: "UMULL.CC", + UMULL_MI: "UMULL.MI", + UMULL_PL: "UMULL.PL", + UMULL_VS: "UMULL.VS", + UMULL_VC: "UMULL.VC", + UMULL_HI: "UMULL.HI", + UMULL_LS: "UMULL.LS", + UMULL_GE: "UMULL.GE", + UMULL_LT: "UMULL.LT", + UMULL_GT: "UMULL.GT", + UMULL_LE: "UMULL.LE", + UMULL: "UMULL", + UMULL_ZZ: "UMULL.ZZ", + UMULL_S_EQ: "UMULL.S.EQ", + UMULL_S_NE: "UMULL.S.NE", + UMULL_S_CS: "UMULL.S.CS", + UMULL_S_CC: "UMULL.S.CC", + UMULL_S_MI: "UMULL.S.MI", + UMULL_S_PL: "UMULL.S.PL", + UMULL_S_VS: "UMULL.S.VS", + UMULL_S_VC: "UMULL.S.VC", + UMULL_S_HI: "UMULL.S.HI", + UMULL_S_LS: "UMULL.S.LS", + UMULL_S_GE: "UMULL.S.GE", + UMULL_S_LT: "UMULL.S.LT", + UMULL_S_GT: "UMULL.S.GT", + UMULL_S_LE: "UMULL.S.LE", + UMULL_S: "UMULL.S", + UMULL_S_ZZ: "UMULL.S.ZZ", + UNDEF: "UNDEF", + UQADD16_EQ: "UQADD16.EQ", + UQADD16_NE: "UQADD16.NE", + UQADD16_CS: "UQADD16.CS", + UQADD16_CC: "UQADD16.CC", + UQADD16_MI: "UQADD16.MI", + UQADD16_PL: "UQADD16.PL", + UQADD16_VS: "UQADD16.VS", + UQADD16_VC: "UQADD16.VC", + UQADD16_HI: "UQADD16.HI", + UQADD16_LS: "UQADD16.LS", + UQADD16_GE: "UQADD16.GE", + UQADD16_LT: "UQADD16.LT", + UQADD16_GT: "UQADD16.GT", + UQADD16_LE: "UQADD16.LE", + UQADD16: "UQADD16", + UQADD16_ZZ: "UQADD16.ZZ", + UQADD8_EQ: "UQADD8.EQ", + UQADD8_NE: "UQADD8.NE", + UQADD8_CS: "UQADD8.CS", + UQADD8_CC: "UQADD8.CC", + UQADD8_MI: "UQADD8.MI", + UQADD8_PL: "UQADD8.PL", + UQADD8_VS: "UQADD8.VS", + UQADD8_VC: "UQADD8.VC", + UQADD8_HI: "UQADD8.HI", + UQADD8_LS: "UQADD8.LS", + UQADD8_GE: "UQADD8.GE", + UQADD8_LT: "UQADD8.LT", + UQADD8_GT: "UQADD8.GT", + UQADD8_LE: "UQADD8.LE", + UQADD8: "UQADD8", + UQADD8_ZZ: "UQADD8.ZZ", + UQASX_EQ: "UQASX.EQ", + UQASX_NE: "UQASX.NE", + UQASX_CS: "UQASX.CS", + UQASX_CC: "UQASX.CC", + UQASX_MI: "UQASX.MI", + UQASX_PL: "UQASX.PL", + UQASX_VS: "UQASX.VS", + UQASX_VC: "UQASX.VC", + UQASX_HI: "UQASX.HI", + UQASX_LS: "UQASX.LS", + UQASX_GE: "UQASX.GE", + UQASX_LT: "UQASX.LT", + UQASX_GT: "UQASX.GT", + UQASX_LE: "UQASX.LE", + UQASX: "UQASX", + UQASX_ZZ: "UQASX.ZZ", + UQSAX_EQ: "UQSAX.EQ", + UQSAX_NE: "UQSAX.NE", + UQSAX_CS: "UQSAX.CS", + UQSAX_CC: "UQSAX.CC", + UQSAX_MI: "UQSAX.MI", + UQSAX_PL: "UQSAX.PL", + UQSAX_VS: "UQSAX.VS", + UQSAX_VC: "UQSAX.VC", + UQSAX_HI: "UQSAX.HI", + UQSAX_LS: "UQSAX.LS", + UQSAX_GE: "UQSAX.GE", + UQSAX_LT: "UQSAX.LT", + UQSAX_GT: "UQSAX.GT", + UQSAX_LE: "UQSAX.LE", + UQSAX: "UQSAX", + UQSAX_ZZ: "UQSAX.ZZ", + UQSUB16_EQ: "UQSUB16.EQ", + UQSUB16_NE: "UQSUB16.NE", + UQSUB16_CS: "UQSUB16.CS", + UQSUB16_CC: "UQSUB16.CC", + UQSUB16_MI: "UQSUB16.MI", + UQSUB16_PL: "UQSUB16.PL", + UQSUB16_VS: "UQSUB16.VS", + UQSUB16_VC: "UQSUB16.VC", + UQSUB16_HI: "UQSUB16.HI", + UQSUB16_LS: "UQSUB16.LS", + UQSUB16_GE: "UQSUB16.GE", + UQSUB16_LT: "UQSUB16.LT", + UQSUB16_GT: "UQSUB16.GT", + UQSUB16_LE: "UQSUB16.LE", + UQSUB16: "UQSUB16", + UQSUB16_ZZ: "UQSUB16.ZZ", + UQSUB8_EQ: "UQSUB8.EQ", + UQSUB8_NE: "UQSUB8.NE", + UQSUB8_CS: "UQSUB8.CS", + UQSUB8_CC: "UQSUB8.CC", + UQSUB8_MI: "UQSUB8.MI", + UQSUB8_PL: "UQSUB8.PL", + UQSUB8_VS: "UQSUB8.VS", + UQSUB8_VC: "UQSUB8.VC", + UQSUB8_HI: "UQSUB8.HI", + UQSUB8_LS: "UQSUB8.LS", + UQSUB8_GE: "UQSUB8.GE", + UQSUB8_LT: "UQSUB8.LT", + UQSUB8_GT: "UQSUB8.GT", + UQSUB8_LE: "UQSUB8.LE", + UQSUB8: "UQSUB8", + UQSUB8_ZZ: "UQSUB8.ZZ", + USAD8_EQ: "USAD8.EQ", + USAD8_NE: "USAD8.NE", + USAD8_CS: "USAD8.CS", + USAD8_CC: "USAD8.CC", + USAD8_MI: "USAD8.MI", + USAD8_PL: "USAD8.PL", + USAD8_VS: "USAD8.VS", + USAD8_VC: "USAD8.VC", + USAD8_HI: "USAD8.HI", + USAD8_LS: "USAD8.LS", + USAD8_GE: "USAD8.GE", + USAD8_LT: "USAD8.LT", + USAD8_GT: "USAD8.GT", + USAD8_LE: "USAD8.LE", + USAD8: "USAD8", + USAD8_ZZ: "USAD8.ZZ", + USADA8_EQ: "USADA8.EQ", + USADA8_NE: "USADA8.NE", + USADA8_CS: "USADA8.CS", + USADA8_CC: "USADA8.CC", + USADA8_MI: "USADA8.MI", + USADA8_PL: "USADA8.PL", + USADA8_VS: "USADA8.VS", + USADA8_VC: "USADA8.VC", + USADA8_HI: "USADA8.HI", + USADA8_LS: "USADA8.LS", + USADA8_GE: "USADA8.GE", + USADA8_LT: "USADA8.LT", + USADA8_GT: "USADA8.GT", + USADA8_LE: "USADA8.LE", + USADA8: "USADA8", + USADA8_ZZ: "USADA8.ZZ", + USAT_EQ: "USAT.EQ", + USAT_NE: "USAT.NE", + USAT_CS: "USAT.CS", + USAT_CC: "USAT.CC", + USAT_MI: "USAT.MI", + USAT_PL: "USAT.PL", + USAT_VS: "USAT.VS", + USAT_VC: "USAT.VC", + USAT_HI: "USAT.HI", + USAT_LS: "USAT.LS", + USAT_GE: "USAT.GE", + USAT_LT: "USAT.LT", + USAT_GT: "USAT.GT", + USAT_LE: "USAT.LE", + USAT: "USAT", + USAT_ZZ: "USAT.ZZ", + USAT16_EQ: "USAT16.EQ", + USAT16_NE: "USAT16.NE", + USAT16_CS: "USAT16.CS", + USAT16_CC: "USAT16.CC", + USAT16_MI: "USAT16.MI", + USAT16_PL: "USAT16.PL", + USAT16_VS: "USAT16.VS", + USAT16_VC: "USAT16.VC", + USAT16_HI: "USAT16.HI", + USAT16_LS: "USAT16.LS", + USAT16_GE: "USAT16.GE", + USAT16_LT: "USAT16.LT", + USAT16_GT: "USAT16.GT", + USAT16_LE: "USAT16.LE", + USAT16: "USAT16", + USAT16_ZZ: "USAT16.ZZ", + USAX_EQ: "USAX.EQ", + USAX_NE: "USAX.NE", + USAX_CS: "USAX.CS", + USAX_CC: "USAX.CC", + USAX_MI: "USAX.MI", + USAX_PL: "USAX.PL", + USAX_VS: "USAX.VS", + USAX_VC: "USAX.VC", + USAX_HI: "USAX.HI", + USAX_LS: "USAX.LS", + USAX_GE: "USAX.GE", + USAX_LT: "USAX.LT", + USAX_GT: "USAX.GT", + USAX_LE: "USAX.LE", + USAX: "USAX", + USAX_ZZ: "USAX.ZZ", + USUB16_EQ: "USUB16.EQ", + USUB16_NE: "USUB16.NE", + USUB16_CS: "USUB16.CS", + USUB16_CC: "USUB16.CC", + USUB16_MI: "USUB16.MI", + USUB16_PL: "USUB16.PL", + USUB16_VS: "USUB16.VS", + USUB16_VC: "USUB16.VC", + USUB16_HI: "USUB16.HI", + USUB16_LS: "USUB16.LS", + USUB16_GE: "USUB16.GE", + USUB16_LT: "USUB16.LT", + USUB16_GT: "USUB16.GT", + USUB16_LE: "USUB16.LE", + USUB16: "USUB16", + USUB16_ZZ: "USUB16.ZZ", + USUB8_EQ: "USUB8.EQ", + USUB8_NE: "USUB8.NE", + USUB8_CS: "USUB8.CS", + USUB8_CC: "USUB8.CC", + USUB8_MI: "USUB8.MI", + USUB8_PL: "USUB8.PL", + USUB8_VS: "USUB8.VS", + USUB8_VC: "USUB8.VC", + USUB8_HI: "USUB8.HI", + USUB8_LS: "USUB8.LS", + USUB8_GE: "USUB8.GE", + USUB8_LT: "USUB8.LT", + USUB8_GT: "USUB8.GT", + USUB8_LE: "USUB8.LE", + USUB8: "USUB8", + USUB8_ZZ: "USUB8.ZZ", + UXTAB_EQ: "UXTAB.EQ", + UXTAB_NE: "UXTAB.NE", + UXTAB_CS: "UXTAB.CS", + UXTAB_CC: "UXTAB.CC", + UXTAB_MI: "UXTAB.MI", + UXTAB_PL: "UXTAB.PL", + UXTAB_VS: "UXTAB.VS", + UXTAB_VC: "UXTAB.VC", + UXTAB_HI: "UXTAB.HI", + UXTAB_LS: "UXTAB.LS", + UXTAB_GE: "UXTAB.GE", + UXTAB_LT: "UXTAB.LT", + UXTAB_GT: "UXTAB.GT", + UXTAB_LE: "UXTAB.LE", + UXTAB: "UXTAB", + UXTAB_ZZ: "UXTAB.ZZ", + UXTAB16_EQ: "UXTAB16.EQ", + UXTAB16_NE: "UXTAB16.NE", + UXTAB16_CS: "UXTAB16.CS", + UXTAB16_CC: "UXTAB16.CC", + UXTAB16_MI: "UXTAB16.MI", + UXTAB16_PL: "UXTAB16.PL", + UXTAB16_VS: "UXTAB16.VS", + UXTAB16_VC: "UXTAB16.VC", + UXTAB16_HI: "UXTAB16.HI", + UXTAB16_LS: "UXTAB16.LS", + UXTAB16_GE: "UXTAB16.GE", + UXTAB16_LT: "UXTAB16.LT", + UXTAB16_GT: "UXTAB16.GT", + UXTAB16_LE: "UXTAB16.LE", + UXTAB16: "UXTAB16", + UXTAB16_ZZ: "UXTAB16.ZZ", + UXTAH_EQ: "UXTAH.EQ", + UXTAH_NE: "UXTAH.NE", + UXTAH_CS: "UXTAH.CS", + UXTAH_CC: "UXTAH.CC", + UXTAH_MI: "UXTAH.MI", + UXTAH_PL: "UXTAH.PL", + UXTAH_VS: "UXTAH.VS", + UXTAH_VC: "UXTAH.VC", + UXTAH_HI: "UXTAH.HI", + UXTAH_LS: "UXTAH.LS", + UXTAH_GE: "UXTAH.GE", + UXTAH_LT: "UXTAH.LT", + UXTAH_GT: "UXTAH.GT", + UXTAH_LE: "UXTAH.LE", + UXTAH: "UXTAH", + UXTAH_ZZ: "UXTAH.ZZ", + UXTB_EQ: "UXTB.EQ", + UXTB_NE: "UXTB.NE", + UXTB_CS: "UXTB.CS", + UXTB_CC: "UXTB.CC", + UXTB_MI: "UXTB.MI", + UXTB_PL: "UXTB.PL", + UXTB_VS: "UXTB.VS", + UXTB_VC: "UXTB.VC", + UXTB_HI: "UXTB.HI", + UXTB_LS: "UXTB.LS", + UXTB_GE: "UXTB.GE", + UXTB_LT: "UXTB.LT", + UXTB_GT: "UXTB.GT", + UXTB_LE: "UXTB.LE", + UXTB: "UXTB", + UXTB_ZZ: "UXTB.ZZ", + UXTB16_EQ: "UXTB16.EQ", + UXTB16_NE: "UXTB16.NE", + UXTB16_CS: "UXTB16.CS", + UXTB16_CC: "UXTB16.CC", + UXTB16_MI: "UXTB16.MI", + UXTB16_PL: "UXTB16.PL", + UXTB16_VS: "UXTB16.VS", + UXTB16_VC: "UXTB16.VC", + UXTB16_HI: "UXTB16.HI", + UXTB16_LS: "UXTB16.LS", + UXTB16_GE: "UXTB16.GE", + UXTB16_LT: "UXTB16.LT", + UXTB16_GT: "UXTB16.GT", + UXTB16_LE: "UXTB16.LE", + UXTB16: "UXTB16", + UXTB16_ZZ: "UXTB16.ZZ", + UXTH_EQ: "UXTH.EQ", + UXTH_NE: "UXTH.NE", + UXTH_CS: "UXTH.CS", + UXTH_CC: "UXTH.CC", + UXTH_MI: "UXTH.MI", + UXTH_PL: "UXTH.PL", + UXTH_VS: "UXTH.VS", + UXTH_VC: "UXTH.VC", + UXTH_HI: "UXTH.HI", + UXTH_LS: "UXTH.LS", + UXTH_GE: "UXTH.GE", + UXTH_LT: "UXTH.LT", + UXTH_GT: "UXTH.GT", + UXTH_LE: "UXTH.LE", + UXTH: "UXTH", + UXTH_ZZ: "UXTH.ZZ", + VABS_EQ_F32: "VABS.EQ.F32", + VABS_NE_F32: "VABS.NE.F32", + VABS_CS_F32: "VABS.CS.F32", + VABS_CC_F32: "VABS.CC.F32", + VABS_MI_F32: "VABS.MI.F32", + VABS_PL_F32: "VABS.PL.F32", + VABS_VS_F32: "VABS.VS.F32", + VABS_VC_F32: "VABS.VC.F32", + VABS_HI_F32: "VABS.HI.F32", + VABS_LS_F32: "VABS.LS.F32", + VABS_GE_F32: "VABS.GE.F32", + VABS_LT_F32: "VABS.LT.F32", + VABS_GT_F32: "VABS.GT.F32", + VABS_LE_F32: "VABS.LE.F32", + VABS_F32: "VABS.F32", + VABS_ZZ_F32: "VABS.ZZ.F32", + VABS_EQ_F64: "VABS.EQ.F64", + VABS_NE_F64: "VABS.NE.F64", + VABS_CS_F64: "VABS.CS.F64", + VABS_CC_F64: "VABS.CC.F64", + VABS_MI_F64: "VABS.MI.F64", + VABS_PL_F64: "VABS.PL.F64", + VABS_VS_F64: "VABS.VS.F64", + VABS_VC_F64: "VABS.VC.F64", + VABS_HI_F64: "VABS.HI.F64", + VABS_LS_F64: "VABS.LS.F64", + VABS_GE_F64: "VABS.GE.F64", + VABS_LT_F64: "VABS.LT.F64", + VABS_GT_F64: "VABS.GT.F64", + VABS_LE_F64: "VABS.LE.F64", + VABS_F64: "VABS.F64", + VABS_ZZ_F64: "VABS.ZZ.F64", + VADD_EQ_F32: "VADD.EQ.F32", + VADD_NE_F32: "VADD.NE.F32", + VADD_CS_F32: "VADD.CS.F32", + VADD_CC_F32: "VADD.CC.F32", + VADD_MI_F32: "VADD.MI.F32", + VADD_PL_F32: "VADD.PL.F32", + VADD_VS_F32: "VADD.VS.F32", + VADD_VC_F32: "VADD.VC.F32", + VADD_HI_F32: "VADD.HI.F32", + VADD_LS_F32: "VADD.LS.F32", + VADD_GE_F32: "VADD.GE.F32", + VADD_LT_F32: "VADD.LT.F32", + VADD_GT_F32: "VADD.GT.F32", + VADD_LE_F32: "VADD.LE.F32", + VADD_F32: "VADD.F32", + VADD_ZZ_F32: "VADD.ZZ.F32", + VADD_EQ_F64: "VADD.EQ.F64", + VADD_NE_F64: "VADD.NE.F64", + VADD_CS_F64: "VADD.CS.F64", + VADD_CC_F64: "VADD.CC.F64", + VADD_MI_F64: "VADD.MI.F64", + VADD_PL_F64: "VADD.PL.F64", + VADD_VS_F64: "VADD.VS.F64", + VADD_VC_F64: "VADD.VC.F64", + VADD_HI_F64: "VADD.HI.F64", + VADD_LS_F64: "VADD.LS.F64", + VADD_GE_F64: "VADD.GE.F64", + VADD_LT_F64: "VADD.LT.F64", + VADD_GT_F64: "VADD.GT.F64", + VADD_LE_F64: "VADD.LE.F64", + VADD_F64: "VADD.F64", + VADD_ZZ_F64: "VADD.ZZ.F64", + VCMP_EQ_F32: "VCMP.EQ.F32", + VCMP_NE_F32: "VCMP.NE.F32", + VCMP_CS_F32: "VCMP.CS.F32", + VCMP_CC_F32: "VCMP.CC.F32", + VCMP_MI_F32: "VCMP.MI.F32", + VCMP_PL_F32: "VCMP.PL.F32", + VCMP_VS_F32: "VCMP.VS.F32", + VCMP_VC_F32: "VCMP.VC.F32", + VCMP_HI_F32: "VCMP.HI.F32", + VCMP_LS_F32: "VCMP.LS.F32", + VCMP_GE_F32: "VCMP.GE.F32", + VCMP_LT_F32: "VCMP.LT.F32", + VCMP_GT_F32: "VCMP.GT.F32", + VCMP_LE_F32: "VCMP.LE.F32", + VCMP_F32: "VCMP.F32", + VCMP_ZZ_F32: "VCMP.ZZ.F32", + VCMP_EQ_F64: "VCMP.EQ.F64", + VCMP_NE_F64: "VCMP.NE.F64", + VCMP_CS_F64: "VCMP.CS.F64", + VCMP_CC_F64: "VCMP.CC.F64", + VCMP_MI_F64: "VCMP.MI.F64", + VCMP_PL_F64: "VCMP.PL.F64", + VCMP_VS_F64: "VCMP.VS.F64", + VCMP_VC_F64: "VCMP.VC.F64", + VCMP_HI_F64: "VCMP.HI.F64", + VCMP_LS_F64: "VCMP.LS.F64", + VCMP_GE_F64: "VCMP.GE.F64", + VCMP_LT_F64: "VCMP.LT.F64", + VCMP_GT_F64: "VCMP.GT.F64", + VCMP_LE_F64: "VCMP.LE.F64", + VCMP_F64: "VCMP.F64", + VCMP_ZZ_F64: "VCMP.ZZ.F64", + VCMP_E_EQ_F32: "VCMP.E.EQ.F32", + VCMP_E_NE_F32: "VCMP.E.NE.F32", + VCMP_E_CS_F32: "VCMP.E.CS.F32", + VCMP_E_CC_F32: "VCMP.E.CC.F32", + VCMP_E_MI_F32: "VCMP.E.MI.F32", + VCMP_E_PL_F32: "VCMP.E.PL.F32", + VCMP_E_VS_F32: "VCMP.E.VS.F32", + VCMP_E_VC_F32: "VCMP.E.VC.F32", + VCMP_E_HI_F32: "VCMP.E.HI.F32", + VCMP_E_LS_F32: "VCMP.E.LS.F32", + VCMP_E_GE_F32: "VCMP.E.GE.F32", + VCMP_E_LT_F32: "VCMP.E.LT.F32", + VCMP_E_GT_F32: "VCMP.E.GT.F32", + VCMP_E_LE_F32: "VCMP.E.LE.F32", + VCMP_E_F32: "VCMP.E.F32", + VCMP_E_ZZ_F32: "VCMP.E.ZZ.F32", + VCMP_E_EQ_F64: "VCMP.E.EQ.F64", + VCMP_E_NE_F64: "VCMP.E.NE.F64", + VCMP_E_CS_F64: "VCMP.E.CS.F64", + VCMP_E_CC_F64: "VCMP.E.CC.F64", + VCMP_E_MI_F64: "VCMP.E.MI.F64", + VCMP_E_PL_F64: "VCMP.E.PL.F64", + VCMP_E_VS_F64: "VCMP.E.VS.F64", + VCMP_E_VC_F64: "VCMP.E.VC.F64", + VCMP_E_HI_F64: "VCMP.E.HI.F64", + VCMP_E_LS_F64: "VCMP.E.LS.F64", + VCMP_E_GE_F64: "VCMP.E.GE.F64", + VCMP_E_LT_F64: "VCMP.E.LT.F64", + VCMP_E_GT_F64: "VCMP.E.GT.F64", + VCMP_E_LE_F64: "VCMP.E.LE.F64", + VCMP_E_F64: "VCMP.E.F64", + VCMP_E_ZZ_F64: "VCMP.E.ZZ.F64", + VCVT_EQ_F32_FXS16: "VCVT.EQ.F32.FXS16", + VCVT_NE_F32_FXS16: "VCVT.NE.F32.FXS16", + VCVT_CS_F32_FXS16: "VCVT.CS.F32.FXS16", + VCVT_CC_F32_FXS16: "VCVT.CC.F32.FXS16", + VCVT_MI_F32_FXS16: "VCVT.MI.F32.FXS16", + VCVT_PL_F32_FXS16: "VCVT.PL.F32.FXS16", + VCVT_VS_F32_FXS16: "VCVT.VS.F32.FXS16", + VCVT_VC_F32_FXS16: "VCVT.VC.F32.FXS16", + VCVT_HI_F32_FXS16: "VCVT.HI.F32.FXS16", + VCVT_LS_F32_FXS16: "VCVT.LS.F32.FXS16", + VCVT_GE_F32_FXS16: "VCVT.GE.F32.FXS16", + VCVT_LT_F32_FXS16: "VCVT.LT.F32.FXS16", + VCVT_GT_F32_FXS16: "VCVT.GT.F32.FXS16", + VCVT_LE_F32_FXS16: "VCVT.LE.F32.FXS16", + VCVT_F32_FXS16: "VCVT.F32.FXS16", + VCVT_ZZ_F32_FXS16: "VCVT.ZZ.F32.FXS16", + VCVT_EQ_F32_FXS32: "VCVT.EQ.F32.FXS32", + VCVT_NE_F32_FXS32: "VCVT.NE.F32.FXS32", + VCVT_CS_F32_FXS32: "VCVT.CS.F32.FXS32", + VCVT_CC_F32_FXS32: "VCVT.CC.F32.FXS32", + VCVT_MI_F32_FXS32: "VCVT.MI.F32.FXS32", + VCVT_PL_F32_FXS32: "VCVT.PL.F32.FXS32", + VCVT_VS_F32_FXS32: "VCVT.VS.F32.FXS32", + VCVT_VC_F32_FXS32: "VCVT.VC.F32.FXS32", + VCVT_HI_F32_FXS32: "VCVT.HI.F32.FXS32", + VCVT_LS_F32_FXS32: "VCVT.LS.F32.FXS32", + VCVT_GE_F32_FXS32: "VCVT.GE.F32.FXS32", + VCVT_LT_F32_FXS32: "VCVT.LT.F32.FXS32", + VCVT_GT_F32_FXS32: "VCVT.GT.F32.FXS32", + VCVT_LE_F32_FXS32: "VCVT.LE.F32.FXS32", + VCVT_F32_FXS32: "VCVT.F32.FXS32", + VCVT_ZZ_F32_FXS32: "VCVT.ZZ.F32.FXS32", + VCVT_EQ_F32_FXU16: "VCVT.EQ.F32.FXU16", + VCVT_NE_F32_FXU16: "VCVT.NE.F32.FXU16", + VCVT_CS_F32_FXU16: "VCVT.CS.F32.FXU16", + VCVT_CC_F32_FXU16: "VCVT.CC.F32.FXU16", + VCVT_MI_F32_FXU16: "VCVT.MI.F32.FXU16", + VCVT_PL_F32_FXU16: "VCVT.PL.F32.FXU16", + VCVT_VS_F32_FXU16: "VCVT.VS.F32.FXU16", + VCVT_VC_F32_FXU16: "VCVT.VC.F32.FXU16", + VCVT_HI_F32_FXU16: "VCVT.HI.F32.FXU16", + VCVT_LS_F32_FXU16: "VCVT.LS.F32.FXU16", + VCVT_GE_F32_FXU16: "VCVT.GE.F32.FXU16", + VCVT_LT_F32_FXU16: "VCVT.LT.F32.FXU16", + VCVT_GT_F32_FXU16: "VCVT.GT.F32.FXU16", + VCVT_LE_F32_FXU16: "VCVT.LE.F32.FXU16", + VCVT_F32_FXU16: "VCVT.F32.FXU16", + VCVT_ZZ_F32_FXU16: "VCVT.ZZ.F32.FXU16", + VCVT_EQ_F32_FXU32: "VCVT.EQ.F32.FXU32", + VCVT_NE_F32_FXU32: "VCVT.NE.F32.FXU32", + VCVT_CS_F32_FXU32: "VCVT.CS.F32.FXU32", + VCVT_CC_F32_FXU32: "VCVT.CC.F32.FXU32", + VCVT_MI_F32_FXU32: "VCVT.MI.F32.FXU32", + VCVT_PL_F32_FXU32: "VCVT.PL.F32.FXU32", + VCVT_VS_F32_FXU32: "VCVT.VS.F32.FXU32", + VCVT_VC_F32_FXU32: "VCVT.VC.F32.FXU32", + VCVT_HI_F32_FXU32: "VCVT.HI.F32.FXU32", + VCVT_LS_F32_FXU32: "VCVT.LS.F32.FXU32", + VCVT_GE_F32_FXU32: "VCVT.GE.F32.FXU32", + VCVT_LT_F32_FXU32: "VCVT.LT.F32.FXU32", + VCVT_GT_F32_FXU32: "VCVT.GT.F32.FXU32", + VCVT_LE_F32_FXU32: "VCVT.LE.F32.FXU32", + VCVT_F32_FXU32: "VCVT.F32.FXU32", + VCVT_ZZ_F32_FXU32: "VCVT.ZZ.F32.FXU32", + VCVT_EQ_F64_FXS16: "VCVT.EQ.F64.FXS16", + VCVT_NE_F64_FXS16: "VCVT.NE.F64.FXS16", + VCVT_CS_F64_FXS16: "VCVT.CS.F64.FXS16", + VCVT_CC_F64_FXS16: "VCVT.CC.F64.FXS16", + VCVT_MI_F64_FXS16: "VCVT.MI.F64.FXS16", + VCVT_PL_F64_FXS16: "VCVT.PL.F64.FXS16", + VCVT_VS_F64_FXS16: "VCVT.VS.F64.FXS16", + VCVT_VC_F64_FXS16: "VCVT.VC.F64.FXS16", + VCVT_HI_F64_FXS16: "VCVT.HI.F64.FXS16", + VCVT_LS_F64_FXS16: "VCVT.LS.F64.FXS16", + VCVT_GE_F64_FXS16: "VCVT.GE.F64.FXS16", + VCVT_LT_F64_FXS16: "VCVT.LT.F64.FXS16", + VCVT_GT_F64_FXS16: "VCVT.GT.F64.FXS16", + VCVT_LE_F64_FXS16: "VCVT.LE.F64.FXS16", + VCVT_F64_FXS16: "VCVT.F64.FXS16", + VCVT_ZZ_F64_FXS16: "VCVT.ZZ.F64.FXS16", + VCVT_EQ_F64_FXS32: "VCVT.EQ.F64.FXS32", + VCVT_NE_F64_FXS32: "VCVT.NE.F64.FXS32", + VCVT_CS_F64_FXS32: "VCVT.CS.F64.FXS32", + VCVT_CC_F64_FXS32: "VCVT.CC.F64.FXS32", + VCVT_MI_F64_FXS32: "VCVT.MI.F64.FXS32", + VCVT_PL_F64_FXS32: "VCVT.PL.F64.FXS32", + VCVT_VS_F64_FXS32: "VCVT.VS.F64.FXS32", + VCVT_VC_F64_FXS32: "VCVT.VC.F64.FXS32", + VCVT_HI_F64_FXS32: "VCVT.HI.F64.FXS32", + VCVT_LS_F64_FXS32: "VCVT.LS.F64.FXS32", + VCVT_GE_F64_FXS32: "VCVT.GE.F64.FXS32", + VCVT_LT_F64_FXS32: "VCVT.LT.F64.FXS32", + VCVT_GT_F64_FXS32: "VCVT.GT.F64.FXS32", + VCVT_LE_F64_FXS32: "VCVT.LE.F64.FXS32", + VCVT_F64_FXS32: "VCVT.F64.FXS32", + VCVT_ZZ_F64_FXS32: "VCVT.ZZ.F64.FXS32", + VCVT_EQ_F64_FXU16: "VCVT.EQ.F64.FXU16", + VCVT_NE_F64_FXU16: "VCVT.NE.F64.FXU16", + VCVT_CS_F64_FXU16: "VCVT.CS.F64.FXU16", + VCVT_CC_F64_FXU16: "VCVT.CC.F64.FXU16", + VCVT_MI_F64_FXU16: "VCVT.MI.F64.FXU16", + VCVT_PL_F64_FXU16: "VCVT.PL.F64.FXU16", + VCVT_VS_F64_FXU16: "VCVT.VS.F64.FXU16", + VCVT_VC_F64_FXU16: "VCVT.VC.F64.FXU16", + VCVT_HI_F64_FXU16: "VCVT.HI.F64.FXU16", + VCVT_LS_F64_FXU16: "VCVT.LS.F64.FXU16", + VCVT_GE_F64_FXU16: "VCVT.GE.F64.FXU16", + VCVT_LT_F64_FXU16: "VCVT.LT.F64.FXU16", + VCVT_GT_F64_FXU16: "VCVT.GT.F64.FXU16", + VCVT_LE_F64_FXU16: "VCVT.LE.F64.FXU16", + VCVT_F64_FXU16: "VCVT.F64.FXU16", + VCVT_ZZ_F64_FXU16: "VCVT.ZZ.F64.FXU16", + VCVT_EQ_F64_FXU32: "VCVT.EQ.F64.FXU32", + VCVT_NE_F64_FXU32: "VCVT.NE.F64.FXU32", + VCVT_CS_F64_FXU32: "VCVT.CS.F64.FXU32", + VCVT_CC_F64_FXU32: "VCVT.CC.F64.FXU32", + VCVT_MI_F64_FXU32: "VCVT.MI.F64.FXU32", + VCVT_PL_F64_FXU32: "VCVT.PL.F64.FXU32", + VCVT_VS_F64_FXU32: "VCVT.VS.F64.FXU32", + VCVT_VC_F64_FXU32: "VCVT.VC.F64.FXU32", + VCVT_HI_F64_FXU32: "VCVT.HI.F64.FXU32", + VCVT_LS_F64_FXU32: "VCVT.LS.F64.FXU32", + VCVT_GE_F64_FXU32: "VCVT.GE.F64.FXU32", + VCVT_LT_F64_FXU32: "VCVT.LT.F64.FXU32", + VCVT_GT_F64_FXU32: "VCVT.GT.F64.FXU32", + VCVT_LE_F64_FXU32: "VCVT.LE.F64.FXU32", + VCVT_F64_FXU32: "VCVT.F64.FXU32", + VCVT_ZZ_F64_FXU32: "VCVT.ZZ.F64.FXU32", + VCVT_EQ_F32_U32: "VCVT.EQ.F32.U32", + VCVT_NE_F32_U32: "VCVT.NE.F32.U32", + VCVT_CS_F32_U32: "VCVT.CS.F32.U32", + VCVT_CC_F32_U32: "VCVT.CC.F32.U32", + VCVT_MI_F32_U32: "VCVT.MI.F32.U32", + VCVT_PL_F32_U32: "VCVT.PL.F32.U32", + VCVT_VS_F32_U32: "VCVT.VS.F32.U32", + VCVT_VC_F32_U32: "VCVT.VC.F32.U32", + VCVT_HI_F32_U32: "VCVT.HI.F32.U32", + VCVT_LS_F32_U32: "VCVT.LS.F32.U32", + VCVT_GE_F32_U32: "VCVT.GE.F32.U32", + VCVT_LT_F32_U32: "VCVT.LT.F32.U32", + VCVT_GT_F32_U32: "VCVT.GT.F32.U32", + VCVT_LE_F32_U32: "VCVT.LE.F32.U32", + VCVT_F32_U32: "VCVT.F32.U32", + VCVT_ZZ_F32_U32: "VCVT.ZZ.F32.U32", + VCVT_EQ_F32_S32: "VCVT.EQ.F32.S32", + VCVT_NE_F32_S32: "VCVT.NE.F32.S32", + VCVT_CS_F32_S32: "VCVT.CS.F32.S32", + VCVT_CC_F32_S32: "VCVT.CC.F32.S32", + VCVT_MI_F32_S32: "VCVT.MI.F32.S32", + VCVT_PL_F32_S32: "VCVT.PL.F32.S32", + VCVT_VS_F32_S32: "VCVT.VS.F32.S32", + VCVT_VC_F32_S32: "VCVT.VC.F32.S32", + VCVT_HI_F32_S32: "VCVT.HI.F32.S32", + VCVT_LS_F32_S32: "VCVT.LS.F32.S32", + VCVT_GE_F32_S32: "VCVT.GE.F32.S32", + VCVT_LT_F32_S32: "VCVT.LT.F32.S32", + VCVT_GT_F32_S32: "VCVT.GT.F32.S32", + VCVT_LE_F32_S32: "VCVT.LE.F32.S32", + VCVT_F32_S32: "VCVT.F32.S32", + VCVT_ZZ_F32_S32: "VCVT.ZZ.F32.S32", + VCVT_EQ_F64_U32: "VCVT.EQ.F64.U32", + VCVT_NE_F64_U32: "VCVT.NE.F64.U32", + VCVT_CS_F64_U32: "VCVT.CS.F64.U32", + VCVT_CC_F64_U32: "VCVT.CC.F64.U32", + VCVT_MI_F64_U32: "VCVT.MI.F64.U32", + VCVT_PL_F64_U32: "VCVT.PL.F64.U32", + VCVT_VS_F64_U32: "VCVT.VS.F64.U32", + VCVT_VC_F64_U32: "VCVT.VC.F64.U32", + VCVT_HI_F64_U32: "VCVT.HI.F64.U32", + VCVT_LS_F64_U32: "VCVT.LS.F64.U32", + VCVT_GE_F64_U32: "VCVT.GE.F64.U32", + VCVT_LT_F64_U32: "VCVT.LT.F64.U32", + VCVT_GT_F64_U32: "VCVT.GT.F64.U32", + VCVT_LE_F64_U32: "VCVT.LE.F64.U32", + VCVT_F64_U32: "VCVT.F64.U32", + VCVT_ZZ_F64_U32: "VCVT.ZZ.F64.U32", + VCVT_EQ_F64_S32: "VCVT.EQ.F64.S32", + VCVT_NE_F64_S32: "VCVT.NE.F64.S32", + VCVT_CS_F64_S32: "VCVT.CS.F64.S32", + VCVT_CC_F64_S32: "VCVT.CC.F64.S32", + VCVT_MI_F64_S32: "VCVT.MI.F64.S32", + VCVT_PL_F64_S32: "VCVT.PL.F64.S32", + VCVT_VS_F64_S32: "VCVT.VS.F64.S32", + VCVT_VC_F64_S32: "VCVT.VC.F64.S32", + VCVT_HI_F64_S32: "VCVT.HI.F64.S32", + VCVT_LS_F64_S32: "VCVT.LS.F64.S32", + VCVT_GE_F64_S32: "VCVT.GE.F64.S32", + VCVT_LT_F64_S32: "VCVT.LT.F64.S32", + VCVT_GT_F64_S32: "VCVT.GT.F64.S32", + VCVT_LE_F64_S32: "VCVT.LE.F64.S32", + VCVT_F64_S32: "VCVT.F64.S32", + VCVT_ZZ_F64_S32: "VCVT.ZZ.F64.S32", + VCVT_EQ_F64_F32: "VCVT.EQ.F64.F32", + VCVT_NE_F64_F32: "VCVT.NE.F64.F32", + VCVT_CS_F64_F32: "VCVT.CS.F64.F32", + VCVT_CC_F64_F32: "VCVT.CC.F64.F32", + VCVT_MI_F64_F32: "VCVT.MI.F64.F32", + VCVT_PL_F64_F32: "VCVT.PL.F64.F32", + VCVT_VS_F64_F32: "VCVT.VS.F64.F32", + VCVT_VC_F64_F32: "VCVT.VC.F64.F32", + VCVT_HI_F64_F32: "VCVT.HI.F64.F32", + VCVT_LS_F64_F32: "VCVT.LS.F64.F32", + VCVT_GE_F64_F32: "VCVT.GE.F64.F32", + VCVT_LT_F64_F32: "VCVT.LT.F64.F32", + VCVT_GT_F64_F32: "VCVT.GT.F64.F32", + VCVT_LE_F64_F32: "VCVT.LE.F64.F32", + VCVT_F64_F32: "VCVT.F64.F32", + VCVT_ZZ_F64_F32: "VCVT.ZZ.F64.F32", + VCVT_EQ_F32_F64: "VCVT.EQ.F32.F64", + VCVT_NE_F32_F64: "VCVT.NE.F32.F64", + VCVT_CS_F32_F64: "VCVT.CS.F32.F64", + VCVT_CC_F32_F64: "VCVT.CC.F32.F64", + VCVT_MI_F32_F64: "VCVT.MI.F32.F64", + VCVT_PL_F32_F64: "VCVT.PL.F32.F64", + VCVT_VS_F32_F64: "VCVT.VS.F32.F64", + VCVT_VC_F32_F64: "VCVT.VC.F32.F64", + VCVT_HI_F32_F64: "VCVT.HI.F32.F64", + VCVT_LS_F32_F64: "VCVT.LS.F32.F64", + VCVT_GE_F32_F64: "VCVT.GE.F32.F64", + VCVT_LT_F32_F64: "VCVT.LT.F32.F64", + VCVT_GT_F32_F64: "VCVT.GT.F32.F64", + VCVT_LE_F32_F64: "VCVT.LE.F32.F64", + VCVT_F32_F64: "VCVT.F32.F64", + VCVT_ZZ_F32_F64: "VCVT.ZZ.F32.F64", + VCVT_EQ_FXS16_F32: "VCVT.EQ.FXS16.F32", + VCVT_NE_FXS16_F32: "VCVT.NE.FXS16.F32", + VCVT_CS_FXS16_F32: "VCVT.CS.FXS16.F32", + VCVT_CC_FXS16_F32: "VCVT.CC.FXS16.F32", + VCVT_MI_FXS16_F32: "VCVT.MI.FXS16.F32", + VCVT_PL_FXS16_F32: "VCVT.PL.FXS16.F32", + VCVT_VS_FXS16_F32: "VCVT.VS.FXS16.F32", + VCVT_VC_FXS16_F32: "VCVT.VC.FXS16.F32", + VCVT_HI_FXS16_F32: "VCVT.HI.FXS16.F32", + VCVT_LS_FXS16_F32: "VCVT.LS.FXS16.F32", + VCVT_GE_FXS16_F32: "VCVT.GE.FXS16.F32", + VCVT_LT_FXS16_F32: "VCVT.LT.FXS16.F32", + VCVT_GT_FXS16_F32: "VCVT.GT.FXS16.F32", + VCVT_LE_FXS16_F32: "VCVT.LE.FXS16.F32", + VCVT_FXS16_F32: "VCVT.FXS16.F32", + VCVT_ZZ_FXS16_F32: "VCVT.ZZ.FXS16.F32", + VCVT_EQ_FXS16_F64: "VCVT.EQ.FXS16.F64", + VCVT_NE_FXS16_F64: "VCVT.NE.FXS16.F64", + VCVT_CS_FXS16_F64: "VCVT.CS.FXS16.F64", + VCVT_CC_FXS16_F64: "VCVT.CC.FXS16.F64", + VCVT_MI_FXS16_F64: "VCVT.MI.FXS16.F64", + VCVT_PL_FXS16_F64: "VCVT.PL.FXS16.F64", + VCVT_VS_FXS16_F64: "VCVT.VS.FXS16.F64", + VCVT_VC_FXS16_F64: "VCVT.VC.FXS16.F64", + VCVT_HI_FXS16_F64: "VCVT.HI.FXS16.F64", + VCVT_LS_FXS16_F64: "VCVT.LS.FXS16.F64", + VCVT_GE_FXS16_F64: "VCVT.GE.FXS16.F64", + VCVT_LT_FXS16_F64: "VCVT.LT.FXS16.F64", + VCVT_GT_FXS16_F64: "VCVT.GT.FXS16.F64", + VCVT_LE_FXS16_F64: "VCVT.LE.FXS16.F64", + VCVT_FXS16_F64: "VCVT.FXS16.F64", + VCVT_ZZ_FXS16_F64: "VCVT.ZZ.FXS16.F64", + VCVT_EQ_FXS32_F32: "VCVT.EQ.FXS32.F32", + VCVT_NE_FXS32_F32: "VCVT.NE.FXS32.F32", + VCVT_CS_FXS32_F32: "VCVT.CS.FXS32.F32", + VCVT_CC_FXS32_F32: "VCVT.CC.FXS32.F32", + VCVT_MI_FXS32_F32: "VCVT.MI.FXS32.F32", + VCVT_PL_FXS32_F32: "VCVT.PL.FXS32.F32", + VCVT_VS_FXS32_F32: "VCVT.VS.FXS32.F32", + VCVT_VC_FXS32_F32: "VCVT.VC.FXS32.F32", + VCVT_HI_FXS32_F32: "VCVT.HI.FXS32.F32", + VCVT_LS_FXS32_F32: "VCVT.LS.FXS32.F32", + VCVT_GE_FXS32_F32: "VCVT.GE.FXS32.F32", + VCVT_LT_FXS32_F32: "VCVT.LT.FXS32.F32", + VCVT_GT_FXS32_F32: "VCVT.GT.FXS32.F32", + VCVT_LE_FXS32_F32: "VCVT.LE.FXS32.F32", + VCVT_FXS32_F32: "VCVT.FXS32.F32", + VCVT_ZZ_FXS32_F32: "VCVT.ZZ.FXS32.F32", + VCVT_EQ_FXS32_F64: "VCVT.EQ.FXS32.F64", + VCVT_NE_FXS32_F64: "VCVT.NE.FXS32.F64", + VCVT_CS_FXS32_F64: "VCVT.CS.FXS32.F64", + VCVT_CC_FXS32_F64: "VCVT.CC.FXS32.F64", + VCVT_MI_FXS32_F64: "VCVT.MI.FXS32.F64", + VCVT_PL_FXS32_F64: "VCVT.PL.FXS32.F64", + VCVT_VS_FXS32_F64: "VCVT.VS.FXS32.F64", + VCVT_VC_FXS32_F64: "VCVT.VC.FXS32.F64", + VCVT_HI_FXS32_F64: "VCVT.HI.FXS32.F64", + VCVT_LS_FXS32_F64: "VCVT.LS.FXS32.F64", + VCVT_GE_FXS32_F64: "VCVT.GE.FXS32.F64", + VCVT_LT_FXS32_F64: "VCVT.LT.FXS32.F64", + VCVT_GT_FXS32_F64: "VCVT.GT.FXS32.F64", + VCVT_LE_FXS32_F64: "VCVT.LE.FXS32.F64", + VCVT_FXS32_F64: "VCVT.FXS32.F64", + VCVT_ZZ_FXS32_F64: "VCVT.ZZ.FXS32.F64", + VCVT_EQ_FXU16_F32: "VCVT.EQ.FXU16.F32", + VCVT_NE_FXU16_F32: "VCVT.NE.FXU16.F32", + VCVT_CS_FXU16_F32: "VCVT.CS.FXU16.F32", + VCVT_CC_FXU16_F32: "VCVT.CC.FXU16.F32", + VCVT_MI_FXU16_F32: "VCVT.MI.FXU16.F32", + VCVT_PL_FXU16_F32: "VCVT.PL.FXU16.F32", + VCVT_VS_FXU16_F32: "VCVT.VS.FXU16.F32", + VCVT_VC_FXU16_F32: "VCVT.VC.FXU16.F32", + VCVT_HI_FXU16_F32: "VCVT.HI.FXU16.F32", + VCVT_LS_FXU16_F32: "VCVT.LS.FXU16.F32", + VCVT_GE_FXU16_F32: "VCVT.GE.FXU16.F32", + VCVT_LT_FXU16_F32: "VCVT.LT.FXU16.F32", + VCVT_GT_FXU16_F32: "VCVT.GT.FXU16.F32", + VCVT_LE_FXU16_F32: "VCVT.LE.FXU16.F32", + VCVT_FXU16_F32: "VCVT.FXU16.F32", + VCVT_ZZ_FXU16_F32: "VCVT.ZZ.FXU16.F32", + VCVT_EQ_FXU16_F64: "VCVT.EQ.FXU16.F64", + VCVT_NE_FXU16_F64: "VCVT.NE.FXU16.F64", + VCVT_CS_FXU16_F64: "VCVT.CS.FXU16.F64", + VCVT_CC_FXU16_F64: "VCVT.CC.FXU16.F64", + VCVT_MI_FXU16_F64: "VCVT.MI.FXU16.F64", + VCVT_PL_FXU16_F64: "VCVT.PL.FXU16.F64", + VCVT_VS_FXU16_F64: "VCVT.VS.FXU16.F64", + VCVT_VC_FXU16_F64: "VCVT.VC.FXU16.F64", + VCVT_HI_FXU16_F64: "VCVT.HI.FXU16.F64", + VCVT_LS_FXU16_F64: "VCVT.LS.FXU16.F64", + VCVT_GE_FXU16_F64: "VCVT.GE.FXU16.F64", + VCVT_LT_FXU16_F64: "VCVT.LT.FXU16.F64", + VCVT_GT_FXU16_F64: "VCVT.GT.FXU16.F64", + VCVT_LE_FXU16_F64: "VCVT.LE.FXU16.F64", + VCVT_FXU16_F64: "VCVT.FXU16.F64", + VCVT_ZZ_FXU16_F64: "VCVT.ZZ.FXU16.F64", + VCVT_EQ_FXU32_F32: "VCVT.EQ.FXU32.F32", + VCVT_NE_FXU32_F32: "VCVT.NE.FXU32.F32", + VCVT_CS_FXU32_F32: "VCVT.CS.FXU32.F32", + VCVT_CC_FXU32_F32: "VCVT.CC.FXU32.F32", + VCVT_MI_FXU32_F32: "VCVT.MI.FXU32.F32", + VCVT_PL_FXU32_F32: "VCVT.PL.FXU32.F32", + VCVT_VS_FXU32_F32: "VCVT.VS.FXU32.F32", + VCVT_VC_FXU32_F32: "VCVT.VC.FXU32.F32", + VCVT_HI_FXU32_F32: "VCVT.HI.FXU32.F32", + VCVT_LS_FXU32_F32: "VCVT.LS.FXU32.F32", + VCVT_GE_FXU32_F32: "VCVT.GE.FXU32.F32", + VCVT_LT_FXU32_F32: "VCVT.LT.FXU32.F32", + VCVT_GT_FXU32_F32: "VCVT.GT.FXU32.F32", + VCVT_LE_FXU32_F32: "VCVT.LE.FXU32.F32", + VCVT_FXU32_F32: "VCVT.FXU32.F32", + VCVT_ZZ_FXU32_F32: "VCVT.ZZ.FXU32.F32", + VCVT_EQ_FXU32_F64: "VCVT.EQ.FXU32.F64", + VCVT_NE_FXU32_F64: "VCVT.NE.FXU32.F64", + VCVT_CS_FXU32_F64: "VCVT.CS.FXU32.F64", + VCVT_CC_FXU32_F64: "VCVT.CC.FXU32.F64", + VCVT_MI_FXU32_F64: "VCVT.MI.FXU32.F64", + VCVT_PL_FXU32_F64: "VCVT.PL.FXU32.F64", + VCVT_VS_FXU32_F64: "VCVT.VS.FXU32.F64", + VCVT_VC_FXU32_F64: "VCVT.VC.FXU32.F64", + VCVT_HI_FXU32_F64: "VCVT.HI.FXU32.F64", + VCVT_LS_FXU32_F64: "VCVT.LS.FXU32.F64", + VCVT_GE_FXU32_F64: "VCVT.GE.FXU32.F64", + VCVT_LT_FXU32_F64: "VCVT.LT.FXU32.F64", + VCVT_GT_FXU32_F64: "VCVT.GT.FXU32.F64", + VCVT_LE_FXU32_F64: "VCVT.LE.FXU32.F64", + VCVT_FXU32_F64: "VCVT.FXU32.F64", + VCVT_ZZ_FXU32_F64: "VCVT.ZZ.FXU32.F64", + VCVTB_EQ_F32_F16: "VCVTB.EQ.F32.F16", + VCVTB_NE_F32_F16: "VCVTB.NE.F32.F16", + VCVTB_CS_F32_F16: "VCVTB.CS.F32.F16", + VCVTB_CC_F32_F16: "VCVTB.CC.F32.F16", + VCVTB_MI_F32_F16: "VCVTB.MI.F32.F16", + VCVTB_PL_F32_F16: "VCVTB.PL.F32.F16", + VCVTB_VS_F32_F16: "VCVTB.VS.F32.F16", + VCVTB_VC_F32_F16: "VCVTB.VC.F32.F16", + VCVTB_HI_F32_F16: "VCVTB.HI.F32.F16", + VCVTB_LS_F32_F16: "VCVTB.LS.F32.F16", + VCVTB_GE_F32_F16: "VCVTB.GE.F32.F16", + VCVTB_LT_F32_F16: "VCVTB.LT.F32.F16", + VCVTB_GT_F32_F16: "VCVTB.GT.F32.F16", + VCVTB_LE_F32_F16: "VCVTB.LE.F32.F16", + VCVTB_F32_F16: "VCVTB.F32.F16", + VCVTB_ZZ_F32_F16: "VCVTB.ZZ.F32.F16", + VCVTB_EQ_F16_F32: "VCVTB.EQ.F16.F32", + VCVTB_NE_F16_F32: "VCVTB.NE.F16.F32", + VCVTB_CS_F16_F32: "VCVTB.CS.F16.F32", + VCVTB_CC_F16_F32: "VCVTB.CC.F16.F32", + VCVTB_MI_F16_F32: "VCVTB.MI.F16.F32", + VCVTB_PL_F16_F32: "VCVTB.PL.F16.F32", + VCVTB_VS_F16_F32: "VCVTB.VS.F16.F32", + VCVTB_VC_F16_F32: "VCVTB.VC.F16.F32", + VCVTB_HI_F16_F32: "VCVTB.HI.F16.F32", + VCVTB_LS_F16_F32: "VCVTB.LS.F16.F32", + VCVTB_GE_F16_F32: "VCVTB.GE.F16.F32", + VCVTB_LT_F16_F32: "VCVTB.LT.F16.F32", + VCVTB_GT_F16_F32: "VCVTB.GT.F16.F32", + VCVTB_LE_F16_F32: "VCVTB.LE.F16.F32", + VCVTB_F16_F32: "VCVTB.F16.F32", + VCVTB_ZZ_F16_F32: "VCVTB.ZZ.F16.F32", + VCVTT_EQ_F32_F16: "VCVTT.EQ.F32.F16", + VCVTT_NE_F32_F16: "VCVTT.NE.F32.F16", + VCVTT_CS_F32_F16: "VCVTT.CS.F32.F16", + VCVTT_CC_F32_F16: "VCVTT.CC.F32.F16", + VCVTT_MI_F32_F16: "VCVTT.MI.F32.F16", + VCVTT_PL_F32_F16: "VCVTT.PL.F32.F16", + VCVTT_VS_F32_F16: "VCVTT.VS.F32.F16", + VCVTT_VC_F32_F16: "VCVTT.VC.F32.F16", + VCVTT_HI_F32_F16: "VCVTT.HI.F32.F16", + VCVTT_LS_F32_F16: "VCVTT.LS.F32.F16", + VCVTT_GE_F32_F16: "VCVTT.GE.F32.F16", + VCVTT_LT_F32_F16: "VCVTT.LT.F32.F16", + VCVTT_GT_F32_F16: "VCVTT.GT.F32.F16", + VCVTT_LE_F32_F16: "VCVTT.LE.F32.F16", + VCVTT_F32_F16: "VCVTT.F32.F16", + VCVTT_ZZ_F32_F16: "VCVTT.ZZ.F32.F16", + VCVTT_EQ_F16_F32: "VCVTT.EQ.F16.F32", + VCVTT_NE_F16_F32: "VCVTT.NE.F16.F32", + VCVTT_CS_F16_F32: "VCVTT.CS.F16.F32", + VCVTT_CC_F16_F32: "VCVTT.CC.F16.F32", + VCVTT_MI_F16_F32: "VCVTT.MI.F16.F32", + VCVTT_PL_F16_F32: "VCVTT.PL.F16.F32", + VCVTT_VS_F16_F32: "VCVTT.VS.F16.F32", + VCVTT_VC_F16_F32: "VCVTT.VC.F16.F32", + VCVTT_HI_F16_F32: "VCVTT.HI.F16.F32", + VCVTT_LS_F16_F32: "VCVTT.LS.F16.F32", + VCVTT_GE_F16_F32: "VCVTT.GE.F16.F32", + VCVTT_LT_F16_F32: "VCVTT.LT.F16.F32", + VCVTT_GT_F16_F32: "VCVTT.GT.F16.F32", + VCVTT_LE_F16_F32: "VCVTT.LE.F16.F32", + VCVTT_F16_F32: "VCVTT.F16.F32", + VCVTT_ZZ_F16_F32: "VCVTT.ZZ.F16.F32", + VCVTR_EQ_U32_F32: "VCVTR.EQ.U32.F32", + VCVTR_NE_U32_F32: "VCVTR.NE.U32.F32", + VCVTR_CS_U32_F32: "VCVTR.CS.U32.F32", + VCVTR_CC_U32_F32: "VCVTR.CC.U32.F32", + VCVTR_MI_U32_F32: "VCVTR.MI.U32.F32", + VCVTR_PL_U32_F32: "VCVTR.PL.U32.F32", + VCVTR_VS_U32_F32: "VCVTR.VS.U32.F32", + VCVTR_VC_U32_F32: "VCVTR.VC.U32.F32", + VCVTR_HI_U32_F32: "VCVTR.HI.U32.F32", + VCVTR_LS_U32_F32: "VCVTR.LS.U32.F32", + VCVTR_GE_U32_F32: "VCVTR.GE.U32.F32", + VCVTR_LT_U32_F32: "VCVTR.LT.U32.F32", + VCVTR_GT_U32_F32: "VCVTR.GT.U32.F32", + VCVTR_LE_U32_F32: "VCVTR.LE.U32.F32", + VCVTR_U32_F32: "VCVTR.U32.F32", + VCVTR_ZZ_U32_F32: "VCVTR.ZZ.U32.F32", + VCVTR_EQ_U32_F64: "VCVTR.EQ.U32.F64", + VCVTR_NE_U32_F64: "VCVTR.NE.U32.F64", + VCVTR_CS_U32_F64: "VCVTR.CS.U32.F64", + VCVTR_CC_U32_F64: "VCVTR.CC.U32.F64", + VCVTR_MI_U32_F64: "VCVTR.MI.U32.F64", + VCVTR_PL_U32_F64: "VCVTR.PL.U32.F64", + VCVTR_VS_U32_F64: "VCVTR.VS.U32.F64", + VCVTR_VC_U32_F64: "VCVTR.VC.U32.F64", + VCVTR_HI_U32_F64: "VCVTR.HI.U32.F64", + VCVTR_LS_U32_F64: "VCVTR.LS.U32.F64", + VCVTR_GE_U32_F64: "VCVTR.GE.U32.F64", + VCVTR_LT_U32_F64: "VCVTR.LT.U32.F64", + VCVTR_GT_U32_F64: "VCVTR.GT.U32.F64", + VCVTR_LE_U32_F64: "VCVTR.LE.U32.F64", + VCVTR_U32_F64: "VCVTR.U32.F64", + VCVTR_ZZ_U32_F64: "VCVTR.ZZ.U32.F64", + VCVTR_EQ_S32_F32: "VCVTR.EQ.S32.F32", + VCVTR_NE_S32_F32: "VCVTR.NE.S32.F32", + VCVTR_CS_S32_F32: "VCVTR.CS.S32.F32", + VCVTR_CC_S32_F32: "VCVTR.CC.S32.F32", + VCVTR_MI_S32_F32: "VCVTR.MI.S32.F32", + VCVTR_PL_S32_F32: "VCVTR.PL.S32.F32", + VCVTR_VS_S32_F32: "VCVTR.VS.S32.F32", + VCVTR_VC_S32_F32: "VCVTR.VC.S32.F32", + VCVTR_HI_S32_F32: "VCVTR.HI.S32.F32", + VCVTR_LS_S32_F32: "VCVTR.LS.S32.F32", + VCVTR_GE_S32_F32: "VCVTR.GE.S32.F32", + VCVTR_LT_S32_F32: "VCVTR.LT.S32.F32", + VCVTR_GT_S32_F32: "VCVTR.GT.S32.F32", + VCVTR_LE_S32_F32: "VCVTR.LE.S32.F32", + VCVTR_S32_F32: "VCVTR.S32.F32", + VCVTR_ZZ_S32_F32: "VCVTR.ZZ.S32.F32", + VCVTR_EQ_S32_F64: "VCVTR.EQ.S32.F64", + VCVTR_NE_S32_F64: "VCVTR.NE.S32.F64", + VCVTR_CS_S32_F64: "VCVTR.CS.S32.F64", + VCVTR_CC_S32_F64: "VCVTR.CC.S32.F64", + VCVTR_MI_S32_F64: "VCVTR.MI.S32.F64", + VCVTR_PL_S32_F64: "VCVTR.PL.S32.F64", + VCVTR_VS_S32_F64: "VCVTR.VS.S32.F64", + VCVTR_VC_S32_F64: "VCVTR.VC.S32.F64", + VCVTR_HI_S32_F64: "VCVTR.HI.S32.F64", + VCVTR_LS_S32_F64: "VCVTR.LS.S32.F64", + VCVTR_GE_S32_F64: "VCVTR.GE.S32.F64", + VCVTR_LT_S32_F64: "VCVTR.LT.S32.F64", + VCVTR_GT_S32_F64: "VCVTR.GT.S32.F64", + VCVTR_LE_S32_F64: "VCVTR.LE.S32.F64", + VCVTR_S32_F64: "VCVTR.S32.F64", + VCVTR_ZZ_S32_F64: "VCVTR.ZZ.S32.F64", + VCVT_EQ_U32_F32: "VCVT.EQ.U32.F32", + VCVT_NE_U32_F32: "VCVT.NE.U32.F32", + VCVT_CS_U32_F32: "VCVT.CS.U32.F32", + VCVT_CC_U32_F32: "VCVT.CC.U32.F32", + VCVT_MI_U32_F32: "VCVT.MI.U32.F32", + VCVT_PL_U32_F32: "VCVT.PL.U32.F32", + VCVT_VS_U32_F32: "VCVT.VS.U32.F32", + VCVT_VC_U32_F32: "VCVT.VC.U32.F32", + VCVT_HI_U32_F32: "VCVT.HI.U32.F32", + VCVT_LS_U32_F32: "VCVT.LS.U32.F32", + VCVT_GE_U32_F32: "VCVT.GE.U32.F32", + VCVT_LT_U32_F32: "VCVT.LT.U32.F32", + VCVT_GT_U32_F32: "VCVT.GT.U32.F32", + VCVT_LE_U32_F32: "VCVT.LE.U32.F32", + VCVT_U32_F32: "VCVT.U32.F32", + VCVT_ZZ_U32_F32: "VCVT.ZZ.U32.F32", + VCVT_EQ_U32_F64: "VCVT.EQ.U32.F64", + VCVT_NE_U32_F64: "VCVT.NE.U32.F64", + VCVT_CS_U32_F64: "VCVT.CS.U32.F64", + VCVT_CC_U32_F64: "VCVT.CC.U32.F64", + VCVT_MI_U32_F64: "VCVT.MI.U32.F64", + VCVT_PL_U32_F64: "VCVT.PL.U32.F64", + VCVT_VS_U32_F64: "VCVT.VS.U32.F64", + VCVT_VC_U32_F64: "VCVT.VC.U32.F64", + VCVT_HI_U32_F64: "VCVT.HI.U32.F64", + VCVT_LS_U32_F64: "VCVT.LS.U32.F64", + VCVT_GE_U32_F64: "VCVT.GE.U32.F64", + VCVT_LT_U32_F64: "VCVT.LT.U32.F64", + VCVT_GT_U32_F64: "VCVT.GT.U32.F64", + VCVT_LE_U32_F64: "VCVT.LE.U32.F64", + VCVT_U32_F64: "VCVT.U32.F64", + VCVT_ZZ_U32_F64: "VCVT.ZZ.U32.F64", + VCVT_EQ_S32_F32: "VCVT.EQ.S32.F32", + VCVT_NE_S32_F32: "VCVT.NE.S32.F32", + VCVT_CS_S32_F32: "VCVT.CS.S32.F32", + VCVT_CC_S32_F32: "VCVT.CC.S32.F32", + VCVT_MI_S32_F32: "VCVT.MI.S32.F32", + VCVT_PL_S32_F32: "VCVT.PL.S32.F32", + VCVT_VS_S32_F32: "VCVT.VS.S32.F32", + VCVT_VC_S32_F32: "VCVT.VC.S32.F32", + VCVT_HI_S32_F32: "VCVT.HI.S32.F32", + VCVT_LS_S32_F32: "VCVT.LS.S32.F32", + VCVT_GE_S32_F32: "VCVT.GE.S32.F32", + VCVT_LT_S32_F32: "VCVT.LT.S32.F32", + VCVT_GT_S32_F32: "VCVT.GT.S32.F32", + VCVT_LE_S32_F32: "VCVT.LE.S32.F32", + VCVT_S32_F32: "VCVT.S32.F32", + VCVT_ZZ_S32_F32: "VCVT.ZZ.S32.F32", + VCVT_EQ_S32_F64: "VCVT.EQ.S32.F64", + VCVT_NE_S32_F64: "VCVT.NE.S32.F64", + VCVT_CS_S32_F64: "VCVT.CS.S32.F64", + VCVT_CC_S32_F64: "VCVT.CC.S32.F64", + VCVT_MI_S32_F64: "VCVT.MI.S32.F64", + VCVT_PL_S32_F64: "VCVT.PL.S32.F64", + VCVT_VS_S32_F64: "VCVT.VS.S32.F64", + VCVT_VC_S32_F64: "VCVT.VC.S32.F64", + VCVT_HI_S32_F64: "VCVT.HI.S32.F64", + VCVT_LS_S32_F64: "VCVT.LS.S32.F64", + VCVT_GE_S32_F64: "VCVT.GE.S32.F64", + VCVT_LT_S32_F64: "VCVT.LT.S32.F64", + VCVT_GT_S32_F64: "VCVT.GT.S32.F64", + VCVT_LE_S32_F64: "VCVT.LE.S32.F64", + VCVT_S32_F64: "VCVT.S32.F64", + VCVT_ZZ_S32_F64: "VCVT.ZZ.S32.F64", + VDIV_EQ_F32: "VDIV.EQ.F32", + VDIV_NE_F32: "VDIV.NE.F32", + VDIV_CS_F32: "VDIV.CS.F32", + VDIV_CC_F32: "VDIV.CC.F32", + VDIV_MI_F32: "VDIV.MI.F32", + VDIV_PL_F32: "VDIV.PL.F32", + VDIV_VS_F32: "VDIV.VS.F32", + VDIV_VC_F32: "VDIV.VC.F32", + VDIV_HI_F32: "VDIV.HI.F32", + VDIV_LS_F32: "VDIV.LS.F32", + VDIV_GE_F32: "VDIV.GE.F32", + VDIV_LT_F32: "VDIV.LT.F32", + VDIV_GT_F32: "VDIV.GT.F32", + VDIV_LE_F32: "VDIV.LE.F32", + VDIV_F32: "VDIV.F32", + VDIV_ZZ_F32: "VDIV.ZZ.F32", + VDIV_EQ_F64: "VDIV.EQ.F64", + VDIV_NE_F64: "VDIV.NE.F64", + VDIV_CS_F64: "VDIV.CS.F64", + VDIV_CC_F64: "VDIV.CC.F64", + VDIV_MI_F64: "VDIV.MI.F64", + VDIV_PL_F64: "VDIV.PL.F64", + VDIV_VS_F64: "VDIV.VS.F64", + VDIV_VC_F64: "VDIV.VC.F64", + VDIV_HI_F64: "VDIV.HI.F64", + VDIV_LS_F64: "VDIV.LS.F64", + VDIV_GE_F64: "VDIV.GE.F64", + VDIV_LT_F64: "VDIV.LT.F64", + VDIV_GT_F64: "VDIV.GT.F64", + VDIV_LE_F64: "VDIV.LE.F64", + VDIV_F64: "VDIV.F64", + VDIV_ZZ_F64: "VDIV.ZZ.F64", + VLDR_EQ: "VLDR.EQ", + VLDR_NE: "VLDR.NE", + VLDR_CS: "VLDR.CS", + VLDR_CC: "VLDR.CC", + VLDR_MI: "VLDR.MI", + VLDR_PL: "VLDR.PL", + VLDR_VS: "VLDR.VS", + VLDR_VC: "VLDR.VC", + VLDR_HI: "VLDR.HI", + VLDR_LS: "VLDR.LS", + VLDR_GE: "VLDR.GE", + VLDR_LT: "VLDR.LT", + VLDR_GT: "VLDR.GT", + VLDR_LE: "VLDR.LE", + VLDR: "VLDR", + VLDR_ZZ: "VLDR.ZZ", + VMLA_EQ_F32: "VMLA.EQ.F32", + VMLA_NE_F32: "VMLA.NE.F32", + VMLA_CS_F32: "VMLA.CS.F32", + VMLA_CC_F32: "VMLA.CC.F32", + VMLA_MI_F32: "VMLA.MI.F32", + VMLA_PL_F32: "VMLA.PL.F32", + VMLA_VS_F32: "VMLA.VS.F32", + VMLA_VC_F32: "VMLA.VC.F32", + VMLA_HI_F32: "VMLA.HI.F32", + VMLA_LS_F32: "VMLA.LS.F32", + VMLA_GE_F32: "VMLA.GE.F32", + VMLA_LT_F32: "VMLA.LT.F32", + VMLA_GT_F32: "VMLA.GT.F32", + VMLA_LE_F32: "VMLA.LE.F32", + VMLA_F32: "VMLA.F32", + VMLA_ZZ_F32: "VMLA.ZZ.F32", + VMLA_EQ_F64: "VMLA.EQ.F64", + VMLA_NE_F64: "VMLA.NE.F64", + VMLA_CS_F64: "VMLA.CS.F64", + VMLA_CC_F64: "VMLA.CC.F64", + VMLA_MI_F64: "VMLA.MI.F64", + VMLA_PL_F64: "VMLA.PL.F64", + VMLA_VS_F64: "VMLA.VS.F64", + VMLA_VC_F64: "VMLA.VC.F64", + VMLA_HI_F64: "VMLA.HI.F64", + VMLA_LS_F64: "VMLA.LS.F64", + VMLA_GE_F64: "VMLA.GE.F64", + VMLA_LT_F64: "VMLA.LT.F64", + VMLA_GT_F64: "VMLA.GT.F64", + VMLA_LE_F64: "VMLA.LE.F64", + VMLA_F64: "VMLA.F64", + VMLA_ZZ_F64: "VMLA.ZZ.F64", + VMLS_EQ_F32: "VMLS.EQ.F32", + VMLS_NE_F32: "VMLS.NE.F32", + VMLS_CS_F32: "VMLS.CS.F32", + VMLS_CC_F32: "VMLS.CC.F32", + VMLS_MI_F32: "VMLS.MI.F32", + VMLS_PL_F32: "VMLS.PL.F32", + VMLS_VS_F32: "VMLS.VS.F32", + VMLS_VC_F32: "VMLS.VC.F32", + VMLS_HI_F32: "VMLS.HI.F32", + VMLS_LS_F32: "VMLS.LS.F32", + VMLS_GE_F32: "VMLS.GE.F32", + VMLS_LT_F32: "VMLS.LT.F32", + VMLS_GT_F32: "VMLS.GT.F32", + VMLS_LE_F32: "VMLS.LE.F32", + VMLS_F32: "VMLS.F32", + VMLS_ZZ_F32: "VMLS.ZZ.F32", + VMLS_EQ_F64: "VMLS.EQ.F64", + VMLS_NE_F64: "VMLS.NE.F64", + VMLS_CS_F64: "VMLS.CS.F64", + VMLS_CC_F64: "VMLS.CC.F64", + VMLS_MI_F64: "VMLS.MI.F64", + VMLS_PL_F64: "VMLS.PL.F64", + VMLS_VS_F64: "VMLS.VS.F64", + VMLS_VC_F64: "VMLS.VC.F64", + VMLS_HI_F64: "VMLS.HI.F64", + VMLS_LS_F64: "VMLS.LS.F64", + VMLS_GE_F64: "VMLS.GE.F64", + VMLS_LT_F64: "VMLS.LT.F64", + VMLS_GT_F64: "VMLS.GT.F64", + VMLS_LE_F64: "VMLS.LE.F64", + VMLS_F64: "VMLS.F64", + VMLS_ZZ_F64: "VMLS.ZZ.F64", + VMOV_EQ: "VMOV.EQ", + VMOV_NE: "VMOV.NE", + VMOV_CS: "VMOV.CS", + VMOV_CC: "VMOV.CC", + VMOV_MI: "VMOV.MI", + VMOV_PL: "VMOV.PL", + VMOV_VS: "VMOV.VS", + VMOV_VC: "VMOV.VC", + VMOV_HI: "VMOV.HI", + VMOV_LS: "VMOV.LS", + VMOV_GE: "VMOV.GE", + VMOV_LT: "VMOV.LT", + VMOV_GT: "VMOV.GT", + VMOV_LE: "VMOV.LE", + VMOV: "VMOV", + VMOV_ZZ: "VMOV.ZZ", + VMOV_EQ_32: "VMOV.EQ.32", + VMOV_NE_32: "VMOV.NE.32", + VMOV_CS_32: "VMOV.CS.32", + VMOV_CC_32: "VMOV.CC.32", + VMOV_MI_32: "VMOV.MI.32", + VMOV_PL_32: "VMOV.PL.32", + VMOV_VS_32: "VMOV.VS.32", + VMOV_VC_32: "VMOV.VC.32", + VMOV_HI_32: "VMOV.HI.32", + VMOV_LS_32: "VMOV.LS.32", + VMOV_GE_32: "VMOV.GE.32", + VMOV_LT_32: "VMOV.LT.32", + VMOV_GT_32: "VMOV.GT.32", + VMOV_LE_32: "VMOV.LE.32", + VMOV_32: "VMOV.32", + VMOV_ZZ_32: "VMOV.ZZ.32", + VMOV_EQ_F32: "VMOV.EQ.F32", + VMOV_NE_F32: "VMOV.NE.F32", + VMOV_CS_F32: "VMOV.CS.F32", + VMOV_CC_F32: "VMOV.CC.F32", + VMOV_MI_F32: "VMOV.MI.F32", + VMOV_PL_F32: "VMOV.PL.F32", + VMOV_VS_F32: "VMOV.VS.F32", + VMOV_VC_F32: "VMOV.VC.F32", + VMOV_HI_F32: "VMOV.HI.F32", + VMOV_LS_F32: "VMOV.LS.F32", + VMOV_GE_F32: "VMOV.GE.F32", + VMOV_LT_F32: "VMOV.LT.F32", + VMOV_GT_F32: "VMOV.GT.F32", + VMOV_LE_F32: "VMOV.LE.F32", + VMOV_F32: "VMOV.F32", + VMOV_ZZ_F32: "VMOV.ZZ.F32", + VMOV_EQ_F64: "VMOV.EQ.F64", + VMOV_NE_F64: "VMOV.NE.F64", + VMOV_CS_F64: "VMOV.CS.F64", + VMOV_CC_F64: "VMOV.CC.F64", + VMOV_MI_F64: "VMOV.MI.F64", + VMOV_PL_F64: "VMOV.PL.F64", + VMOV_VS_F64: "VMOV.VS.F64", + VMOV_VC_F64: "VMOV.VC.F64", + VMOV_HI_F64: "VMOV.HI.F64", + VMOV_LS_F64: "VMOV.LS.F64", + VMOV_GE_F64: "VMOV.GE.F64", + VMOV_LT_F64: "VMOV.LT.F64", + VMOV_GT_F64: "VMOV.GT.F64", + VMOV_LE_F64: "VMOV.LE.F64", + VMOV_F64: "VMOV.F64", + VMOV_ZZ_F64: "VMOV.ZZ.F64", + VMRS_EQ: "VMRS.EQ", + VMRS_NE: "VMRS.NE", + VMRS_CS: "VMRS.CS", + VMRS_CC: "VMRS.CC", + VMRS_MI: "VMRS.MI", + VMRS_PL: "VMRS.PL", + VMRS_VS: "VMRS.VS", + VMRS_VC: "VMRS.VC", + VMRS_HI: "VMRS.HI", + VMRS_LS: "VMRS.LS", + VMRS_GE: "VMRS.GE", + VMRS_LT: "VMRS.LT", + VMRS_GT: "VMRS.GT", + VMRS_LE: "VMRS.LE", + VMRS: "VMRS", + VMRS_ZZ: "VMRS.ZZ", + VMSR_EQ: "VMSR.EQ", + VMSR_NE: "VMSR.NE", + VMSR_CS: "VMSR.CS", + VMSR_CC: "VMSR.CC", + VMSR_MI: "VMSR.MI", + VMSR_PL: "VMSR.PL", + VMSR_VS: "VMSR.VS", + VMSR_VC: "VMSR.VC", + VMSR_HI: "VMSR.HI", + VMSR_LS: "VMSR.LS", + VMSR_GE: "VMSR.GE", + VMSR_LT: "VMSR.LT", + VMSR_GT: "VMSR.GT", + VMSR_LE: "VMSR.LE", + VMSR: "VMSR", + VMSR_ZZ: "VMSR.ZZ", + VMUL_EQ_F32: "VMUL.EQ.F32", + VMUL_NE_F32: "VMUL.NE.F32", + VMUL_CS_F32: "VMUL.CS.F32", + VMUL_CC_F32: "VMUL.CC.F32", + VMUL_MI_F32: "VMUL.MI.F32", + VMUL_PL_F32: "VMUL.PL.F32", + VMUL_VS_F32: "VMUL.VS.F32", + VMUL_VC_F32: "VMUL.VC.F32", + VMUL_HI_F32: "VMUL.HI.F32", + VMUL_LS_F32: "VMUL.LS.F32", + VMUL_GE_F32: "VMUL.GE.F32", + VMUL_LT_F32: "VMUL.LT.F32", + VMUL_GT_F32: "VMUL.GT.F32", + VMUL_LE_F32: "VMUL.LE.F32", + VMUL_F32: "VMUL.F32", + VMUL_ZZ_F32: "VMUL.ZZ.F32", + VMUL_EQ_F64: "VMUL.EQ.F64", + VMUL_NE_F64: "VMUL.NE.F64", + VMUL_CS_F64: "VMUL.CS.F64", + VMUL_CC_F64: "VMUL.CC.F64", + VMUL_MI_F64: "VMUL.MI.F64", + VMUL_PL_F64: "VMUL.PL.F64", + VMUL_VS_F64: "VMUL.VS.F64", + VMUL_VC_F64: "VMUL.VC.F64", + VMUL_HI_F64: "VMUL.HI.F64", + VMUL_LS_F64: "VMUL.LS.F64", + VMUL_GE_F64: "VMUL.GE.F64", + VMUL_LT_F64: "VMUL.LT.F64", + VMUL_GT_F64: "VMUL.GT.F64", + VMUL_LE_F64: "VMUL.LE.F64", + VMUL_F64: "VMUL.F64", + VMUL_ZZ_F64: "VMUL.ZZ.F64", + VNEG_EQ_F32: "VNEG.EQ.F32", + VNEG_NE_F32: "VNEG.NE.F32", + VNEG_CS_F32: "VNEG.CS.F32", + VNEG_CC_F32: "VNEG.CC.F32", + VNEG_MI_F32: "VNEG.MI.F32", + VNEG_PL_F32: "VNEG.PL.F32", + VNEG_VS_F32: "VNEG.VS.F32", + VNEG_VC_F32: "VNEG.VC.F32", + VNEG_HI_F32: "VNEG.HI.F32", + VNEG_LS_F32: "VNEG.LS.F32", + VNEG_GE_F32: "VNEG.GE.F32", + VNEG_LT_F32: "VNEG.LT.F32", + VNEG_GT_F32: "VNEG.GT.F32", + VNEG_LE_F32: "VNEG.LE.F32", + VNEG_F32: "VNEG.F32", + VNEG_ZZ_F32: "VNEG.ZZ.F32", + VNEG_EQ_F64: "VNEG.EQ.F64", + VNEG_NE_F64: "VNEG.NE.F64", + VNEG_CS_F64: "VNEG.CS.F64", + VNEG_CC_F64: "VNEG.CC.F64", + VNEG_MI_F64: "VNEG.MI.F64", + VNEG_PL_F64: "VNEG.PL.F64", + VNEG_VS_F64: "VNEG.VS.F64", + VNEG_VC_F64: "VNEG.VC.F64", + VNEG_HI_F64: "VNEG.HI.F64", + VNEG_LS_F64: "VNEG.LS.F64", + VNEG_GE_F64: "VNEG.GE.F64", + VNEG_LT_F64: "VNEG.LT.F64", + VNEG_GT_F64: "VNEG.GT.F64", + VNEG_LE_F64: "VNEG.LE.F64", + VNEG_F64: "VNEG.F64", + VNEG_ZZ_F64: "VNEG.ZZ.F64", + VNMLS_EQ_F32: "VNMLS.EQ.F32", + VNMLS_NE_F32: "VNMLS.NE.F32", + VNMLS_CS_F32: "VNMLS.CS.F32", + VNMLS_CC_F32: "VNMLS.CC.F32", + VNMLS_MI_F32: "VNMLS.MI.F32", + VNMLS_PL_F32: "VNMLS.PL.F32", + VNMLS_VS_F32: "VNMLS.VS.F32", + VNMLS_VC_F32: "VNMLS.VC.F32", + VNMLS_HI_F32: "VNMLS.HI.F32", + VNMLS_LS_F32: "VNMLS.LS.F32", + VNMLS_GE_F32: "VNMLS.GE.F32", + VNMLS_LT_F32: "VNMLS.LT.F32", + VNMLS_GT_F32: "VNMLS.GT.F32", + VNMLS_LE_F32: "VNMLS.LE.F32", + VNMLS_F32: "VNMLS.F32", + VNMLS_ZZ_F32: "VNMLS.ZZ.F32", + VNMLS_EQ_F64: "VNMLS.EQ.F64", + VNMLS_NE_F64: "VNMLS.NE.F64", + VNMLS_CS_F64: "VNMLS.CS.F64", + VNMLS_CC_F64: "VNMLS.CC.F64", + VNMLS_MI_F64: "VNMLS.MI.F64", + VNMLS_PL_F64: "VNMLS.PL.F64", + VNMLS_VS_F64: "VNMLS.VS.F64", + VNMLS_VC_F64: "VNMLS.VC.F64", + VNMLS_HI_F64: "VNMLS.HI.F64", + VNMLS_LS_F64: "VNMLS.LS.F64", + VNMLS_GE_F64: "VNMLS.GE.F64", + VNMLS_LT_F64: "VNMLS.LT.F64", + VNMLS_GT_F64: "VNMLS.GT.F64", + VNMLS_LE_F64: "VNMLS.LE.F64", + VNMLS_F64: "VNMLS.F64", + VNMLS_ZZ_F64: "VNMLS.ZZ.F64", + VNMLA_EQ_F32: "VNMLA.EQ.F32", + VNMLA_NE_F32: "VNMLA.NE.F32", + VNMLA_CS_F32: "VNMLA.CS.F32", + VNMLA_CC_F32: "VNMLA.CC.F32", + VNMLA_MI_F32: "VNMLA.MI.F32", + VNMLA_PL_F32: "VNMLA.PL.F32", + VNMLA_VS_F32: "VNMLA.VS.F32", + VNMLA_VC_F32: "VNMLA.VC.F32", + VNMLA_HI_F32: "VNMLA.HI.F32", + VNMLA_LS_F32: "VNMLA.LS.F32", + VNMLA_GE_F32: "VNMLA.GE.F32", + VNMLA_LT_F32: "VNMLA.LT.F32", + VNMLA_GT_F32: "VNMLA.GT.F32", + VNMLA_LE_F32: "VNMLA.LE.F32", + VNMLA_F32: "VNMLA.F32", + VNMLA_ZZ_F32: "VNMLA.ZZ.F32", + VNMLA_EQ_F64: "VNMLA.EQ.F64", + VNMLA_NE_F64: "VNMLA.NE.F64", + VNMLA_CS_F64: "VNMLA.CS.F64", + VNMLA_CC_F64: "VNMLA.CC.F64", + VNMLA_MI_F64: "VNMLA.MI.F64", + VNMLA_PL_F64: "VNMLA.PL.F64", + VNMLA_VS_F64: "VNMLA.VS.F64", + VNMLA_VC_F64: "VNMLA.VC.F64", + VNMLA_HI_F64: "VNMLA.HI.F64", + VNMLA_LS_F64: "VNMLA.LS.F64", + VNMLA_GE_F64: "VNMLA.GE.F64", + VNMLA_LT_F64: "VNMLA.LT.F64", + VNMLA_GT_F64: "VNMLA.GT.F64", + VNMLA_LE_F64: "VNMLA.LE.F64", + VNMLA_F64: "VNMLA.F64", + VNMLA_ZZ_F64: "VNMLA.ZZ.F64", + VNMUL_EQ_F32: "VNMUL.EQ.F32", + VNMUL_NE_F32: "VNMUL.NE.F32", + VNMUL_CS_F32: "VNMUL.CS.F32", + VNMUL_CC_F32: "VNMUL.CC.F32", + VNMUL_MI_F32: "VNMUL.MI.F32", + VNMUL_PL_F32: "VNMUL.PL.F32", + VNMUL_VS_F32: "VNMUL.VS.F32", + VNMUL_VC_F32: "VNMUL.VC.F32", + VNMUL_HI_F32: "VNMUL.HI.F32", + VNMUL_LS_F32: "VNMUL.LS.F32", + VNMUL_GE_F32: "VNMUL.GE.F32", + VNMUL_LT_F32: "VNMUL.LT.F32", + VNMUL_GT_F32: "VNMUL.GT.F32", + VNMUL_LE_F32: "VNMUL.LE.F32", + VNMUL_F32: "VNMUL.F32", + VNMUL_ZZ_F32: "VNMUL.ZZ.F32", + VNMUL_EQ_F64: "VNMUL.EQ.F64", + VNMUL_NE_F64: "VNMUL.NE.F64", + VNMUL_CS_F64: "VNMUL.CS.F64", + VNMUL_CC_F64: "VNMUL.CC.F64", + VNMUL_MI_F64: "VNMUL.MI.F64", + VNMUL_PL_F64: "VNMUL.PL.F64", + VNMUL_VS_F64: "VNMUL.VS.F64", + VNMUL_VC_F64: "VNMUL.VC.F64", + VNMUL_HI_F64: "VNMUL.HI.F64", + VNMUL_LS_F64: "VNMUL.LS.F64", + VNMUL_GE_F64: "VNMUL.GE.F64", + VNMUL_LT_F64: "VNMUL.LT.F64", + VNMUL_GT_F64: "VNMUL.GT.F64", + VNMUL_LE_F64: "VNMUL.LE.F64", + VNMUL_F64: "VNMUL.F64", + VNMUL_ZZ_F64: "VNMUL.ZZ.F64", + VSQRT_EQ_F32: "VSQRT.EQ.F32", + VSQRT_NE_F32: "VSQRT.NE.F32", + VSQRT_CS_F32: "VSQRT.CS.F32", + VSQRT_CC_F32: "VSQRT.CC.F32", + VSQRT_MI_F32: "VSQRT.MI.F32", + VSQRT_PL_F32: "VSQRT.PL.F32", + VSQRT_VS_F32: "VSQRT.VS.F32", + VSQRT_VC_F32: "VSQRT.VC.F32", + VSQRT_HI_F32: "VSQRT.HI.F32", + VSQRT_LS_F32: "VSQRT.LS.F32", + VSQRT_GE_F32: "VSQRT.GE.F32", + VSQRT_LT_F32: "VSQRT.LT.F32", + VSQRT_GT_F32: "VSQRT.GT.F32", + VSQRT_LE_F32: "VSQRT.LE.F32", + VSQRT_F32: "VSQRT.F32", + VSQRT_ZZ_F32: "VSQRT.ZZ.F32", + VSQRT_EQ_F64: "VSQRT.EQ.F64", + VSQRT_NE_F64: "VSQRT.NE.F64", + VSQRT_CS_F64: "VSQRT.CS.F64", + VSQRT_CC_F64: "VSQRT.CC.F64", + VSQRT_MI_F64: "VSQRT.MI.F64", + VSQRT_PL_F64: "VSQRT.PL.F64", + VSQRT_VS_F64: "VSQRT.VS.F64", + VSQRT_VC_F64: "VSQRT.VC.F64", + VSQRT_HI_F64: "VSQRT.HI.F64", + VSQRT_LS_F64: "VSQRT.LS.F64", + VSQRT_GE_F64: "VSQRT.GE.F64", + VSQRT_LT_F64: "VSQRT.LT.F64", + VSQRT_GT_F64: "VSQRT.GT.F64", + VSQRT_LE_F64: "VSQRT.LE.F64", + VSQRT_F64: "VSQRT.F64", + VSQRT_ZZ_F64: "VSQRT.ZZ.F64", + VSTR_EQ: "VSTR.EQ", + VSTR_NE: "VSTR.NE", + VSTR_CS: "VSTR.CS", + VSTR_CC: "VSTR.CC", + VSTR_MI: "VSTR.MI", + VSTR_PL: "VSTR.PL", + VSTR_VS: "VSTR.VS", + VSTR_VC: "VSTR.VC", + VSTR_HI: "VSTR.HI", + VSTR_LS: "VSTR.LS", + VSTR_GE: "VSTR.GE", + VSTR_LT: "VSTR.LT", + VSTR_GT: "VSTR.GT", + VSTR_LE: "VSTR.LE", + VSTR: "VSTR", + VSTR_ZZ: "VSTR.ZZ", + VSUB_EQ_F32: "VSUB.EQ.F32", + VSUB_NE_F32: "VSUB.NE.F32", + VSUB_CS_F32: "VSUB.CS.F32", + VSUB_CC_F32: "VSUB.CC.F32", + VSUB_MI_F32: "VSUB.MI.F32", + VSUB_PL_F32: "VSUB.PL.F32", + VSUB_VS_F32: "VSUB.VS.F32", + VSUB_VC_F32: "VSUB.VC.F32", + VSUB_HI_F32: "VSUB.HI.F32", + VSUB_LS_F32: "VSUB.LS.F32", + VSUB_GE_F32: "VSUB.GE.F32", + VSUB_LT_F32: "VSUB.LT.F32", + VSUB_GT_F32: "VSUB.GT.F32", + VSUB_LE_F32: "VSUB.LE.F32", + VSUB_F32: "VSUB.F32", + VSUB_ZZ_F32: "VSUB.ZZ.F32", + VSUB_EQ_F64: "VSUB.EQ.F64", + VSUB_NE_F64: "VSUB.NE.F64", + VSUB_CS_F64: "VSUB.CS.F64", + VSUB_CC_F64: "VSUB.CC.F64", + VSUB_MI_F64: "VSUB.MI.F64", + VSUB_PL_F64: "VSUB.PL.F64", + VSUB_VS_F64: "VSUB.VS.F64", + VSUB_VC_F64: "VSUB.VC.F64", + VSUB_HI_F64: "VSUB.HI.F64", + VSUB_LS_F64: "VSUB.LS.F64", + VSUB_GE_F64: "VSUB.GE.F64", + VSUB_LT_F64: "VSUB.LT.F64", + VSUB_GT_F64: "VSUB.GT.F64", + VSUB_LE_F64: "VSUB.LE.F64", + VSUB_F64: "VSUB.F64", + VSUB_ZZ_F64: "VSUB.ZZ.F64", + WFE_EQ: "WFE.EQ", + WFE_NE: "WFE.NE", + WFE_CS: "WFE.CS", + WFE_CC: "WFE.CC", + WFE_MI: "WFE.MI", + WFE_PL: "WFE.PL", + WFE_VS: "WFE.VS", + WFE_VC: "WFE.VC", + WFE_HI: "WFE.HI", + WFE_LS: "WFE.LS", + WFE_GE: "WFE.GE", + WFE_LT: "WFE.LT", + WFE_GT: "WFE.GT", + WFE_LE: "WFE.LE", + WFE: "WFE", + WFE_ZZ: "WFE.ZZ", + WFI_EQ: "WFI.EQ", + WFI_NE: "WFI.NE", + WFI_CS: "WFI.CS", + WFI_CC: "WFI.CC", + WFI_MI: "WFI.MI", + WFI_PL: "WFI.PL", + WFI_VS: "WFI.VS", + WFI_VC: "WFI.VC", + WFI_HI: "WFI.HI", + WFI_LS: "WFI.LS", + WFI_GE: "WFI.GE", + WFI_LT: "WFI.LT", + WFI_GT: "WFI.GT", + WFI_LE: "WFI.LE", + WFI: "WFI", + WFI_ZZ: "WFI.ZZ", + YIELD_EQ: "YIELD.EQ", + YIELD_NE: "YIELD.NE", + YIELD_CS: "YIELD.CS", + YIELD_CC: "YIELD.CC", + YIELD_MI: "YIELD.MI", + YIELD_PL: "YIELD.PL", + YIELD_VS: "YIELD.VS", + YIELD_VC: "YIELD.VC", + YIELD_HI: "YIELD.HI", + YIELD_LS: "YIELD.LS", + YIELD_GE: "YIELD.GE", + YIELD_LT: "YIELD.LT", + YIELD_GT: "YIELD.GT", + YIELD_LE: "YIELD.LE", + YIELD: "YIELD", + YIELD_ZZ: "YIELD.ZZ", +} + +var instFormats = [...]instFormat{ + {0x0fe00000, 0x02a00000, 2, ADC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // ADC{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|1|0|1|S|Rn:4|Rd:4|imm12:12 + {0x0fe00090, 0x00a00010, 4, ADC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // ADC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|1|0|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 + {0x0fe00010, 0x00a00000, 2, ADC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // ADC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|1|0|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 + {0x0fe00000, 0x02800000, 2, ADD_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // ADD{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|1|0|0|S|Rn:4|Rd:4|imm12:12 + {0x0fe00090, 0x00800010, 4, ADD_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // ADD{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|1|0|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 + {0x0fe00010, 0x00800000, 2, ADD_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // ADD{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|1|0|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 + {0x0fef0000, 0x028d0000, 2, ADD_EQ, 0x14011c04, instArgs{arg_R_12, arg_SP, arg_const}}, // ADD{S}<c> <Rd>,SP,#<const> cond:4|0|0|1|0|1|0|0|S|1|1|0|1|Rd:4|imm12:12 + {0x0fef0010, 0x008d0000, 2, ADD_EQ, 0x14011c04, instArgs{arg_R_12, arg_SP, arg_R_shift_imm}}, // ADD{S}<c> <Rd>,SP,<Rm>{,<shift>} cond:4|0|0|0|0|1|0|0|S|1|1|0|1|Rd:4|imm5:5|type:2|0|Rm:4 + {0x0fe00000, 0x02000000, 2, AND_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // AND{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|0|0|0|S|Rn:4|Rd:4|imm12:12 + {0x0fe00090, 0x00000010, 4, AND_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // AND{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|0|0|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 + {0x0fe00010, 0x00000000, 2, AND_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // AND{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|0|0|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 + {0x0fef0070, 0x01a00040, 4, ASR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_imm5_32}}, // ASR{S}<c> <Rd>,<Rm>,#<imm5_32> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|1|0|0|Rm:4 + {0x0fef00f0, 0x01a00050, 4, ASR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_R_8}}, // ASR{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|1|0|1|Rn:4 + {0x0f000000, 0x0a000000, 4, B_EQ, 0x1c04, instArgs{arg_label24}}, // B<c> <label24> cond:4|1|0|1|0|imm24:24 + {0x0fe0007f, 0x07c0001f, 4, BFC_EQ, 0x1c04, instArgs{arg_R_12, arg_imm5, arg_lsb_width}}, // BFC<c> <Rd>,#<lsb>,#<width> cond:4|0|1|1|1|1|1|0|msb:5|Rd:4|lsb:5|0|0|1|1|1|1|1 + {0x0fe00070, 0x07c00010, 2, BFI_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_imm5, arg_lsb_width}}, // BFI<c> <Rd>,<Rn>,#<lsb>,#<width> cond:4|0|1|1|1|1|1|0|msb:5|Rd:4|lsb:5|0|0|1|Rn:4 + {0x0fe00000, 0x03c00000, 2, BIC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // BIC{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|1|1|1|0|S|Rn:4|Rd:4|imm12:12 + {0x0fe00090, 0x01c00010, 4, BIC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // BIC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|1|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 + {0x0fe00010, 0x01c00000, 2, BIC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // BIC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|1|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 + {0x0ff000f0, 0x01200070, 4, BKPT_EQ, 0x1c04, instArgs{arg_imm_12at8_4at0}}, // BKPT<c> #<imm12+4> cond:4|0|0|0|1|0|0|1|0|imm12:12|0|1|1|1|imm4:4 + {0x0f000000, 0x0b000000, 4, BL_EQ, 0x1c04, instArgs{arg_label24}}, // BL<c> <label24> cond:4|1|0|1|1|imm24:24 + {0xfe000000, 0xfa000000, 4, BLX, 0x0, instArgs{arg_label24H}}, // BLX <label24H> 1|1|1|1|1|0|1|H|imm24:24 + {0x0ffffff0, 0x012fff30, 4, BLX_EQ, 0x1c04, instArgs{arg_R_0}}, // BLX<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 + {0x0ff000f0, 0x012fff30, 3, BLX_EQ, 0x1c04, instArgs{arg_R_0}}, // BLX<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 + {0x0ffffff0, 0x012fff10, 4, BX_EQ, 0x1c04, instArgs{arg_R_0}}, // BX<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 + {0x0ff000f0, 0x012fff10, 3, BX_EQ, 0x1c04, instArgs{arg_R_0}}, // BX<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 + {0x0ffffff0, 0x012fff20, 4, BXJ_EQ, 0x1c04, instArgs{arg_R_0}}, // BXJ<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|0|Rm:4 + {0x0ff000f0, 0x012fff20, 3, BXJ_EQ, 0x1c04, instArgs{arg_R_0}}, // BXJ<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|0|Rm:4 + {0xffffffff, 0xf57ff01f, 4, CLREX, 0x0, instArgs{}}, // CLREX 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|1|(1)|(1)|(1)|(1) + {0xfff000f0, 0xf57ff01f, 3, CLREX, 0x0, instArgs{}}, // CLREX 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|1|(1)|(1)|(1)|(1) + {0x0fff0ff0, 0x016f0f10, 4, CLZ_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // CLZ<c> <Rd>,<Rm> cond:4|0|0|0|1|0|1|1|0|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 + {0x0ff000f0, 0x016f0f10, 3, CLZ_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // CLZ<c> <Rd>,<Rm> cond:4|0|0|0|1|0|1|1|0|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 + {0x0ff0f000, 0x03700000, 4, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // CMN<c> <Rn>,#<const> cond:4|0|0|1|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 + {0x0ff00000, 0x03700000, 3, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // CMN<c> <Rn>,#<const> cond:4|0|0|1|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 + {0x0ff0f090, 0x01700010, 4, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // CMN<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 + {0x0ff00090, 0x01700010, 3, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // CMN<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 + {0x0ff0f010, 0x01700000, 4, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // CMN<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 + {0x0ff00010, 0x01700000, 3, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // CMN<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 + {0x0ff0f000, 0x03500000, 4, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // CMP<c> <Rn>,#<const> cond:4|0|0|1|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 + {0x0ff00000, 0x03500000, 3, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // CMP<c> <Rn>,#<const> cond:4|0|0|1|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 + {0x0ff0f090, 0x01500010, 4, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // CMP<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 + {0x0ff00090, 0x01500010, 3, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // CMP<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 + {0x0ff0f010, 0x01500000, 4, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // CMP<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 + {0x0ff00010, 0x01500000, 3, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // CMP<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 + {0x0ffffff0, 0x0320f0f0, 4, DBG_EQ, 0x1c04, instArgs{arg_option}}, // DBG<c> #<option> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|1|1|1|1|option:4 + {0x0fff00f0, 0x0320f0f0, 3, DBG_EQ, 0x1c04, instArgs{arg_option}}, // DBG<c> #<option> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|1|1|1|1|option:4 + {0xfffffff0, 0xf57ff050, 4, DMB, 0x0, instArgs{arg_option}}, // DMB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|1|option:4 + {0xfff000f0, 0xf57ff050, 3, DMB, 0x0, instArgs{arg_option}}, // DMB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|1|option:4 + {0xfffffff0, 0xf57ff040, 4, DSB, 0x0, instArgs{arg_option}}, // DSB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|0|option:4 + {0xfff000f0, 0xf57ff040, 3, DSB, 0x0, instArgs{arg_option}}, // DSB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|0|option:4 + {0x0fe00000, 0x02200000, 2, EOR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // EOR{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|0|0|1|S|Rn:4|Rd:4|imm12:12 + {0x0fe00090, 0x00200010, 4, EOR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // EOR{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|0|0|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 + {0x0fe00010, 0x00200000, 2, EOR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // EOR{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|0|0|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 + {0xfffffff0, 0xf57ff060, 4, ISB, 0x0, instArgs{arg_option}}, // ISB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|1|0|option:4 + {0xfff000f0, 0xf57ff060, 3, ISB, 0x0, instArgs{arg_option}}, // ISB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|1|0|option:4 + {0x0fd00000, 0x08900000, 2, LDM_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // LDM<c> <Rn>{!},<registers> cond:4|1|0|0|0|1|0|W|1|Rn:4|register_list:16 + {0x0fd00000, 0x08100000, 4, LDMDA_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // LDMDA<c> <Rn>{!},<registers> cond:4|1|0|0|0|0|0|W|1|Rn:4|register_list:16 + {0x0fd00000, 0x09100000, 4, LDMDB_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // LDMDB<c> <Rn>{!},<registers> cond:4|1|0|0|1|0|0|W|1|Rn:4|register_list:16 + {0x0fd00000, 0x09900000, 4, LDMIB_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // LDMIB<c> <Rn>{!},<registers> cond:4|1|0|0|1|1|0|W|1|Rn:4|register_list:16 + {0x0f7f0000, 0x051f0000, 4, LDR_EQ, 0x1c04, instArgs{arg_R_12, arg_label_pm_12}}, // LDR<c> <Rt>,<label+/-12> cond:4|0|1|0|(1)|U|0|(0)|1|1|1|1|1|Rt:4|imm12:12 + {0x0e5f0000, 0x051f0000, 3, LDR_EQ, 0x1c04, instArgs{arg_R_12, arg_label_pm_12}}, // LDR<c> <Rt>,<label+/-12> cond:4|0|1|0|(1)|U|0|(0)|1|1|1|1|1|Rt:4|imm12:12 + {0x0e500010, 0x06100000, 2, LDR_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_W}}, // LDR<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|0|W|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 + {0x0e500000, 0x04100000, 2, LDR_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_W}}, // LDR<c> <Rt>,[<Rn>{,#+/-<imm12>}]{!} cond:4|0|1|0|P|U|0|W|1|Rn:4|Rt:4|imm12:12 + {0x0f7f0000, 0x055f0000, 4, LDRB_EQ, 0x1c04, instArgs{arg_R_12, arg_label_pm_12}}, // LDRB<c> <Rt>,<label+/-12> cond:4|0|1|0|(1)|U|1|(0)|1|1|1|1|1|Rt:4|imm12:12 + {0x0e5f0000, 0x055f0000, 3, LDRB_EQ, 0x1c04, instArgs{arg_R_12, arg_label_pm_12}}, // LDRB<c> <Rt>,<label+/-12> cond:4|0|1|0|(1)|U|1|(0)|1|1|1|1|1|Rt:4|imm12:12 + {0x0e500010, 0x06500000, 2, LDRB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_W}}, // LDRB<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|1|W|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 + {0x0e500000, 0x04500000, 2, LDRB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_W}}, // LDRB<c> <Rt>,[<Rn>{,#+/-<imm12>}]{!} cond:4|0|1|0|P|U|1|W|1|Rn:4|Rt:4|imm12:12 + {0x0f700000, 0x04700000, 4, LDRBT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_postindex}}, // LDRBT<c> <Rt>,[<Rn>],#+/-<imm12> cond:4|0|1|0|0|U|1|1|1|Rn:4|Rt:4|imm12:12 + {0x0f700010, 0x06700000, 4, LDRBT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_postindex}}, // LDRBT<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>} cond:4|0|1|1|0|U|1|1|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 + {0x0e500ff0, 0x000000d0, 4, LDRD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R_pm_R_W}}, // LDRD<c> <Rt1>,<Rt2>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|0|1|Rm:4 + {0x0e5000f0, 0x000000d0, 3, LDRD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R_pm_R_W}}, // LDRD<c> <Rt1>,<Rt2>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|0|1|Rm:4 + {0x0e5000f0, 0x004000d0, 2, LDRD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R_pm_imm8_W}}, // LDRD<c> <Rt1>,<Rt2>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|0|Rn:4|Rt:4|imm4H:4|1|1|0|1|imm4L:4 + {0x0ff00fff, 0x01900f9f, 4, LDREX_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R}}, // LDREX<c> <Rt>,[<Rn>] cond:4|0|0|0|1|1|0|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) + {0x0ff000f0, 0x01900f9f, 3, LDREX_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R}}, // LDREX<c> <Rt>,[<Rn>] cond:4|0|0|0|1|1|0|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) + {0x0ff00fff, 0x01d00f9f, 4, LDREXB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R}}, // LDREXB<c> <Rt>, [<Rn>] cond:4|0|0|0|1|1|1|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) + {0x0ff000f0, 0x01d00f9f, 3, LDREXB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R}}, // LDREXB<c> <Rt>, [<Rn>] cond:4|0|0|0|1|1|1|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) + {0x0ff00fff, 0x01b00f9f, 4, LDREXD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R}}, // LDREXD<c> <Rt1>,<Rt2>,[<Rn>] cond:4|0|0|0|1|1|0|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) + {0x0ff000f0, 0x01b00f9f, 3, LDREXD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R}}, // LDREXD<c> <Rt1>,<Rt2>,[<Rn>] cond:4|0|0|0|1|1|0|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) + {0x0ff00fff, 0x01f00f9f, 4, LDREXH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R}}, // LDREXH<c> <Rt>, [<Rn>] cond:4|0|0|0|1|1|1|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) + {0x0ff000f0, 0x01f00f9f, 3, LDREXH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R}}, // LDREXH<c> <Rt>, [<Rn>] cond:4|0|0|0|1|1|1|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) + {0x0e500ff0, 0x001000b0, 2, LDRH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_W}}, // LDRH<c> <Rt>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|1|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4 + {0x0e5000f0, 0x005000b0, 2, LDRH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_W}}, // LDRH<c> <Rt>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|1|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4 + {0x0f7000f0, 0x007000b0, 4, LDRHT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_postindex}}, // LDRHT<c> <Rt>, [<Rn>] {,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|1|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4 + {0x0f700ff0, 0x003000b0, 4, LDRHT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_postindex}}, // LDRHT<c> <Rt>, [<Rn>], +/-<Rm> cond:4|0|0|0|0|U|0|1|1|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4 + {0x0e500ff0, 0x001000d0, 2, LDRSB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_W}}, // LDRSB<c> <Rt>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|1|Rn:4|Rt:4|0|0|0|0|1|1|0|1|Rm:4 + {0x0e5000f0, 0x005000d0, 2, LDRSB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_W}}, // LDRSB<c> <Rt>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|1|Rn:4|Rt:4|imm4H:4|1|1|0|1|imm4L:4 + {0x0f7000f0, 0x007000d0, 4, LDRSBT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_postindex}}, // LDRSBT<c> <Rt>, [<Rn>] {,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|1|Rn:4|Rt:4|imm4H:4|1|1|0|1|imm4L:4 + {0x0f700ff0, 0x003000d0, 4, LDRSBT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_postindex}}, // LDRSBT<c> <Rt>, [<Rn>], +/-<Rm> cond:4|0|0|0|0|U|0|1|1|Rn:4|Rt:4|0|0|0|0|1|1|0|1|Rm:4 + {0x0e500ff0, 0x001000f0, 2, LDRSH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_W}}, // LDRSH<c> <Rt>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|1|Rn:4|Rt:4|0|0|0|0|1|1|1|1|Rm:4 + {0x0e5000f0, 0x005000f0, 2, LDRSH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_W}}, // LDRSH<c> <Rt>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|1|Rn:4|Rt:4|imm4H:4|1|1|1|1|imm4L:4 + {0x0f7000f0, 0x007000f0, 4, LDRSHT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_postindex}}, // LDRSHT<c> <Rt>, [<Rn>] {,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|1|Rn:4|Rt:4|imm4H:4|1|1|1|1|imm4L:4 + {0x0f700ff0, 0x003000f0, 4, LDRSHT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_postindex}}, // LDRSHT<c> <Rt>, [<Rn>], +/-<Rm> cond:4|0|0|0|0|U|0|1|1|Rn:4|Rt:4|0|0|0|0|1|1|1|1|Rm:4 + {0x0f700000, 0x04300000, 4, LDRT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_postindex}}, // LDRT<c> <Rt>, [<Rn>] {,#+/-<imm12>} cond:4|0|1|0|0|U|0|1|1|Rn:4|Rt:4|imm12:12 + {0x0f700010, 0x06300000, 4, LDRT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_postindex}}, // LDRT<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>} cond:4|0|1|1|0|U|0|1|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 + {0x0fef0070, 0x01a00000, 2, LSL_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_imm5_nz}}, // LSL{S}<c> <Rd>,<Rm>,#<imm5_nz> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|0|0|0|Rm:4 + {0x0fef00f0, 0x01a00010, 4, LSL_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_R_8}}, // LSL{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|0|0|1|Rn:4 + {0x0fef0070, 0x01a00020, 4, LSR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_imm5_32}}, // LSR{S}<c> <Rd>,<Rm>,#<imm5_32> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|0|1|0|Rm:4 + {0x0fef00f0, 0x01a00030, 4, LSR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_R_8}}, // LSR{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|0|1|1|Rn:4 + {0x0fe000f0, 0x00200090, 4, MLA_EQ, 0x14011c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // MLA{S}<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|0|0|0|0|0|1|S|Rd:4|Ra:4|Rm:4|1|0|0|1|Rn:4 + {0x0ff000f0, 0x00600090, 4, MLS_EQ, 0x1c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // MLS<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|0|0|0|0|1|1|0|Rd:4|Ra:4|Rm:4|1|0|0|1|Rn:4 + {0x0ff00000, 0x03400000, 4, MOVT_EQ, 0x1c04, instArgs{arg_R_12, arg_imm_4at16_12at0}}, // MOVT<c> <Rd>,#<imm12+4> cond:4|0|0|1|1|0|1|0|0|imm4:4|Rd:4|imm12:12 + {0x0ff00000, 0x03000000, 4, MOVW_EQ, 0x1c04, instArgs{arg_R_12, arg_imm_4at16_12at0}}, // MOVW<c> <Rd>,#<imm12+4> cond:4|0|0|1|1|0|0|0|0|imm4:4|Rd:4|imm12:12 + {0x0fef0000, 0x03a00000, 2, MOV_EQ, 0x14011c04, instArgs{arg_R_12, arg_const}}, // MOV{S}<c> <Rd>,#<const> cond:4|0|0|1|1|1|0|1|S|0|0|0|0|Rd:4|imm12:12 + {0x0fef0ff0, 0x01a00000, 2, MOV_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0}}, // MOV{S}<c> <Rd>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|0|0|0|0|0|0|0|0|Rm:4 + {0x0fff0fff, 0x010f0000, 4, MRS_EQ, 0x1c04, instArgs{arg_R_12, arg_APSR}}, // MRS<c> <Rd>,APSR cond:4|0|0|0|1|0|0|0|0|(1)|(1)|(1)|(1)|Rd:4|(0)|(0)|(0)|(0)|0|0|0|0|(0)|(0)|(0)|(0) + {0x0ff000f0, 0x010f0000, 3, MRS_EQ, 0x1c04, instArgs{arg_R_12, arg_APSR}}, // MRS<c> <Rd>,APSR cond:4|0|0|0|1|0|0|0|0|(1)|(1)|(1)|(1)|Rd:4|(0)|(0)|(0)|(0)|0|0|0|0|(0)|(0)|(0)|(0) + {0x0fe0f0f0, 0x00000090, 4, MUL_EQ, 0x14011c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // MUL{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|0|0|0|0|S|Rd:4|(0)|(0)|(0)|(0)|Rm:4|1|0|0|1|Rn:4 + {0x0fe000f0, 0x00000090, 3, MUL_EQ, 0x14011c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // MUL{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|0|0|0|0|S|Rd:4|(0)|(0)|(0)|(0)|Rm:4|1|0|0|1|Rn:4 + {0x0fef0000, 0x03e00000, 2, MVN_EQ, 0x14011c04, instArgs{arg_R_12, arg_const}}, // MVN{S}<c> <Rd>,#<const> cond:4|0|0|1|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm12:12 + {0x0fe00000, 0x03e00000, 1, MVN_EQ, 0x14011c04, instArgs{arg_R_12, arg_const}}, // MVN{S}<c> <Rd>,#<const> cond:4|0|0|1|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm12:12 + {0x0fef0090, 0x01e00010, 4, MVN_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_shift_R}}, // MVN{S}<c> <Rd>,<Rm>,<type> <Rs> cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|Rs:4|0|type:2|1|Rm:4 + {0x0fe00090, 0x01e00010, 3, MVN_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_shift_R}}, // MVN{S}<c> <Rd>,<Rm>,<type> <Rs> cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|Rs:4|0|type:2|1|Rm:4 + {0x0fef0010, 0x01e00000, 2, MVN_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_shift_imm}}, // MVN{S}<c> <Rd>,<Rm>{,<shift>} cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm5:5|type:2|0|Rm:4 + {0x0fe00010, 0x01e00000, 1, MVN_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_shift_imm}}, // MVN{S}<c> <Rd>,<Rm>{,<shift>} cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm5:5|type:2|0|Rm:4 + {0x0fffffff, 0x0320f000, 4, NOP_EQ, 0x1c04, instArgs{}}, // NOP<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|0 + {0x0fff00ff, 0x0320f000, 3, NOP_EQ, 0x1c04, instArgs{}}, // NOP<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|0 + {0x0fe00000, 0x03800000, 2, ORR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // ORR{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|1|1|0|0|S|Rn:4|Rd:4|imm12:12 + {0x0fe00090, 0x01800010, 4, ORR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // ORR{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|1|0|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 + {0x0fe00010, 0x01800000, 2, ORR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // ORR{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|1|0|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 + {0x0ff00030, 0x06800010, 4, PKHBT_EQ, 0x6011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // PKH<BT,TB><c> <Rd>,<Rn>,<Rm>{,LSL #<imm5>} cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|imm5:5|tb|0|1|Rm:4 + {0xff7ff000, 0xf55ff000, 4, PLD, 0x0, instArgs{arg_label_pm_12}}, // PLD <label+/-12> 1|1|1|1|0|1|0|1|U|(1)|0|1|1|1|1|1|(1)|(1)|(1)|(1)|imm12:12 + {0xff3f0000, 0xf55ff000, 3, PLD, 0x0, instArgs{arg_label_pm_12}}, // PLD <label+/-12> 1|1|1|1|0|1|0|1|U|(1)|0|1|1|1|1|1|(1)|(1)|(1)|(1)|imm12:12 + {0xff30f000, 0xf510f000, 2, PLD_W, 0x1601, instArgs{arg_mem_R_pm_imm12_offset}}, // PLD{W} [<Rn>,#+/-<imm12>] 1|1|1|1|0|1|0|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12 + {0xff300000, 0xf510f000, 1, PLD_W, 0x1601, instArgs{arg_mem_R_pm_imm12_offset}}, // PLD{W} [<Rn>,#+/-<imm12>] 1|1|1|1|0|1|0|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12 + {0xff30f010, 0xf710f000, 4, PLD_W, 0x1601, instArgs{arg_mem_R_pm_R_shift_imm_offset}}, // PLD{W} [<Rn>,+/-<Rm>{, <shift>}] 1|1|1|1|0|1|1|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4 + {0xff300010, 0xf710f000, 3, PLD_W, 0x1601, instArgs{arg_mem_R_pm_R_shift_imm_offset}}, // PLD{W} [<Rn>,+/-<Rm>{, <shift>}] 1|1|1|1|0|1|1|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4 + {0xff70f000, 0xf450f000, 4, PLI, 0x0, instArgs{arg_mem_R_pm_imm12_offset}}, // PLI [<Rn>,#+/-<imm12>] 1|1|1|1|0|1|0|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12 + {0xff700000, 0xf450f000, 3, PLI, 0x0, instArgs{arg_mem_R_pm_imm12_offset}}, // PLI [<Rn>,#+/-<imm12>] 1|1|1|1|0|1|0|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12 + {0xff70f010, 0xf650f000, 4, PLI, 0x0, instArgs{arg_mem_R_pm_R_shift_imm_offset}}, // PLI [<Rn>,+/-<Rm>{, <shift>}] 1|1|1|1|0|1|1|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4 + {0xff700010, 0xf650f000, 3, PLI, 0x0, instArgs{arg_mem_R_pm_R_shift_imm_offset}}, // PLI [<Rn>,+/-<Rm>{, <shift>}] 1|1|1|1|0|1|1|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4 + {0x0fff0000, 0x08bd0000, 4, POP_EQ, 0x1c04, instArgs{arg_registers2}}, // POP<c> <registers2> cond:4|1|0|0|0|1|0|1|1|1|1|0|1|register_list:16 + {0x0fff0fff, 0x049d0004, 4, POP_EQ, 0x1c04, instArgs{arg_registers1}}, // POP<c> <registers1> cond:4|0|1|0|0|1|0|0|1|1|1|0|1|Rt:4|0|0|0|0|0|0|0|0|0|1|0|0 + {0x0fff0000, 0x092d0000, 4, PUSH_EQ, 0x1c04, instArgs{arg_registers2}}, // PUSH<c> <registers2> cond:4|1|0|0|1|0|0|1|0|1|1|0|1|register_list:16 + {0x0fff0fff, 0x052d0004, 4, PUSH_EQ, 0x1c04, instArgs{arg_registers1}}, // PUSH<c> <registers1> cond:4|0|1|0|1|0|0|1|0|1|1|0|1|Rt:4|0|0|0|0|0|0|0|0|0|1|0|0 + {0x0ff00ff0, 0x06200f10, 4, QADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 + {0x0ff000f0, 0x06200f10, 3, QADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 + {0x0ff00ff0, 0x06200f90, 4, QADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 + {0x0ff000f0, 0x06200f90, 3, QADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 + {0x0ff00ff0, 0x01000050, 4, QADD_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_R_16}}, // QADD<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|0|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4 + {0x0ff000f0, 0x01000050, 3, QADD_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_R_16}}, // QADD<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|0|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4 + {0x0ff00ff0, 0x06200f30, 4, QASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 + {0x0ff000f0, 0x06200f30, 3, QASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 + {0x0ff00ff0, 0x01400050, 4, QDADD_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_R_16}}, // QDADD<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|1|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4 + {0x0ff000f0, 0x01400050, 3, QDADD_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_R_16}}, // QDADD<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|1|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4 + {0x0ff00ff0, 0x01600050, 4, QDSUB_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_R_16}}, // QDSUB<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|1|1|0|Rn:4|Rd:4|0|0|0|0|0|1|0|1|Rm:4 + {0x0ff00ff0, 0x06200f50, 4, QSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 + {0x0ff000f0, 0x06200f50, 3, QSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 + {0x0ff00ff0, 0x06200f70, 4, QSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 + {0x0ff000f0, 0x06200f70, 3, QSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 + {0x0ff00ff0, 0x06200ff0, 4, QSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 + {0x0ff000f0, 0x06200ff0, 3, QSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 + {0x0ff00ff0, 0x01200050, 4, QSUB_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_R_16}}, // QSUB<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|0|1|0|Rn:4|Rd:4|0|0|0|0|0|1|0|1|Rm:4 + {0x0fff0ff0, 0x06ff0f30, 4, RBIT_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // RBIT<c> <Rd>,<Rm> cond:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 + {0x0ff000f0, 0x06ff0f30, 3, RBIT_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // RBIT<c> <Rd>,<Rm> cond:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 + {0x0fff0ff0, 0x06bf0fb0, 4, REV16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // REV16<c> <Rd>,<Rm> cond:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 + {0x0ff000f0, 0x06bf0fb0, 3, REV16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // REV16<c> <Rd>,<Rm> cond:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 + {0x0fff0ff0, 0x06bf0f30, 4, REV_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // REV<c> <Rd>,<Rm> cond:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 + {0x0ff000f0, 0x06bf0f30, 3, REV_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // REV<c> <Rd>,<Rm> cond:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 + {0x0fff0ff0, 0x06ff0fb0, 4, REVSH_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // REVSH<c> <Rd>,<Rm> cond:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 + {0x0ff000f0, 0x06ff0fb0, 3, REVSH_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // REVSH<c> <Rd>,<Rm> cond:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 + {0x0fef0070, 0x01a00060, 2, ROR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_imm5}}, // ROR{S}<c> <Rd>,<Rm>,#<imm5> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|1|1|0|Rm:4 + {0x0fef00f0, 0x01a00070, 4, ROR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_R_8}}, // ROR{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|1|1|1|Rn:4 + {0x0fef0ff0, 0x01a00060, 4, RRX_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0}}, // RRX{S}<c> <Rd>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|0|0|0|0|0|1|1|0|Rm:4 + {0x0fe00000, 0x02600000, 2, RSB_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // RSB{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|0|1|1|S|Rn:4|Rd:4|imm12:12 + {0x0fe00090, 0x00600010, 4, RSB_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // RSB{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|0|1|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 + {0x0fe00010, 0x00600000, 2, RSB_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // RSB{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|0|1|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 + {0x0fe00000, 0x02e00000, 2, RSC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // RSC{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|1|1|1|S|Rn:4|Rd:4|imm12:12 + {0x0fe00090, 0x00e00010, 4, RSC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // RSC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|1|1|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 + {0x0fe00010, 0x00e00000, 2, RSC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // RSC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|1|1|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 + {0x0ff00ff0, 0x06100f10, 4, SADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 + {0x0ff000f0, 0x06100f10, 3, SADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 + {0x0ff00ff0, 0x06100f90, 4, SADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 + {0x0ff000f0, 0x06100f90, 3, SADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 + {0x0ff00ff0, 0x06100f30, 4, SASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 + {0x0ff000f0, 0x06100f30, 3, SASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 + {0x0fe00000, 0x02c00000, 2, SBC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // SBC{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|1|1|0|S|Rn:4|Rd:4|imm12:12 + {0x0fe00090, 0x00c00010, 4, SBC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // SBC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|1|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 + {0x0fe00010, 0x00c00000, 2, SBC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // SBC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|1|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 + {0x0fe00070, 0x07a00050, 4, SBFX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_imm5, arg_widthm1}}, // SBFX<c> <Rd>,<Rn>,#<lsb>,#<widthm1> cond:4|0|1|1|1|1|0|1|widthm1:5|Rd:4|lsb:5|1|0|1|Rn:4 + {0x0ff00ff0, 0x06800fb0, 4, SEL_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SEL<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 + {0x0ff000f0, 0x06800fb0, 3, SEL_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SEL<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 + {0xfffffdff, 0xf1010000, 4, SETEND, 0x0, instArgs{arg_endian}}, // SETEND <endian_specifier> 1|1|1|1|0|0|0|1|0|0|0|0|0|0|0|1|0|0|0|0|0|0|E|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0) + {0xfffffc00, 0xf1010000, 3, SETEND, 0x0, instArgs{arg_endian}}, // SETEND <endian_specifier> 1|1|1|1|0|0|0|1|0|0|0|0|0|0|0|1|0|0|0|0|0|0|E|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0) + {0x0fffffff, 0x0320f004, 4, SEV_EQ, 0x1c04, instArgs{}}, // SEV<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|1|0|0 + {0x0fff00ff, 0x0320f004, 3, SEV_EQ, 0x1c04, instArgs{}}, // SEV<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|1|0|0 + {0x0ff00ff0, 0x06300f10, 4, SHADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 + {0x0ff000f0, 0x06300f10, 3, SHADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 + {0x0ff00ff0, 0x06300f90, 4, SHADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 + {0x0ff000f0, 0x06300f90, 3, SHADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 + {0x0ff00ff0, 0x06300f30, 4, SHASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 + {0x0ff000f0, 0x06300f30, 3, SHASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 + {0x0ff00ff0, 0x06300f50, 4, SHSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 + {0x0ff000f0, 0x06300f50, 3, SHSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 + {0x0ff00ff0, 0x06300f70, 4, SHSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 + {0x0ff000f0, 0x06300f70, 3, SHSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 + {0x0ff00ff0, 0x06300ff0, 4, SHSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 + {0x0ff000f0, 0x06300ff0, 3, SHSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 + {0x0ff00090, 0x01000080, 4, SMLABB_EQ, 0x50106011c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // SMLA<x><y><c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|0|0|1|0|0|0|0|Rd:4|Ra:4|Rm:4|1|M|N|0|Rn:4 + {0x0ff000d0, 0x07000010, 2, SMLAD_EQ, 0x5011c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // SMLAD{X}<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|1|1|1|0|0|0|0|Rd:4|Ra:4|Rm:4|0|0|M|1|Rn:4 + {0x0ff00090, 0x01400080, 4, SMLALBB_EQ, 0x50106011c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // SMLAL<x><y><c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|1|0|1|0|0|RdHi:4|RdLo:4|Rm:4|1|M|N|0|Rn:4 + {0x0ff000d0, 0x07400010, 4, SMLALD_EQ, 0x5011c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // SMLALD{X}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|1|1|1|0|1|0|0|RdHi:4|RdLo:4|Rm:4|0|0|M|1|Rn:4 + {0x0fe000f0, 0x00e00090, 4, SMLAL_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // SMLAL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|1|1|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4 + {0x0ff000b0, 0x01200080, 4, SMLAWB_EQ, 0x6011c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // SMLAW<y><c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|0|0|1|0|0|1|0|Rd:4|Ra:4|Rm:4|1|M|0|0|Rn:4 + {0x0ff000d0, 0x07000050, 2, SMLSD_EQ, 0x5011c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // SMLSD{X}<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|1|1|1|0|0|0|0|Rd:4|Ra:4|Rm:4|0|1|M|1|Rn:4 + {0x0ff000d0, 0x07400050, 4, SMLSLD_EQ, 0x5011c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // SMLSLD{X}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|1|1|1|0|1|0|0|RdHi:4|RdLo:4|Rm:4|0|1|M|1|Rn:4 + {0x0ff000d0, 0x07500010, 2, SMMLA_EQ, 0x5011c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // SMMLA{R}<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|1|1|1|0|1|0|1|Rd:4|Ra:4|Rm:4|0|0|R|1|Rn:4 + {0x0ff000d0, 0x075000d0, 4, SMMLS_EQ, 0x5011c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // SMMLS{R}<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|1|1|1|0|1|0|1|Rd:4|Ra:4|Rm:4|1|1|R|1|Rn:4 + {0x0ff0f0d0, 0x0750f010, 4, SMMUL_EQ, 0x5011c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // SMMUL{R}<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|1|0|1|0|1|Rd:4|1|1|1|1|Rm:4|0|0|R|1|Rn:4 + {0x0ff0f0d0, 0x0700f010, 4, SMUAD_EQ, 0x5011c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // SMUAD{X}<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|1|0|0|0|0|Rd:4|1|1|1|1|Rm:4|0|0|M|1|Rn:4 + {0x0ff0f090, 0x01600080, 4, SMULBB_EQ, 0x50106011c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // SMUL<x><y><c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|0|1|1|0|Rd:4|0|0|0|0|Rm:4|1|M|N|0|Rn:4 + {0x0fe000f0, 0x00c00090, 4, SMULL_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // SMULL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|1|0|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4 + {0x0ff0f0b0, 0x012000a0, 4, SMULWB_EQ, 0x6011c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // SMULW<y><c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|0|0|1|0|Rd:4|0|0|0|0|Rm:4|1|M|1|0|Rn:4 + {0x0ff0f0d0, 0x0700f050, 4, SMUSD_EQ, 0x5011c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // SMUSD{X}<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|1|0|0|0|0|Rd:4|1|1|1|1|Rm:4|0|1|M|1|Rn:4 + {0x0ff00ff0, 0x06a00f30, 4, SSAT16_EQ, 0x1c04, instArgs{arg_R_12, arg_satimm4m1, arg_R_0}}, // SSAT16<c> <Rd>,#<sat_imm4m1>,<Rn> cond:4|0|1|1|0|1|0|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4 + {0x0ff000f0, 0x06a00f30, 3, SSAT16_EQ, 0x1c04, instArgs{arg_R_12, arg_satimm4m1, arg_R_0}}, // SSAT16<c> <Rd>,#<sat_imm4m1>,<Rn> cond:4|0|1|1|0|1|0|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4 + {0x0fe00030, 0x06a00010, 4, SSAT_EQ, 0x1c04, instArgs{arg_R_12, arg_satimm5m1, arg_R_shift_imm}}, // SSAT<c> <Rd>,#<sat_imm5m1>,<Rn>{,<shift>} cond:4|0|1|1|0|1|0|1|sat_imm:5|Rd:4|imm5:5|sh|0|1|Rn:4 + {0x0ff00ff0, 0x06100f50, 4, SSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 + {0x0ff000f0, 0x06100f50, 3, SSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 + {0x0ff00ff0, 0x06100f70, 4, SSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 + {0x0ff000f0, 0x06100f70, 3, SSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 + {0x0ff00ff0, 0x06100ff0, 4, SSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 + {0x0ff000f0, 0x06100ff0, 3, SSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 + {0x0fd00000, 0x08800000, 4, STM_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // STM<c> <Rn>{!},<registers> cond:4|1|0|0|0|1|0|W|0|Rn:4|register_list:16 + {0x0fd00000, 0x08000000, 4, STMDA_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // STMDA<c> <Rn>{!},<registers> cond:4|1|0|0|0|0|0|W|0|Rn:4|register_list:16 + {0x0fd00000, 0x09000000, 2, STMDB_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // STMDB<c> <Rn>{!},<registers> cond:4|1|0|0|1|0|0|W|0|Rn:4|register_list:16 + {0x0fd00000, 0x09800000, 4, STMIB_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // STMIB<c> <Rn>{!},<registers> cond:4|1|0|0|1|1|0|W|0|Rn:4|register_list:16 + {0x0e500018, 0x06000000, 2, STR_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_W}}, // STR<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|0|W|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 + {0x0e500000, 0x04000000, 2, STR_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_W}}, // STR<c> <Rt>,[<Rn>{,#+/-<imm12>}]{!} cond:4|0|1|0|P|U|0|W|0|Rn:4|Rt:4|imm12:12 + {0x0e500010, 0x06400000, 2, STRB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_W}}, // STRB<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|1|W|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 + {0x0e500000, 0x04400000, 2, STRB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_W}}, // STRB<c> <Rt>,[<Rn>{,#+/-<imm12>}]{!} cond:4|0|1|0|P|U|1|W|0|Rn:4|Rt:4|imm12:12 + {0x0f700000, 0x04600000, 4, STRBT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_postindex}}, // STRBT<c> <Rt>,[<Rn>],#+/-<imm12> cond:4|0|1|0|0|U|1|1|0|Rn:4|Rt:4|imm12:12 + {0x0f700010, 0x06600000, 4, STRBT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_postindex}}, // STRBT<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>} cond:4|0|1|1|0|U|1|1|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 + {0x0e500ff0, 0x000000f0, 4, STRD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R_pm_R_W}}, // STRD<c> <Rt1>,<Rt2>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|1|1|Rm:4 + {0x0e5000f0, 0x000000f0, 3, STRD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R_pm_R_W}}, // STRD<c> <Rt1>,<Rt2>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|1|1|Rm:4 + {0x0e5000f0, 0x004000f0, 4, STRD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R_pm_imm8_W}}, // STRD<c> <Rt1>,<Rt2>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|0|Rn:4|Rt:4|imm4H:4|1|1|1|1|imm4L:4 + {0x0ff00ff0, 0x01800f90, 4, STREX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_mem_R}}, // STREX<c> <Rd>,<Rt>,[<Rn>] cond:4|0|0|0|1|1|0|0|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4 + {0x0ff00ff0, 0x01c00f90, 4, STREXB_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_mem_R}}, // STREXB<c> <Rd>,<Rt>,[<Rn>] cond:4|0|0|0|1|1|1|0|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4 + {0x0ff00ff0, 0x01a00f90, 4, STREXD_EQ, 0x1c04, instArgs{arg_R_12, arg_R1_0, arg_R2_0, arg_mem_R}}, // STREXD<c> <Rd>,<Rt1>,<Rt2>,[<Rn>] cond:4|0|0|0|1|1|0|1|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4 + {0x0ff00ff0, 0x01e00f90, 4, STREXH_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_mem_R}}, // STREXH<c> <Rd>,<Rt>,[<Rn>] cond:4|0|0|0|1|1|1|1|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4 + {0x0e500ff0, 0x000000b0, 2, STRH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_W}}, // STRH<c> <Rt>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4 + {0x0e5000f0, 0x004000b0, 2, STRH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_W}}, // STRH<c> <Rt>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|0|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4 + {0x0f7000f0, 0x006000b0, 4, STRHT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_postindex}}, // STRHT<c> <Rt>, [<Rn>] {,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|0|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4 + {0x0f700ff0, 0x002000b0, 4, STRHT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_postindex}}, // STRHT<c> <Rt>, [<Rn>], +/-<Rm> cond:4|0|0|0|0|U|0|1|0|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4 + {0x0f700000, 0x04200000, 4, STRT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_postindex}}, // STRT<c> <Rt>, [<Rn>] {,#+/-<imm12>} cond:4|0|1|0|0|U|0|1|0|Rn:4|Rt:4|imm12:12 + {0x0f700010, 0x06200000, 4, STRT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_postindex}}, // STRT<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>} cond:4|0|1|1|0|U|0|1|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 + {0x0fe00000, 0x02400000, 2, SUB_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // SUB{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|0|1|0|S|Rn:4|Rd:4|imm12:12 + {0x0fe00090, 0x00400010, 4, SUB_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // SUB{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|0|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 + {0x0fe00010, 0x00400000, 2, SUB_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // SUB{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|0|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 + {0x0fef0000, 0x024d0000, 2, SUB_EQ, 0x14011c04, instArgs{arg_R_12, arg_SP, arg_const}}, // SUB{S}<c> <Rd>,SP,#<const> cond:4|0|0|1|0|0|1|0|S|1|1|0|1|Rd:4|imm12:12 + {0x0fef0010, 0x004d0000, 2, SUB_EQ, 0x14011c04, instArgs{arg_R_12, arg_SP, arg_R_shift_imm}}, // SUB{S}<c> <Rd>,SP,<Rm>{,<shift>} cond:4|0|0|0|0|0|1|0|S|1|1|0|1|Rd:4|imm5:5|type:2|0|Rm:4 + {0x0f000000, 0x0f000000, 4, SVC_EQ, 0x1c04, instArgs{arg_imm24}}, // SVC<c> #<imm24> cond:4|1|1|1|1|imm24:24 + {0x0fb00ff0, 0x01000090, 4, SWP_EQ, 0x16011c04, instArgs{arg_R_12, arg_R_0, arg_mem_R}}, // SWP{B}<c> <Rt>,<Rm>,[<Rn>] cond:4|0|0|0|1|0|B|0|0|Rn:4|Rt:4|0|0|0|0|1|0|0|1|Rm:4 + {0x0ff003f0, 0x06800070, 2, SXTAB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_rotate}}, // SXTAB16<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 + {0x0ff003f0, 0x06a00070, 2, SXTAB_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_rotate}}, // SXTAB<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|1|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 + {0x0ff003f0, 0x06b00070, 2, SXTAH_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_rotate}}, // SXTAH<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|1|1|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 + {0x0fff03f0, 0x068f0070, 4, SXTB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_rotate}}, // SXTB16<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|0|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 + {0x0fff03f0, 0x06af0070, 4, SXTB_EQ, 0x1c04, instArgs{arg_R_12, arg_R_rotate}}, // SXTB<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|1|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 + {0x0fff03f0, 0x06bf0070, 4, SXTH_EQ, 0x1c04, instArgs{arg_R_12, arg_R_rotate}}, // SXTH<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|1|1|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 + {0x0ff0f000, 0x03300000, 4, TEQ_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // TEQ<c> <Rn>,#<const> cond:4|0|0|1|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 + {0x0ff00000, 0x03300000, 3, TEQ_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // TEQ<c> <Rn>,#<const> cond:4|0|0|1|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 + {0x0ff0f090, 0x01300010, 4, TEQ_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // TEQ<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 + {0x0ff00090, 0x01300010, 3, TEQ_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // TEQ<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 + {0x0ff0f010, 0x01300000, 4, TEQ_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // TEQ<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 + {0x0ff00010, 0x01300000, 3, TEQ_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // TEQ<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 + {0x0ff0f000, 0x03100000, 4, TST_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // TST<c> <Rn>,#<const> cond:4|0|0|1|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 + {0x0ff00000, 0x03100000, 3, TST_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // TST<c> <Rn>,#<const> cond:4|0|0|1|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 + {0x0ff0f090, 0x01100010, 4, TST_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // TST<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 + {0x0ff00090, 0x01100010, 3, TST_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // TST<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 + {0x0ff0f010, 0x01100000, 4, TST_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // TST<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 + {0x0ff00010, 0x01100000, 3, TST_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // TST<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 + {0x0ff00ff0, 0x06500f10, 4, UADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 + {0x0ff000f0, 0x06500f10, 3, UADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 + {0x0ff00ff0, 0x06500f90, 4, UADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 + {0x0ff000f0, 0x06500f90, 3, UADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 + {0x0ff00ff0, 0x06500f30, 4, UASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 + {0x0ff000f0, 0x06500f30, 3, UASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 + {0x0fe00070, 0x07e00050, 4, UBFX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_imm5, arg_widthm1}}, // UBFX<c> <Rd>,<Rn>,#<lsb>,#<widthm1> cond:4|0|1|1|1|1|1|1|widthm1:5|Rd:4|lsb:5|1|0|1|Rn:4 + {0x0ff00ff0, 0x06700f10, 4, UHADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 + {0x0ff000f0, 0x06700f10, 3, UHADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 + {0x0ff00ff0, 0x06700f90, 4, UHADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 + {0x0ff000f0, 0x06700f90, 3, UHADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 + {0x0ff00ff0, 0x06700f30, 4, UHASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 + {0x0ff000f0, 0x06700f30, 3, UHASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 + {0x0ff00ff0, 0x06700f50, 4, UHSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 + {0x0ff000f0, 0x06700f50, 3, UHSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 + {0x0ff00ff0, 0x06700f70, 4, UHSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 + {0x0ff000f0, 0x06700f70, 3, UHSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 + {0x0ff00ff0, 0x06700ff0, 4, UHSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 + {0x0ff000f0, 0x06700ff0, 3, UHSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 + {0x0ff000f0, 0x00400090, 4, UMAAL_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // UMAAL<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|0|1|0|0|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4 + {0x0fe000f0, 0x00a00090, 4, UMLAL_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // UMLAL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|0|1|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4 + {0x0fe000f0, 0x00800090, 4, UMULL_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // UMULL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|0|0|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4 + {0x0ff00ff0, 0x06600f10, 4, UQADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 + {0x0ff000f0, 0x06600f10, 3, UQADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 + {0x0ff00ff0, 0x06600f90, 4, UQADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 + {0x0ff000f0, 0x06600f90, 3, UQADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 + {0x0ff00ff0, 0x06600f30, 4, UQASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 + {0x0ff000f0, 0x06600f30, 3, UQASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 + {0x0ff00ff0, 0x06600f50, 4, UQSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 + {0x0ff000f0, 0x06600f50, 3, UQSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 + {0x0ff00ff0, 0x06600f70, 4, UQSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 + {0x0ff000f0, 0x06600f70, 3, UQSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 + {0x0ff00ff0, 0x06600ff0, 4, UQSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 + {0x0ff000f0, 0x06600ff0, 3, UQSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 + {0x0ff0f0f0, 0x0780f010, 4, USAD8_EQ, 0x1c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // USAD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|1|1|0|0|0|Rd:4|1|1|1|1|Rm:4|0|0|0|1|Rn:4 + {0x0ff000f0, 0x07800010, 2, USADA8_EQ, 0x1c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // USADA8<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|1|1|1|1|0|0|0|Rd:4|Ra:4|Rm:4|0|0|0|1|Rn:4 + {0x0ff00ff0, 0x06e00f30, 4, USAT16_EQ, 0x1c04, instArgs{arg_R_12, arg_satimm4, arg_R_0}}, // USAT16<c> <Rd>,#<sat_imm4>,<Rn> cond:4|0|1|1|0|1|1|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4 + {0x0ff000f0, 0x06e00f30, 3, USAT16_EQ, 0x1c04, instArgs{arg_R_12, arg_satimm4, arg_R_0}}, // USAT16<c> <Rd>,#<sat_imm4>,<Rn> cond:4|0|1|1|0|1|1|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4 + {0x0fe00030, 0x06e00010, 4, USAT_EQ, 0x1c04, instArgs{arg_R_12, arg_satimm5, arg_R_shift_imm}}, // USAT<c> <Rd>,#<sat_imm5>,<Rn>{,<shift>} cond:4|0|1|1|0|1|1|1|sat_imm:5|Rd:4|imm5:5|sh|0|1|Rn:4 + {0x0ff00ff0, 0x06500f50, 4, USAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // USAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 + {0x0ff000f0, 0x06500f50, 3, USAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // USAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 + {0x0ff00ff0, 0x06500f70, 4, USUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // USUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 + {0x0ff000f0, 0x06500f70, 3, USUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // USUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 + {0x0ff00ff0, 0x06500ff0, 4, USUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // USUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 + {0x0ff000f0, 0x06500ff0, 3, USUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // USUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 + {0x0ff003f0, 0x06c00070, 2, UXTAB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_rotate}}, // UXTAB16<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|0|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 + {0x0ff003f0, 0x06e00070, 2, UXTAB_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_rotate}}, // UXTAB<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|1|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 + {0x0ff003f0, 0x06f00070, 2, UXTAH_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_rotate}}, // UXTAH<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|1|1|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 + {0x0fff03f0, 0x06cf0070, 4, UXTB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_rotate}}, // UXTB16<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|0|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 + {0x0fff03f0, 0x06ef0070, 4, UXTB_EQ, 0x1c04, instArgs{arg_R_12, arg_R_rotate}}, // UXTB<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|1|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 + {0x0fff03f0, 0x06ff0070, 4, UXTH_EQ, 0x1c04, instArgs{arg_R_12, arg_R_rotate}}, // UXTH<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|1|1|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 + {0x0fb00e10, 0x0e000a00, 4, VMLA_EQ_F32, 0x60108011c04, instArgs{arg_Sd_Dd, arg_Sn_Dn, arg_Sm_Dm}}, // V<MLA,MLS><c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|0|0|Vn:4|Vd:4|1|0|1|sz|N|op|M|0|Vm:4 + {0x0fbf0ed0, 0x0eb00ac0, 4, VABS_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sm_Dm}}, // VABS<c>.F<32,64> <Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|0|0|0|Vd:4|1|0|1|sz|1|1|M|0|Vm:4 + {0x0fb00e50, 0x0e300a00, 4, VADD_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sn_Dn, arg_Sm_Dm}}, // VADD<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|1|1|Vn:4|Vd:4|1|0|1|sz|N|0|M|0|Vm:4 + {0x0fbf0e7f, 0x0eb50a40, 4, VCMP_EQ_F32, 0x70108011c04, instArgs{arg_Sd_Dd, arg_fp_0}}, // VCMP{E}<c>.F<32,64> <Sd,Dd>, #0.0 cond:4|1|1|1|0|1|D|1|1|0|1|0|1|Vd:4|1|0|1|sz|E|1|0|0|(0)|(0)|(0)|(0) + {0x0fbf0e70, 0x0eb50a40, 3, VCMP_EQ_F32, 0x70108011c04, instArgs{arg_Sd_Dd, arg_fp_0}}, // VCMP{E}<c>.F<32,64> <Sd,Dd>, #0.0 cond:4|1|1|1|0|1|D|1|1|0|1|0|1|Vd:4|1|0|1|sz|E|1|0|0|(0)|(0)|(0)|(0) + {0x0fbf0e50, 0x0eb40a40, 4, VCMP_EQ_F32, 0x70108011c04, instArgs{arg_Sd_Dd, arg_Sm_Dm}}, // VCMP{E}<c>.F<32,64> <Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|1|0|0|Vd:4|1|0|1|sz|E|1|M|0|Vm:4 + {0x0fbe0e50, 0x0eba0a40, 4, VCVT_EQ_F32_FXS16, 0x801100107011c04, instArgs{arg_Sd_Dd, arg_Sd_Dd, arg_fbits}}, // VCVT<c>.F<32,64>.FX<S,U><16,32> <Sd,Dd>, <Sd,Dd>, #<fbits> cond:4|1|1|1|0|1|D|1|1|1|0|1|U|Vd:4|1|0|1|sz|sx|1|i|0|imm4:4 + {0x0fbe0e50, 0x0ebe0a40, 4, VCVT_EQ_FXS16_F32, 0x1001070108011c04, instArgs{arg_Sd_Dd, arg_Sd_Dd, arg_fbits}}, // VCVT<c>.FX<S,U><16,32>.F<32,64> <Sd,Dd>, <Sd,Dd>, #<fbits> cond:4|1|1|1|0|1|D|1|1|1|1|1|U|Vd:4|1|0|1|sz|sx|1|i|0|imm4:4 + {0x0fbf0ed0, 0x0eb70ac0, 4, VCVT_EQ_F64_F32, 0x8011c04, instArgs{arg_Dd_Sd, arg_Sm_Dm}}, // VCVT<c>.<F64.F32,F32.F64> <Dd,Sd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|1|1|1|Vd:4|1|0|1|sz|1|1|M|0|Vm:4 + {0x0fbe0f50, 0x0eb20a40, 4, VCVTB_EQ_F32_F16, 0x70110011c04, instArgs{arg_Sd, arg_Sm}}, // VCVT<B,T><c>.<F32.F16,F16.F32> <Sd>, <Sm> cond:4|1|1|1|0|1|D|1|1|0|0|1|op|Vd:4|1|0|1|0|T|1|M|0|Vm:4 + {0x0fbf0e50, 0x0eb80a40, 4, VCVT_EQ_F32_U32, 0x80107011c04, instArgs{arg_Sd_Dd, arg_Sm}}, // VCVT<c>.F<32,64>.<U,S>32 <Sd,Dd>, <Sm> cond:4|1|1|1|0|1|D|1|1|1|0|0|0|Vd:4|1|0|1|sz|op|1|M|0|Vm:4 + {0x0fbe0e50, 0x0ebc0a40, 4, VCVTR_EQ_U32_F32, 0x701100108011c04, instArgs{arg_Sd, arg_Sm_Dm}}, // VCVT<R,><c>.<U,S>32.F<32,64> <Sd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|1|1|0|signed|Vd:4|1|0|1|sz|op|1|M|0|Vm:4 + {0x0fb00e50, 0x0e800a00, 4, VDIV_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sn_Dn, arg_Sm_Dm}}, // VDIV<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|1|D|0|0|Vn:4|Vd:4|1|0|1|sz|N|0|M|0|Vm:4 + {0x0f300e00, 0x0d100a00, 4, VLDR_EQ, 0x1c04, instArgs{arg_Sd_Dd, arg_mem_R_pm_imm8at0_offset}}, // VLDR<c> <Sd,Dd>, [<Rn>{,#+/-<imm8>}] cond:4|1|1|0|1|U|D|0|1|Rn:4|Vd:4|1|0|1|sz|imm8:8 + {0x0ff00f7f, 0x0e000a10, 4, VMOV_EQ, 0x1c04, instArgs{arg_Sn, arg_R_12}}, // VMOV<c> <Sn>, <Rt> cond:4|1|1|1|0|0|0|0|0|Vn:4|Rt:4|1|0|1|0|N|0|0|1|0|0|0|0 + {0x0ff00f7f, 0x0e100a10, 4, VMOV_EQ, 0x1c04, instArgs{arg_R_12, arg_Sn}}, // VMOV<c> <Rt>, <Sn> cond:4|1|1|1|0|0|0|0|1|Vn:4|Rt:4|1|0|1|0|N|0|0|1|0|0|0|0 + {0x0fd00f7f, 0x0e100b10, 4, VMOV_EQ_32, 0x1c04, instArgs{arg_R_12, arg_Dn_half}}, // VMOV<c>.32 <Rt>, <Dn[x]> cond:4|1|1|1|0|0|0|opc1|1|Vn:4|Rt:4|1|0|1|1|N|0|0|1|0|0|0|0 + {0x0fd00f7f, 0x0e000b10, 4, VMOV_EQ_32, 0x1c04, instArgs{arg_Dn_half, arg_R_12}}, // VMOV<c>.32 <Dd[x]>, <Rt> cond:4|1|1|1|0|0|0|opc1|0|Vd:4|Rt:4|1|0|1|1|D|0|0|1|0|0|0|0 + {0x0fb00ef0, 0x0eb00a00, 4, VMOV_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_imm_vfp}}, // VMOV<c>.F<32,64> <Sd,Dd>, #<imm_vfp> cond:4|1|1|1|0|1|D|1|1|imm4H:4|Vd:4|1|0|1|sz|0|0|0|0|imm4L:4 + {0x0fbf0ed0, 0x0eb00a40, 4, VMOV_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sm_Dm}}, // VMOV<c>.F<32,64> <Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|0|0|0|Vd:4|1|0|1|sz|0|1|M|0|Vm:4 + {0x0fff0fff, 0x0ef10a10, 4, VMRS_EQ, 0x1c04, instArgs{arg_R_12_nzcv, arg_FPSCR}}, // VMRS<c> <Rt_nzcv>, FPSCR cond:4|1|1|1|0|1|1|1|1|0|0|0|1|Rt:4|1|0|1|0|0|0|0|1|0|0|0|0 + {0x0fff0fff, 0x0ee10a10, 4, VMSR_EQ, 0x1c04, instArgs{arg_FPSCR, arg_R_12}}, // VMSR<c> FPSCR, <Rt> cond:4|1|1|1|0|1|1|1|0|0|0|0|1|Rt:4|1|0|1|0|0|0|0|1|0|0|0|0 + {0x0fb00e50, 0x0e200a00, 4, VMUL_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sn_Dn, arg_Sm_Dm}}, // VMUL<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|1|0|Vn:4|Vd:4|1|0|1|sz|N|0|M|0|Vm:4 + {0x0fbf0ed0, 0x0eb10a40, 4, VNEG_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sm_Dm}}, // VNEG<c>.F<32,64> <Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|0|0|1|Vd:4|1|0|1|sz|0|1|M|0|Vm:4 + {0x0fb00e10, 0x0e100a00, 4, VNMLS_EQ_F32, 0x60108011c04, instArgs{arg_Sd_Dd, arg_Sn_Dn, arg_Sm_Dm}}, // VN<MLS,MLA><c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|0|1|Vn:4|Vd:4|1|0|1|sz|N|op|M|0|Vm:4 + {0x0fb00e50, 0x0e200a40, 4, VNMUL_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sn_Dn, arg_Sm_Dm}}, // VNMUL<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|1|0|Vn:4|Vd:4|1|0|1|sz|N|1|M|0|Vm:4 + {0x0fbf0ed0, 0x0eb10ac0, 4, VSQRT_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sm_Dm}}, // VSQRT<c>.F<32,64> <Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|0|0|1|Vd:4|1|0|1|sz|1|1|M|0|Vm:4 + {0x0f300e00, 0x0d000a00, 4, VSTR_EQ, 0x1c04, instArgs{arg_Sd_Dd, arg_mem_R_pm_imm8at0_offset}}, // VSTR<c> <Sd,Dd>, [<Rn>{,#+/-<imm8>}] cond:4|1|1|0|1|U|D|0|0|Rn:4|Vd:4|1|0|1|sz|imm8:8 + {0x0fb00e50, 0x0e300a40, 4, VSUB_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sn_Dn, arg_Sm_Dm}}, // VSUB<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|1|1|Vn:4|Vd:4|1|0|1|sz|N|1|M|0|Vm:4 + {0x0fffffff, 0x0320f002, 4, WFE_EQ, 0x1c04, instArgs{}}, // WFE<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|0 + {0x0fff00ff, 0x0320f002, 3, WFE_EQ, 0x1c04, instArgs{}}, // WFE<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|0 + {0x0fffffff, 0x0320f003, 4, WFI_EQ, 0x1c04, instArgs{}}, // WFI<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|1 + {0x0fff00ff, 0x0320f003, 3, WFI_EQ, 0x1c04, instArgs{}}, // WFI<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|1 + {0x0fffffff, 0x0320f001, 4, YIELD_EQ, 0x1c04, instArgs{}}, // YIELD<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|1 + {0x0fff00ff, 0x0320f001, 3, YIELD_EQ, 0x1c04, instArgs{}}, // YIELD<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|1 + {0xffffffff, 0xf7fabcfd, 4, UNDEF, 0x0, instArgs{}}, // UNDEF 1|1|1|1|0|1|1|1|1|1|1|1|1|0|1|0|1|0|1|1|1|1|0|0|1|1|1|1|1|1|0|1 +} diff --git a/vendor/golang.org/x/arch/ppc64/ppc64asm/LICENSE b/vendor/golang.org/x/arch/ppc64/ppc64asm/LICENSE new file mode 100644 index 00000000..d29b3726 --- /dev/null +++ b/vendor/golang.org/x/arch/ppc64/ppc64asm/LICENSE @@ -0,0 +1,27 @@ +Copyright (c) 2015 The Go Authors. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met: + + * Redistributions of source code must retain the above copyright +notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above +copyright notice, this list of conditions and the following disclaimer +in the documentation and/or other materials provided with the +distribution. + * Neither the name of Google Inc. nor the names of its +contributors may be used to endorse or promote products derived from +this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/vendor/golang.org/x/arch/ppc64/ppc64asm/decode.go b/vendor/golang.org/x/arch/ppc64/ppc64asm/decode.go new file mode 100644 index 00000000..e1518d52 --- /dev/null +++ b/vendor/golang.org/x/arch/ppc64/ppc64asm/decode.go @@ -0,0 +1,179 @@ +// Copyright 2014 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ppc64asm + +import ( + "encoding/binary" + "fmt" + "log" +) + +const debugDecode = false + +// instFormat is a decoding rule for one specific instruction form. +// a uint32 instruction ins matches the rule if ins&Mask == Value +// DontCare bits should be zero, but the machine might not reject +// ones in those bits, they are mainly reserved for future expansion +// of the instruction set. +// The Args are stored in the same order as the instruction manual. +type instFormat struct { + Op Op + Mask uint32 + Value uint32 + DontCare uint32 + Args [5]*argField +} + +// argField indicate how to decode an argument to an instruction. +// First parse the value from the BitFields, shift it left by Shift +// bits to get the actual numerical value. +type argField struct { + Type ArgType + Shift uint8 + BitFields +} + +// Parse parses the Arg out from the given binary instruction i. +func (a argField) Parse(i uint32) Arg { + switch a.Type { + default: + return nil + case TypeUnknown: + return nil + case TypeReg: + return R0 + Reg(a.BitFields.Parse(i)) + case TypeCondRegBit: + return Cond0LT + CondReg(a.BitFields.Parse(i)) + case TypeCondRegField: + return CR0 + CondReg(a.BitFields.Parse(i)) + case TypeFPReg: + return F0 + Reg(a.BitFields.Parse(i)) + case TypeVecReg: + return V0 + Reg(a.BitFields.Parse(i)) + case TypeVecSReg: + return VS0 + Reg(a.BitFields.Parse(i)) + case TypeSpReg: + return SpReg(a.BitFields.Parse(i)) + case TypeImmSigned: + return Imm(a.BitFields.ParseSigned(i) << a.Shift) + case TypeImmUnsigned: + return Imm(a.BitFields.Parse(i) << a.Shift) + case TypePCRel: + return PCRel(a.BitFields.ParseSigned(i) << a.Shift) + case TypeLabel: + return Label(a.BitFields.ParseSigned(i) << a.Shift) + case TypeOffset: + return Offset(a.BitFields.ParseSigned(i) << a.Shift) + } +} + +type ArgType int8 + +const ( + TypeUnknown ArgType = iota + TypePCRel // PC-relative address + TypeLabel // absolute address + TypeReg // integer register + TypeCondRegBit // conditional register bit (0-31) + TypeCondRegField // conditional register field (0-7) + TypeFPReg // floating point register + TypeVecReg // vector register + TypeVecSReg // VSX register + TypeSpReg // special register (depends on Op) + TypeImmSigned // signed immediate + TypeImmUnsigned // unsigned immediate/flag/mask, this is the catch-all type + TypeOffset // signed offset in load/store + TypeLast // must be the last one +) + +func (t ArgType) String() string { + switch t { + default: + return fmt.Sprintf("ArgType(%d)", int(t)) + case TypeUnknown: + return "Unknown" + case TypeReg: + return "Reg" + case TypeCondRegBit: + return "CondRegBit" + case TypeCondRegField: + return "CondRegField" + case TypeFPReg: + return "FPReg" + case TypeVecReg: + return "VecReg" + case TypeVecSReg: + return "VecSReg" + case TypeSpReg: + return "SpReg" + case TypeImmSigned: + return "ImmSigned" + case TypeImmUnsigned: + return "ImmUnsigned" + case TypePCRel: + return "PCRel" + case TypeLabel: + return "Label" + case TypeOffset: + return "Offset" + } +} + +func (t ArgType) GoString() string { + s := t.String() + if t > 0 && t < TypeLast { + return "Type" + s + } + return s +} + +var ( + // Errors + errShort = fmt.Errorf("truncated instruction") + errUnknown = fmt.Errorf("unknown instruction") +) + +var decoderCover []bool + +// Decode decodes the leading bytes in src as a single instruction using +// byte order ord. +func Decode(src []byte, ord binary.ByteOrder) (inst Inst, err error) { + if len(src) < 4 { + return inst, errShort + } + if decoderCover == nil { + decoderCover = make([]bool, len(instFormats)) + } + inst.Len = 4 // only 4-byte instructions are supported + ui := ord.Uint32(src[:inst.Len]) + inst.Enc = ui + for i, iform := range instFormats { + if ui&iform.Mask != iform.Value { + continue + } + if ui&iform.DontCare != 0 { + if debugDecode { + log.Printf("Decode(%#x): unused bit is 1 for Op %s", ui, iform.Op) + } + // to match GNU objdump (libopcodes), we ignore don't care bits + } + for i, argfield := range iform.Args { + if argfield == nil { + break + } + inst.Args[i] = argfield.Parse(ui) + } + inst.Op = iform.Op + if debugDecode { + log.Printf("%#x: search entry %d", ui, i) + continue + } + break + } + if inst.Op == 0 { + return inst, errUnknown + } + return inst, nil +} diff --git a/vendor/golang.org/x/arch/ppc64/ppc64asm/doc.go b/vendor/golang.org/x/arch/ppc64/ppc64asm/doc.go new file mode 100644 index 00000000..5f4ef7d1 --- /dev/null +++ b/vendor/golang.org/x/arch/ppc64/ppc64asm/doc.go @@ -0,0 +1,6 @@ +// Copyright 2014 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// Package ppc64asm implements decoding of 64-bit PowerPC machine code. +package ppc64asm diff --git a/vendor/golang.org/x/arch/ppc64/ppc64asm/field.go b/vendor/golang.org/x/arch/ppc64/ppc64asm/field.go new file mode 100644 index 00000000..26a4fdf1 --- /dev/null +++ b/vendor/golang.org/x/arch/ppc64/ppc64asm/field.go @@ -0,0 +1,84 @@ +// Copyright 2014 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ppc64asm + +import ( + "fmt" + "strings" +) + +// A BitField is a bit-field in a 32-bit word. +// Bits are counted from 0 from the MSB to 31 as the LSB. +type BitField struct { + Offs uint8 // the offset of the left-most bit. + Bits uint8 // length in bits. +} + +func (b BitField) String() string { + if b.Bits > 1 { + return fmt.Sprintf("[%d:%d]", b.Offs, int(b.Offs+b.Bits)-1) + } else if b.Bits == 1 { + return fmt.Sprintf("[%d]", b.Offs) + } else { + return fmt.Sprintf("[%d, len=0]", b.Offs) + } +} + +// Parse extracts the bitfield b from i, and return it as an unsigned integer. +// Parse will panic if b is invalid. +func (b BitField) Parse(i uint32) uint32 { + if b.Bits > 32 || b.Bits == 0 || b.Offs > 31 || b.Offs+b.Bits > 32 { + panic(fmt.Sprintf("invalid bitfiled %v", b)) + } + return (i >> (32 - b.Offs - b.Bits)) & ((1 << b.Bits) - 1) +} + +// ParseSigned extracts the bitfield b from i, and return it as a signed integer. +// ParseSigned will panic if b is invalid. +func (b BitField) ParseSigned(i uint32) int32 { + u := int32(b.Parse(i)) + return u << (32 - b.Bits) >> (32 - b.Bits) +} + +// BitFields is a series of BitFields representing a single number. +type BitFields []BitField + +func (bs BitFields) String() string { + ss := make([]string, len(bs)) + for i, bf := range bs { + ss[i] = bf.String() + } + return fmt.Sprintf("<%s>", strings.Join(ss, "|")) +} + +func (bs *BitFields) Append(b BitField) { + *bs = append(*bs, b) +} + +// parse extracts the bitfields from i, concatenate them and return the result +// as an unsigned integer and the total length of all the bitfields. +// parse will panic if any bitfield in b is invalid, but it doesn't check if +// the sequence of bitfields is reasonable. +func (bs BitFields) parse(i uint32) (u uint32, Bits uint8) { + for _, b := range bs { + u = (u << b.Bits) | b.Parse(i) + Bits += b.Bits + } + return u, Bits +} + +// Parse extracts the bitfields from i, concatenate them and return the result +// as an unsigned integer. Parse will panic if any bitfield in b is invalid. +func (bs BitFields) Parse(i uint32) uint32 { + u, _ := bs.parse(i) + return u +} + +// Parse extracts the bitfields from i, concatenate them and return the result +// as a signed integer. Parse will panic if any bitfield in b is invalid. +func (bs BitFields) ParseSigned(i uint32) int32 { + u, l := bs.parse(i) + return int32(u) << (32 - l) >> (32 - l) +} diff --git a/vendor/golang.org/x/arch/ppc64/ppc64asm/gnu.go b/vendor/golang.org/x/arch/ppc64/ppc64asm/gnu.go new file mode 100644 index 00000000..63be379a --- /dev/null +++ b/vendor/golang.org/x/arch/ppc64/ppc64asm/gnu.go @@ -0,0 +1,125 @@ +// Copyright 2014 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ppc64asm + +import ( + "bytes" + "fmt" + "strings" +) + +// GNUSyntax returns the GNU assembler syntax for the instruction, as defined by GNU binutils. +// This form typically matches the syntax defined in the Power ISA Reference Manual. +func GNUSyntax(inst Inst) string { + var buf bytes.Buffer + if inst.Op == 0 { + return "error: unkown instruction" + } + buf.WriteString(inst.Op.String()) + sep := " " + for i, arg := range inst.Args[:] { + if arg == nil { + break + } + text := gnuArg(&inst, i, arg) + if text == "" { + continue + } + buf.WriteString(sep) + sep = "," + buf.WriteString(text) + } + return buf.String() +} + +// gnuArg formats arg (which is the argIndex's arg in inst) according to GNU rules. +// NOTE: because GNUSyntax is the only caller of this func, and it receives a copy +// of inst, it's ok to modify inst.Args here. +func gnuArg(inst *Inst, argIndex int, arg Arg) string { + // special cases for load/store instructions + if _, ok := arg.(Offset); ok { + if argIndex+1 == len(inst.Args) || inst.Args[argIndex+1] == nil { + panic(fmt.Errorf("wrong table: offset not followed by register")) + } + } + switch arg := arg.(type) { + case Reg: + if isLoadStoreOp(inst.Op) && argIndex == 1 && arg == R0 { + return "0" + } + return arg.String() + case CondReg: + if arg == CR0 && strings.HasPrefix(inst.Op.String(), "cmp") { + return "" // don't show cr0 for cmp instructions + } else if arg >= CR0 { + return fmt.Sprintf("cr%d", int(arg-CR0)) + } + bit := [4]string{"lt", "gt", "eq", "so"}[(arg-Cond0LT)%4] + if arg <= Cond0SO { + return bit + } + return fmt.Sprintf("4*cr%d+%s", int(arg-Cond0LT)/4, bit) + case Imm: + return fmt.Sprintf("%d", arg) + case SpReg: + return fmt.Sprintf("%d", int(arg)) + case PCRel: + return fmt.Sprintf(".%+#x", int(arg)) + case Label: + return fmt.Sprintf("%#x", uint32(arg)) + case Offset: + reg := inst.Args[argIndex+1].(Reg) + removeArg(inst, argIndex+1) + if reg == R0 { + return fmt.Sprintf("%d(0)", int(arg)) + } + return fmt.Sprintf("%d(r%d)", int(arg), reg-R0) + } + return fmt.Sprintf("???(%v)", arg) +} + +// removeArg removes the arg in inst.Args[index]. +func removeArg(inst *Inst, index int) { + for i := index; i < len(inst.Args); i++ { + if i+1 < len(inst.Args) { + inst.Args[i] = inst.Args[i+1] + } else { + inst.Args[i] = nil + } + } +} + +// isLoadStoreOp returns true if op is a load or store instruction +func isLoadStoreOp(op Op) bool { + switch op { + case LBZ, LBZU, LBZX, LBZUX: + return true + case LHZ, LHZU, LHZX, LHZUX: + return true + case LHA, LHAU, LHAX, LHAUX: + return true + case LWZ, LWZU, LWZX, LWZUX: + return true + case LWA, LWAX, LWAUX: + return true + case LD, LDU, LDX, LDUX: + return true + case LQ: + return true + case STB, STBU, STBX, STBUX: + return true + case STH, STHU, STHX, STHUX: + return true + case STW, STWU, STWX, STWUX: + return true + case STD, STDU, STDX, STDUX: + return true + case STQ: + return true + case LHBRX, LWBRX, STHBRX, STWBRX: + return true + } + return false +} diff --git a/vendor/golang.org/x/arch/ppc64/ppc64asm/inst.go b/vendor/golang.org/x/arch/ppc64/ppc64asm/inst.go new file mode 100644 index 00000000..bd86b923 --- /dev/null +++ b/vendor/golang.org/x/arch/ppc64/ppc64asm/inst.go @@ -0,0 +1,344 @@ +// Copyright 2014 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ppc64asm + +import ( + "bytes" + "fmt" +) + +type Inst struct { + Op Op // Opcode mnemonic + Enc uint32 // Raw encoding bits + Len int // Length of encoding in bytes. + Args Args // Instruction arguments, in Power ISA manual order. +} + +func (i Inst) String() string { + var buf bytes.Buffer + buf.WriteString(i.Op.String()) + for j, arg := range i.Args { + if arg == nil { + break + } + if j == 0 { + buf.WriteString(" ") + } else { + buf.WriteString(", ") + } + buf.WriteString(arg.String()) + } + return buf.String() +} + +// An Op is an instruction operation. +type Op uint16 + +func (o Op) String() string { + if int(o) >= len(opstr) || opstr[o] == "" { + return fmt.Sprintf("Op(%d)", int(o)) + } + return opstr[o] +} + +// An Arg is a single instruction argument, one of these types: Reg, CondReg, SpReg, Imm, PCRel, Label, or Offset. +type Arg interface { + IsArg() + String() string +} + +// An Args holds the instruction arguments. +// If an instruction has fewer than 4 arguments, +// the final elements in the array are nil. +type Args [5]Arg + +// A Reg is a single register. The zero value means R0, not the absence of a register. +// It also includes special registers. +type Reg uint16 + +const ( + _ Reg = iota + R0 + R1 + R2 + R3 + R4 + R5 + R6 + R7 + R8 + R9 + R10 + R11 + R12 + R13 + R14 + R15 + R16 + R17 + R18 + R19 + R20 + R21 + R22 + R23 + R24 + R25 + R26 + R27 + R28 + R29 + R30 + R31 + F0 + F1 + F2 + F3 + F4 + F5 + F6 + F7 + F8 + F9 + F10 + F11 + F12 + F13 + F14 + F15 + F16 + F17 + F18 + F19 + F20 + F21 + F22 + F23 + F24 + F25 + F26 + F27 + F28 + F29 + F30 + F31 + V0 // VSX extension, F0 is V0[0:63]. + V1 + V2 + V3 + V4 + V5 + V6 + V7 + V8 + V9 + V10 + V11 + V12 + V13 + V14 + V15 + V16 + V17 + V18 + V19 + V20 + V21 + V22 + V23 + V24 + V25 + V26 + V27 + V28 + V29 + V30 + V31 + VS0 + VS1 + VS2 + VS3 + VS4 + VS5 + VS6 + VS7 + VS8 + VS9 + VS10 + VS11 + VS12 + VS13 + VS14 + VS15 + VS16 + VS17 + VS18 + VS19 + VS20 + VS21 + VS22 + VS23 + VS24 + VS25 + VS26 + VS27 + VS28 + VS29 + VS30 + VS31 + VS32 + VS33 + VS34 + VS35 + VS36 + VS37 + VS38 + VS39 + VS40 + VS41 + VS42 + VS43 + VS44 + VS45 + VS46 + VS47 + VS48 + VS49 + VS50 + VS51 + VS52 + VS53 + VS54 + VS55 + VS56 + VS57 + VS58 + VS59 + VS60 + VS61 + VS62 + VS63 +) + +func (Reg) IsArg() {} +func (r Reg) String() string { + switch { + case R0 <= r && r <= R31: + return fmt.Sprintf("r%d", int(r-R0)) + case F0 <= r && r <= F31: + return fmt.Sprintf("f%d", int(r-F0)) + case V0 <= r && r <= V31: + return fmt.Sprintf("v%d", int(r-V0)) + case VS0 <= r && r <= VS63: + return fmt.Sprintf("vs%d", int(r-VS0)) + default: + return fmt.Sprintf("Reg(%d)", int(r)) + } +} + +// CondReg is a bit or field in the conditon register. +type CondReg int8 + +const ( + _ CondReg = iota + // Condition Regster bits + Cond0LT + Cond0GT + Cond0EQ + Cond0SO + Cond1LT + Cond1GT + Cond1EQ + Cond1SO + Cond2LT + Cond2GT + Cond2EQ + Cond2SO + Cond3LT + Cond3GT + Cond3EQ + Cond3SO + Cond4LT + Cond4GT + Cond4EQ + Cond4SO + Cond5LT + Cond5GT + Cond5EQ + Cond5SO + Cond6LT + Cond6GT + Cond6EQ + Cond6SO + Cond7LT + Cond7GT + Cond7EQ + Cond7SO + // Condition Register Fields + CR0 + CR1 + CR2 + CR3 + CR4 + CR5 + CR6 + CR7 +) + +func (CondReg) IsArg() {} +func (c CondReg) String() string { + switch { + default: + return fmt.Sprintf("CondReg(%d)", int(c)) + case c >= CR0: + return fmt.Sprintf("CR%d", int(c-CR0)) + case c >= Cond0LT && c < CR0: + return fmt.Sprintf("Cond%d%s", int((c-Cond0LT)/4), [4]string{"LT", "GT", "EQ", "SO"}[(c-Cond0LT)%4]) + } +} + +// SpReg is a special register, its meaning depends on Op. +type SpReg uint16 + +const ( + SpRegZero SpReg = 0 +) + +func (SpReg) IsArg() {} +func (s SpReg) String() string { + return fmt.Sprintf("SpReg(%d)", int(s)) +} + +// PCRel is a PC-relative offset, used only in branch instructions. +type PCRel int32 + +func (PCRel) IsArg() {} +func (r PCRel) String() string { + return fmt.Sprintf("PC%+#x", int32(r)) +} + +// A Label is a code (text) address, used only in absolute branch instructions. +type Label uint32 + +func (Label) IsArg() {} +func (l Label) String() string { + return fmt.Sprintf("%#x", uint32(l)) +} + +// Imm represents an immediate number. +type Imm int32 + +func (Imm) IsArg() {} +func (i Imm) String() string { + return fmt.Sprintf("%d", int32(i)) +} + +// Offset represents a memory offset immediate. +type Offset int32 + +func (Offset) IsArg() {} +func (o Offset) String() string { + return fmt.Sprintf("%+d", int32(o)) +} diff --git a/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go b/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go new file mode 100644 index 00000000..57a761e3 --- /dev/null +++ b/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go @@ -0,0 +1,172 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ppc64asm + +import ( + "fmt" + "strings" +) + +// GoSyntax returns the Go assembler syntax for the instruction. +// The pc is the program counter of the first instruction, used for expanding +// PC-relative addresses into absolute ones. +// The symname function queries the symbol table for the program +// being disassembled. It returns the name and base address of the symbol +// containing the target, if any; otherwise it returns "", 0. +func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64)) string { + if symname == nil { + symname = func(uint64) (string, uint64) { return "", 0 } + } + if inst.Op == 0 { + return "?" + } + var args []string + for i, a := range inst.Args[:] { + if a == nil { + break + } + if s := plan9Arg(&inst, i, pc, a, symname); s != "" { + args = append(args, s) + } + } + var op string + op = plan9OpMap[inst.Op] + if op == "" { + op = strings.ToUpper(inst.Op.String()) + } + // laid out the instruction + switch inst.Op { + default: // dst, sA, sB, ... + if len(args) == 0 { + return op + } else if len(args) == 1 { + return fmt.Sprintf("%s %s", op, args[0]) + } + args = append(args, args[0]) + return op + " " + strings.Join(args[1:], ", ") + // store instructions always have the memory operand at the end, no need to reorder + case STB, STBU, STBX, STBUX, + STH, STHU, STHX, STHUX, + STW, STWU, STWX, STWUX, + STD, STDU, STDX, STDUX, + STQ, + STHBRX, STWBRX: + return op + " " + strings.Join(args, ", ") + // branch instructions needs additional handling + case BCLR: + if int(inst.Args[0].(Imm))&20 == 20 { // unconditional + return "RET" + } + return op + " " + strings.Join(args, ", ") + case BC: + if int(inst.Args[0].(Imm))&0x1c == 12 { // jump on cond bit set + return fmt.Sprintf("B%s %s", args[1], args[2]) + } else if int(inst.Args[0].(Imm))&0x1c == 4 && revCondMap[args[1]] != "" { // jump on cond bit not set + return fmt.Sprintf("B%s %s", revCondMap[args[1]], args[2]) + } + return op + " " + strings.Join(args, ", ") + case BCCTR: + if int(inst.Args[0].(Imm))&20 == 20 { // unconditional + return "BR (CTR)" + } + return op + " " + strings.Join(args, ", ") + case BCCTRL: + if int(inst.Args[0].(Imm))&20 == 20 { // unconditional + return "BL (CTR)" + } + return op + " " + strings.Join(args, ", ") + case BCA, BCL, BCLA, BCLRL, BCTAR, BCTARL: + return op + " " + strings.Join(args, ", ") + } +} + +// plan9Arg formats arg (which is the argIndex's arg in inst) according to Plan 9 rules. +// NOTE: because Plan9Syntax is the only caller of this func, and it receives a copy +// of inst, it's ok to modify inst.Args here. +func plan9Arg(inst *Inst, argIndex int, pc uint64, arg Arg, symname func(uint64) (string, uint64)) string { + // special cases for load/store instructions + if _, ok := arg.(Offset); ok { + if argIndex+1 == len(inst.Args) || inst.Args[argIndex+1] == nil { + panic(fmt.Errorf("wrong table: offset not followed by register")) + } + } + switch arg := arg.(type) { + case Reg: + if isLoadStoreOp(inst.Op) && argIndex == 1 && arg == R0 { + return "0" + } + if arg == R30 { + return "g" + } + return strings.ToUpper(arg.String()) + case CondReg: + if arg == CR0 && strings.HasPrefix(inst.Op.String(), "cmp") { + return "" // don't show cr0 for cmp instructions + } else if arg >= CR0 { + return fmt.Sprintf("CR%d", int(arg-CR0)) + } + bit := [4]string{"LT", "GT", "EQ", "SO"}[(arg-Cond0LT)%4] + if arg <= Cond0SO { + return bit + } + return fmt.Sprintf("4*CR%d+%s", int(arg-Cond0LT)/4, bit) + case Imm: + return fmt.Sprintf("$%d", arg) + case SpReg: + switch arg { + case 8: + return "LR" + case 9: + return "CTR" + } + return fmt.Sprintf("SPR(%d)", int(arg)) + case PCRel: + addr := pc + uint64(int64(arg)) + if s, base := symname(addr); s != "" && base == addr { + return fmt.Sprintf("%s(SB)", s) + } + return fmt.Sprintf("%#x", addr) + case Label: + return fmt.Sprintf("%#x", int(arg)) + case Offset: + reg := inst.Args[argIndex+1].(Reg) + removeArg(inst, argIndex+1) + if reg == R0 { + return fmt.Sprintf("%d(0)", int(arg)) + } + return fmt.Sprintf("%d(R%d)", int(arg), reg-R0) + } + return fmt.Sprintf("???(%v)", arg) +} + +// revCondMap maps a conditional register bit to its inverse, if possible. +var revCondMap = map[string]string{ + "LT": "GE", "GT": "LE", "EQ": "NE", +} + +// plan9OpMap maps an Op to its Plan 9 mnemonics, if different than its GNU mnemonics. +var plan9OpMap = map[Op]string{ + LWARX: "LWAR", STWCX_: "STWCCC", + LDARX: "LDAR", STDCX_: "STDCCC", + LHARX: "LHAR", STHCX_: "STHCCC", + LBARX: "LBAR", STBCX_: "STBCCC", + ADDI: "ADD", + ADD_: "ADDCC", + LBZ: "MOVBZ", STB: "MOVB", + LBZU: "MOVBZU", STBU: "MOVBU", // TODO(minux): indexed forms are not handled + LHZ: "MOVHZ", LHA: "MOVH", STH: "MOVH", + LHZU: "MOVHZU", STHU: "MOVHU", + LI: "MOVD", + LIS: "ADDIS", + LWZ: "MOVWZ", LWA: "MOVW", STW: "MOVW", + LWZU: "MOVWZU", STWU: "MOVWU", + LD: "MOVD", STD: "MOVD", + LDU: "MOVDU", STDU: "MOVDU", + MTSPR: "MOVD", MFSPR: "MOVD", // the width is ambiguous for SPRs + B: "BR", + BL: "CALL", + CMPLD: "CMPU", CMPLW: "CMPWU", + CMPD: "CMP", CMPW: "CMPW", +} diff --git a/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go b/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go new file mode 100644 index 00000000..24c745c8 --- /dev/null +++ b/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go @@ -0,0 +1,5421 @@ +// DO NOT EDIT +// generated by: ppc64map -fmt=decoder ../pp64.csv + +package ppc64asm + +const ( + _ Op = iota + CNTLZW + CNTLZW_ + B + BA + BL + BLA + BC + BCA + BCL + BCLA + BCLR + BCLRL + BCCTR + BCCTRL + BCTAR + BCTARL + CRAND + CROR + CRNAND + CRXOR + CRNOR + CRANDC + MCRF + CREQV + CRORC + SC + CLRBHRB + MFBHRBE + LBZ + LBZU + LBZX + LBZUX + LHZ + LHZU + LHZX + LHZUX + LHA + LHAU + LHAX + LHAUX + LWZ + LWZU + LWZX + LWZUX + LWA + LWAX + LWAUX + LD + LDU + LDX + LDUX + STB + STBU + STBX + STBUX + STH + STHU + STHX + STHUX + STW + STWU + STWX + STWUX + STD + STDU + STDX + STDUX + LQ + STQ + LHBRX + LWBRX + STHBRX + STWBRX + LDBRX + STDBRX + LMW + STMW + LSWI + LSWX + STSWI + STSWX + LI + ADDI + LIS + ADDIS + ADD + ADD_ + ADDO + ADDO_ + ADDIC + SUBF + SUBF_ + SUBFO + SUBFO_ + ADDIC_ + SUBFIC + ADDC + ADDC_ + ADDCO + ADDCO_ + SUBFC + SUBFC_ + SUBFCO + SUBFCO_ + ADDE + ADDE_ + ADDEO + ADDEO_ + ADDME + ADDME_ + ADDMEO + ADDMEO_ + SUBFE + SUBFE_ + SUBFEO + SUBFEO_ + SUBFME + SUBFME_ + SUBFMEO + SUBFMEO_ + ADDZE + ADDZE_ + ADDZEO + ADDZEO_ + SUBFZE + SUBFZE_ + SUBFZEO + SUBFZEO_ + NEG + NEG_ + NEGO + NEGO_ + MULLI + MULLW + MULLW_ + MULLWO + MULLWO_ + MULHW + MULHW_ + MULHWU + MULHWU_ + DIVW + DIVW_ + DIVWO + DIVWO_ + DIVWU + DIVWU_ + DIVWUO + DIVWUO_ + DIVWE + DIVWE_ + DIVWEO + DIVWEO_ + DIVWEU + DIVWEU_ + DIVWEUO + DIVWEUO_ + MULLD + MULLD_ + MULLDO + MULLDO_ + MULHDU + MULHDU_ + MULHD + MULHD_ + DIVD + DIVD_ + DIVDO + DIVDO_ + DIVDU + DIVDU_ + DIVDUO + DIVDUO_ + DIVDE + DIVDE_ + DIVDEO + DIVDEO_ + DIVDEU + DIVDEU_ + DIVDEUO + DIVDEUO_ + CMPWI + CMPDI + CMPW + CMPD + CMPLWI + CMPLDI + CMPLW + CMPLD + TWI + TW + TDI + ISEL + TD + ANDI_ + ANDIS_ + ORI + ORIS + XORI + XORIS + AND + AND_ + XOR + XOR_ + NAND + NAND_ + OR + OR_ + NOR + NOR_ + ANDC + ANDC_ + EXTSB + EXTSB_ + EQV + EQV_ + ORC + ORC_ + EXTSH + EXTSH_ + CMPB + POPCNTB + POPCNTW + PRTYD + PRTYW + EXTSW + EXTSW_ + CNTLZD + CNTLZD_ + POPCNTD + BPERMD + RLWINM + RLWINM_ + RLWNM + RLWNM_ + RLWIMI + RLWIMI_ + RLDICL + RLDICL_ + RLDICR + RLDICR_ + RLDIC + RLDIC_ + RLDCL + RLDCL_ + RLDCR + RLDCR_ + RLDIMI + RLDIMI_ + SLW + SLW_ + SRW + SRW_ + SRAWI + SRAWI_ + SRAW + SRAW_ + SLD + SLD_ + SRD + SRD_ + SRADI + SRADI_ + SRAD + SRAD_ + CDTBCD + CBCDTD + ADDG6S + MTSPR + MFSPR + MTCRF + MFCR + MTSLE + MFVSRD + MFVSRWZ + MTVSRD + MTVSRWA + MTVSRWZ + MTOCRF + MFOCRF + MCRXR + MTDCRUX + MFDCRUX + LFS + LFSU + LFSX + LFSUX + LFD + LFDU + LFDX + LFDUX + LFIWAX + LFIWZX + STFS + STFSU + STFSX + STFSUX + STFD + STFDU + STFDX + STFDUX + STFIWX + LFDP + LFDPX + STFDP + STFDPX + FMR + FMR_ + FABS + FABS_ + FNABS + FNABS_ + FNEG + FNEG_ + FCPSGN + FCPSGN_ + FMRGEW + FMRGOW + FADD + FADD_ + FADDS + FADDS_ + FSUB + FSUB_ + FSUBS + FSUBS_ + FMUL + FMUL_ + FMULS + FMULS_ + FDIV + FDIV_ + FDIVS + FDIVS_ + FSQRT + FSQRT_ + FSQRTS + FSQRTS_ + FRE + FRE_ + FRES + FRES_ + FRSQRTE + FRSQRTE_ + FRSQRTES + FRSQRTES_ + FTDIV + FTSQRT + FMADD + FMADD_ + FMADDS + FMADDS_ + FMSUB + FMSUB_ + FMSUBS + FMSUBS_ + FNMADD + FNMADD_ + FNMADDS + FNMADDS_ + FNMSUB + FNMSUB_ + FNMSUBS + FNMSUBS_ + FRSP + FRSP_ + FCTID + FCTID_ + FCTIDZ + FCTIDZ_ + FCTIDU + FCTIDU_ + FCTIDUZ + FCTIDUZ_ + FCTIW + FCTIW_ + FCTIWZ + FCTIWZ_ + FCTIWU + FCTIWU_ + FCTIWUZ + FCTIWUZ_ + FCFID + FCFID_ + FCFIDU + FCFIDU_ + FCFIDS + FCFIDS_ + FCFIDUS + FCFIDUS_ + FRIN + FRIN_ + FRIZ + FRIZ_ + FRIP + FRIP_ + FRIM + FRIM_ + FCMPU + FCMPO + FSEL + FSEL_ + MFFS + MFFS_ + MCRFS + MTFSFI + MTFSFI_ + MTFSF + MTFSF_ + MTFSB0 + MTFSB0_ + MTFSB1 + MTFSB1_ + LVEBX + LVEHX + LVEWX + LVX + LVXL + STVEBX + STVEHX + STVEWX + STVX + STVXL + LVSL + LVSR + VPKPX + VPKSDSS + VPKSDUS + VPKSHSS + VPKSHUS + VPKSWSS + VPKSWUS + VPKUDUM + VPKUDUS + VPKUHUM + VPKUHUS + VPKUWUM + VPKUWUS + VUPKHPX + VUPKLPX + VUPKHSB + VUPKHSH + VUPKHSW + VUPKLSB + VUPKLSH + VUPKLSW + VMRGHB + VMRGHH + VMRGLB + VMRGLH + VMRGHW + VMRGLW + VMRGEW + VMRGOW + VSPLTB + VSPLTH + VSPLTW + VSPLTISB + VSPLTISH + VSPLTISW + VPERM + VSEL + VSL + VSLDOI + VSLO + VSR + VSRO + VADDCUW + VADDSBS + VADDSHS + VADDSWS + VADDUBM + VADDUDM + VADDUHM + VADDUWM + VADDUBS + VADDUHS + VADDUWS + VADDUQM + VADDEUQM + VADDCUQ + VADDECUQ + VSUBCUW + VSUBSBS + VSUBSHS + VSUBSWS + VSUBUBM + VSUBUDM + VSUBUHM + VSUBUWM + VSUBUBS + VSUBUHS + VSUBUWS + VSUBUQM + VSUBEUQM + VSUBCUQ + VSUBECUQ + VMULESB + VMULEUB + VMULOSB + VMULOUB + VMULESH + VMULEUH + VMULOSH + VMULOUH + VMULESW + VMULEUW + VMULOSW + VMULOUW + VMULUWM + VMHADDSHS + VMHRADDSHS + VMLADDUHM + VMSUMUBM + VMSUMMBM + VMSUMSHM + VMSUMSHS + VMSUMUHM + VMSUMUHS + VSUMSWS + VSUM2SWS + VSUM4SBS + VSUM4SHS + VSUM4UBS + VAVGSB + VAVGSH + VAVGSW + VAVGUB + VAVGUW + VAVGUH + VMAXSB + VMAXSD + VMAXUB + VMAXUD + VMAXSH + VMAXSW + VMAXUH + VMAXUW + VMINSB + VMINSD + VMINUB + VMINUD + VMINSH + VMINSW + VMINUH + VMINUW + VCMPEQUB + VCMPEQUB_ + VCMPEQUH + VCMPEQUH_ + VCMPEQUW + VCMPEQUW_ + VCMPEQUD + VCMPEQUD_ + VCMPGTSB + VCMPGTSB_ + VCMPGTSD + VCMPGTSD_ + VCMPGTSH + VCMPGTSH_ + VCMPGTSW + VCMPGTSW_ + VCMPGTUB + VCMPGTUB_ + VCMPGTUD + VCMPGTUD_ + VCMPGTUH + VCMPGTUH_ + VCMPGTUW + VCMPGTUW_ + VAND + VANDC + VEQV + VNAND + VORC + VNOR + VOR + VXOR + VRLB + VRLH + VRLW + VRLD + VSLB + VSLH + VSLW + VSLD + VSRB + VSRH + VSRW + VSRD + VSRAB + VSRAH + VSRAW + VSRAD + VADDFP + VSUBFP + VMADDFP + VNMSUBFP + VMAXFP + VMINFP + VCTSXS + VCTUXS + VCFSX + VCFUX + VRFIM + VRFIN + VRFIP + VRFIZ + VCMPBFP + VCMPBFP_ + VCMPEQFP + VCMPEQFP_ + VCMPGEFP + VCMPGEFP_ + VCMPGTFP + VCMPGTFP_ + VEXPTEFP + VLOGEFP + VREFP + VRSQRTEFP + VCIPHER + VCIPHERLAST + VNCIPHER + VNCIPHERLAST + VSBOX + VSHASIGMAD + VSHASIGMAW + VPMSUMB + VPMSUMD + VPMSUMH + VPMSUMW + VPERMXOR + VGBBD + VCLZB + VCLZH + VCLZW + VCLZD + VPOPCNTB + VPOPCNTD + VPOPCNTH + VPOPCNTW + VBPERMQ + BCDADD_ + BCDSUB_ + MTVSCR + MFVSCR + DADD + DADD_ + DSUB + DSUB_ + DMUL + DMUL_ + DDIV + DDIV_ + DCMPU + DCMPO + DTSTDC + DTSTDG + DTSTEX + DTSTSF + DQUAI + DQUAI_ + DQUA + DQUA_ + DRRND + DRRND_ + DRINTX + DRINTX_ + DRINTN + DRINTN_ + DCTDP + DCTDP_ + DCTQPQ + DCTQPQ_ + DRSP + DRSP_ + DRDPQ + DRDPQ_ + DCFFIX + DCFFIX_ + DCFFIXQ + DCFFIXQ_ + DCTFIX + DCTFIX_ + DDEDPD + DDEDPD_ + DENBCD + DENBCD_ + DXEX + DXEX_ + DIEX + DIEX_ + DSCLI + DSCLI_ + DSCRI + DSCRI_ + LXSDX + LXSIWAX + LXSIWZX + LXSSPX + LXVD2X + LXVDSX + LXVW4X + STXSDX + STXSIWX + STXSSPX + STXVD2X + STXVW4X + XSABSDP + XSADDDP + XSADDSP + XSCMPODP + XSCMPUDP + XSCPSGNDP + XSCVDPSP + XSCVDPSPN + XSCVDPSXDS + XSCVDPSXWS + XSCVDPUXDS + XSCVDPUXWS + XSCVSPDP + XSCVSPDPN + XSCVSXDDP + XSCVSXDSP + XSCVUXDDP + XSCVUXDSP + XSDIVDP + XSDIVSP + XSMADDADP + XSMADDASP + XSMAXDP + XSMINDP + XSMSUBADP + XSMSUBASP + XSMULDP + XSMULSP + XSNABSDP + XSNEGDP + XSNMADDADP + XSNMADDASP + XSNMSUBADP + XSNMSUBASP + XSRDPI + XSRDPIC + XSRDPIM + XSRDPIP + XSRDPIZ + XSREDP + XSRESP + XSRSP + XSRSQRTEDP + XSRSQRTESP + XSSQRTDP + XSSQRTSP + XSSUBDP + XSSUBSP + XSTDIVDP + XSTSQRTDP + XVABSDP + XVABSSP + XVADDDP + XVADDSP + XVCMPEQDP + XVCMPEQDP_ + XVCMPEQSP + XVCMPEQSP_ + XVCMPGEDP + XVCMPGEDP_ + XVCMPGESP + XVCMPGESP_ + XVCMPGTDP + XVCMPGTDP_ + XVCMPGTSP + XVCMPGTSP_ + XVCPSGNDP + XVCPSGNSP + XVCVDPSP + XVCVDPSXDS + XVCVDPSXWS + XVCVDPUXDS + XVCVDPUXWS + XVCVSPDP + XVCVSPSXDS + XVCVSPSXWS + XVCVSPUXDS + XVCVSPUXWS + XVCVSXDDP + XVCVSXDSP + XVCVSXWDP + XVCVSXWSP + XVCVUXDDP + XVCVUXDSP + XVCVUXWDP + XVCVUXWSP + XVDIVDP + XVDIVSP + XVMADDADP + XVMADDASP + XVMAXDP + XVMAXSP + XVMINDP + XVMINSP + XVMSUBADP + XVMSUBASP + XVMULDP + XVMULSP + XVNABSDP + XVNABSSP + XVNEGDP + XVNEGSP + XVNMADDADP + XVNMADDASP + XVNMSUBADP + XVNMSUBASP + XVRDPI + XVRDPIC + XVRDPIM + XVRDPIP + XVRDPIZ + XVREDP + XVRESP + XVRSPI + XVRSPIC + XVRSPIM + XVRSPIP + XVRSPIZ + XVRSQRTEDP + XVRSQRTESP + XVSQRTDP + XVSQRTSP + XVSUBDP + XVSUBSP + XVTDIVDP + XVTDIVSP + XVTSQRTDP + XVTSQRTSP + XXLAND + XXLANDC + XXLEQV + XXLNAND + XXLORC + XXLNOR + XXLOR + XXLXOR + XXMRGHW + XXMRGLW + XXPERMDI + XXSEL + XXSLDWI + XXSPLTW + BRINC + EVABS + EVADDIW + EVADDSMIAAW + EVADDSSIAAW + EVADDUMIAAW + EVADDUSIAAW + EVADDW + EVAND + EVCMPEQ + EVANDC + EVCMPGTS + EVCMPGTU + EVCMPLTU + EVCMPLTS + EVCNTLSW + EVCNTLZW + EVDIVWS + EVDIVWU + EVEQV + EVEXTSB + EVEXTSH + EVLDD + EVLDH + EVLDDX + EVLDHX + EVLDW + EVLHHESPLAT + EVLDWX + EVLHHESPLATX + EVLHHOSSPLAT + EVLHHOUSPLAT + EVLHHOSSPLATX + EVLHHOUSPLATX + EVLWHE + EVLWHOS + EVLWHEX + EVLWHOSX + EVLWHOU + EVLWHSPLAT + EVLWHOUX + EVLWHSPLATX + EVLWWSPLAT + EVMERGEHI + EVLWWSPLATX + EVMERGELO + EVMERGEHILO + EVMHEGSMFAA + EVMERGELOHI + EVMHEGSMFAN + EVMHEGSMIAA + EVMHEGUMIAA + EVMHEGSMIAN + EVMHEGUMIAN + EVMHESMF + EVMHESMFAAW + EVMHESMFA + EVMHESMFANW + EVMHESMI + EVMHESMIAAW + EVMHESMIA + EVMHESMIANW + EVMHESSF + EVMHESSFA + EVMHESSFAAW + EVMHESSFANW + EVMHESSIAAW + EVMHESSIANW + EVMHEUMI + EVMHEUMIAAW + EVMHEUMIA + EVMHEUMIANW + EVMHEUSIAAW + EVMHEUSIANW + EVMHOGSMFAA + EVMHOGSMIAA + EVMHOGSMFAN + EVMHOGSMIAN + EVMHOGUMIAA + EVMHOSMF + EVMHOGUMIAN + EVMHOSMFA + EVMHOSMFAAW + EVMHOSMI + EVMHOSMFANW + EVMHOSMIA + EVMHOSMIAAW + EVMHOSMIANW + EVMHOSSF + EVMHOSSFA + EVMHOSSFAAW + EVMHOSSFANW + EVMHOSSIAAW + EVMHOUMI + EVMHOSSIANW + EVMHOUMIA + EVMHOUMIAAW + EVMHOUSIAAW + EVMHOUMIANW + EVMHOUSIANW + EVMRA + EVMWHSMF + EVMWHSMI + EVMWHSMFA + EVMWHSMIA + EVMWHSSF + EVMWHUMI + EVMWHSSFA + EVMWHUMIA + EVMWLSMIAAW + EVMWLSSIAAW + EVMWLSMIANW + EVMWLSSIANW + EVMWLUMI + EVMWLUMIAAW + EVMWLUMIA + EVMWLUMIANW + EVMWLUSIAAW + EVMWSMF + EVMWLUSIANW + EVMWSMFA + EVMWSMFAA + EVMWSMI + EVMWSMIAA + EVMWSMFAN + EVMWSMIA + EVMWSMIAN + EVMWSSF + EVMWSSFA + EVMWSSFAA + EVMWUMI + EVMWSSFAN + EVMWUMIA + EVMWUMIAA + EVNAND + EVMWUMIAN + EVNEG + EVNOR + EVORC + EVOR + EVRLW + EVRLWI + EVSEL + EVRNDW + EVSLW + EVSPLATFI + EVSRWIS + EVSLWI + EVSPLATI + EVSRWIU + EVSRWS + EVSTDD + EVSRWU + EVSTDDX + EVSTDH + EVSTDW + EVSTDHX + EVSTDWX + EVSTWHE + EVSTWHO + EVSTWWE + EVSTWHEX + EVSTWHOX + EVSTWWEX + EVSTWWO + EVSUBFSMIAAW + EVSTWWOX + EVSUBFSSIAAW + EVSUBFUMIAAW + EVSUBFUSIAAW + EVSUBFW + EVSUBIFW + EVXOR + EVFSABS + EVFSNABS + EVFSNEG + EVFSADD + EVFSMUL + EVFSSUB + EVFSDIV + EVFSCMPGT + EVFSCMPLT + EVFSCMPEQ + EVFSTSTGT + EVFSTSTLT + EVFSTSTEQ + EVFSCFSI + EVFSCFSF + EVFSCFUI + EVFSCFUF + EVFSCTSI + EVFSCTUI + EVFSCTSIZ + EVFSCTUIZ + EVFSCTSF + EVFSCTUF + EFSABS + EFSNEG + EFSNABS + EFSADD + EFSMUL + EFSSUB + EFSDIV + EFSCMPGT + EFSCMPLT + EFSCMPEQ + EFSTSTGT + EFSTSTLT + EFSTSTEQ + EFSCFSI + EFSCFSF + EFSCTSI + EFSCFUI + EFSCFUF + EFSCTUI + EFSCTSIZ + EFSCTSF + EFSCTUIZ + EFSCTUF + EFDABS + EFDNEG + EFDNABS + EFDADD + EFDMUL + EFDSUB + EFDDIV + EFDCMPGT + EFDCMPEQ + EFDCMPLT + EFDTSTGT + EFDTSTLT + EFDCFSI + EFDTSTEQ + EFDCFUI + EFDCFSID + EFDCFSF + EFDCFUF + EFDCFUID + EFDCTSI + EFDCTUI + EFDCTSIDZ + EFDCTUIDZ + EFDCTSIZ + EFDCTSF + EFDCTUF + EFDCTUIZ + EFDCFS + EFSCFD + DLMZB + DLMZB_ + MACCHW + MACCHW_ + MACCHWO + MACCHWO_ + MACCHWS + MACCHWS_ + MACCHWSO + MACCHWSO_ + MACCHWU + MACCHWU_ + MACCHWUO + MACCHWUO_ + MACCHWSU + MACCHWSU_ + MACCHWSUO + MACCHWSUO_ + MACHHW + MACHHW_ + MACHHWO + MACHHWO_ + MACHHWS + MACHHWS_ + MACHHWSO + MACHHWSO_ + MACHHWU + MACHHWU_ + MACHHWUO + MACHHWUO_ + MACHHWSU + MACHHWSU_ + MACHHWSUO + MACHHWSUO_ + MACLHW + MACLHW_ + MACLHWO + MACLHWO_ + MACLHWS + MACLHWS_ + MACLHWSO + MACLHWSO_ + MACLHWU + MACLHWU_ + MACLHWUO + MACLHWUO_ + MULCHW + MULCHW_ + MACLHWSU + MACLHWSU_ + MACLHWSUO + MACLHWSUO_ + MULCHWU + MULCHWU_ + MULHHW + MULHHW_ + MULLHW + MULLHW_ + MULHHWU + MULHHWU_ + MULLHWU + MULLHWU_ + NMACCHW + NMACCHW_ + NMACCHWO + NMACCHWO_ + NMACCHWS + NMACCHWS_ + NMACCHWSO + NMACCHWSO_ + NMACHHW + NMACHHW_ + NMACHHWO + NMACHHWO_ + NMACHHWS + NMACHHWS_ + NMACHHWSO + NMACHHWSO_ + NMACLHW + NMACLHW_ + NMACLHWO + NMACLHWO_ + NMACLHWS + NMACLHWS_ + NMACLHWSO + NMACLHWSO_ + ICBI + ICBT + DCBA + DCBT + DCBTST + DCBZ + DCBST + DCBF + ISYNC + LBARX + LHARX + LWARX + STBCX_ + STHCX_ + STWCX_ + LDARX + STDCX_ + LQARX + STQCX_ + SYNC + EIEIO + MBAR + WAIT + TBEGIN_ + TEND_ + TABORT_ + TABORTWC_ + TABORTWCI_ + TABORTDC_ + TABORTDCI_ + TSR_ + TCHECK + MFTB + RFEBB + LBDX + LHDX + LWDX + LDDX + LFDDX + STBDX + STHDX + STWDX + STDDX + STFDDX + DSN + ECIWX + ECOWX + RFID + HRFID + DOZE + NAP + SLEEP + RVWINKLE + LBZCIX + LWZCIX + LHZCIX + LDCIX + STBCIX + STWCIX + STHCIX + STDCIX + TRECLAIM_ + TRECHKPT_ + MTMSR + MTMSRD + MFMSR + SLBIE + SLBIA + SLBMTE + SLBMFEV + SLBMFEE + SLBFEE_ + MTSR + MTSRIN + MFSR + MFSRIN + TLBIE + TLBIEL + TLBIA + TLBSYNC + MSGSND + MSGCLR + MSGSNDP + MSGCLRP + MTTMR + RFI + RFCI + RFDI + RFMCI + RFGI + EHPRIV + MTDCR + MTDCRX + MFDCR + MFDCRX + WRTEE + WRTEEI + LBEPX + LHEPX + LWEPX + LDEPX + STBEPX + STHEPX + STWEPX + STDEPX + DCBSTEP + DCBTEP + DCBFEP + DCBTSTEP + ICBIEP + DCBZEP + LFDEPX + STFDEPX + EVLDDEPX + EVSTDDEPX + LVEPX + LVEPXL + STVEPX + STVEPXL + DCBI + DCBLQ_ + ICBLQ_ + DCBTLS + DCBTSTLS + ICBTLS + ICBLC + DCBLC + TLBIVAX + TLBILX + TLBSX + TLBSRX_ + TLBRE + TLBWE + DNH + DCI + ICI + DCREAD + ICREAD + MFPMR + MTPMR +) + +var opstr = [...]string{ + CNTLZW: "cntlzw", + CNTLZW_: "cntlzw.", + B: "b", + BA: "ba", + BL: "bl", + BLA: "bla", + BC: "bc", + BCA: "bca", + BCL: "bcl", + BCLA: "bcla", + BCLR: "bclr", + BCLRL: "bclrl", + BCCTR: "bcctr", + BCCTRL: "bcctrl", + BCTAR: "bctar", + BCTARL: "bctarl", + CRAND: "crand", + CROR: "cror", + CRNAND: "crnand", + CRXOR: "crxor", + CRNOR: "crnor", + CRANDC: "crandc", + MCRF: "mcrf", + CREQV: "creqv", + CRORC: "crorc", + SC: "sc", + CLRBHRB: "clrbhrb", + MFBHRBE: "mfbhrbe", + LBZ: "lbz", + LBZU: "lbzu", + LBZX: "lbzx", + LBZUX: "lbzux", + LHZ: "lhz", + LHZU: "lhzu", + LHZX: "lhzx", + LHZUX: "lhzux", + LHA: "lha", + LHAU: "lhau", + LHAX: "lhax", + LHAUX: "lhaux", + LWZ: "lwz", + LWZU: "lwzu", + LWZX: "lwzx", + LWZUX: "lwzux", + LWA: "lwa", + LWAX: "lwax", + LWAUX: "lwaux", + LD: "ld", + LDU: "ldu", + LDX: "ldx", + LDUX: "ldux", + STB: "stb", + STBU: "stbu", + STBX: "stbx", + STBUX: "stbux", + STH: "sth", + STHU: "sthu", + STHX: "sthx", + STHUX: "sthux", + STW: "stw", + STWU: "stwu", + STWX: "stwx", + STWUX: "stwux", + STD: "std", + STDU: "stdu", + STDX: "stdx", + STDUX: "stdux", + LQ: "lq", + STQ: "stq", + LHBRX: "lhbrx", + LWBRX: "lwbrx", + STHBRX: "sthbrx", + STWBRX: "stwbrx", + LDBRX: "ldbrx", + STDBRX: "stdbrx", + LMW: "lmw", + STMW: "stmw", + LSWI: "lswi", + LSWX: "lswx", + STSWI: "stswi", + STSWX: "stswx", + LI: "li", + ADDI: "addi", + LIS: "lis", + ADDIS: "addis", + ADD: "add", + ADD_: "add.", + ADDO: "addo", + ADDO_: "addo.", + ADDIC: "addic", + SUBF: "subf", + SUBF_: "subf.", + SUBFO: "subfo", + SUBFO_: "subfo.", + ADDIC_: "addic.", + SUBFIC: "subfic", + ADDC: "addc", + ADDC_: "addc.", + ADDCO: "addco", + ADDCO_: "addco.", + SUBFC: "subfc", + SUBFC_: "subfc.", + SUBFCO: "subfco", + SUBFCO_: "subfco.", + ADDE: "adde", + ADDE_: "adde.", + ADDEO: "addeo", + ADDEO_: "addeo.", + ADDME: "addme", + ADDME_: "addme.", + ADDMEO: "addmeo", + ADDMEO_: "addmeo.", + SUBFE: "subfe", + SUBFE_: "subfe.", + SUBFEO: "subfeo", + SUBFEO_: "subfeo.", + SUBFME: "subfme", + SUBFME_: "subfme.", + SUBFMEO: "subfmeo", + SUBFMEO_: "subfmeo.", + ADDZE: "addze", + ADDZE_: "addze.", + ADDZEO: "addzeo", + ADDZEO_: "addzeo.", + SUBFZE: "subfze", + SUBFZE_: "subfze.", + SUBFZEO: "subfzeo", + SUBFZEO_: "subfzeo.", + NEG: "neg", + NEG_: "neg.", + NEGO: "nego", + NEGO_: "nego.", + MULLI: "mulli", + MULLW: "mullw", + MULLW_: "mullw.", + MULLWO: "mullwo", + MULLWO_: "mullwo.", + MULHW: "mulhw", + MULHW_: "mulhw.", + MULHWU: "mulhwu", + MULHWU_: "mulhwu.", + DIVW: "divw", + DIVW_: "divw.", + DIVWO: "divwo", + DIVWO_: "divwo.", + DIVWU: "divwu", + DIVWU_: "divwu.", + DIVWUO: "divwuo", + DIVWUO_: "divwuo.", + DIVWE: "divwe", + DIVWE_: "divwe.", + DIVWEO: "divweo", + DIVWEO_: "divweo.", + DIVWEU: "divweu", + DIVWEU_: "divweu.", + DIVWEUO: "divweuo", + DIVWEUO_: "divweuo.", + MULLD: "mulld", + MULLD_: "mulld.", + MULLDO: "mulldo", + MULLDO_: "mulldo.", + MULHDU: "mulhdu", + MULHDU_: "mulhdu.", + MULHD: "mulhd", + MULHD_: "mulhd.", + DIVD: "divd", + DIVD_: "divd.", + DIVDO: "divdo", + DIVDO_: "divdo.", + DIVDU: "divdu", + DIVDU_: "divdu.", + DIVDUO: "divduo", + DIVDUO_: "divduo.", + DIVDE: "divde", + DIVDE_: "divde.", + DIVDEO: "divdeo", + DIVDEO_: "divdeo.", + DIVDEU: "divdeu", + DIVDEU_: "divdeu.", + DIVDEUO: "divdeuo", + DIVDEUO_: "divdeuo.", + CMPWI: "cmpwi", + CMPDI: "cmpdi", + CMPW: "cmpw", + CMPD: "cmpd", + CMPLWI: "cmplwi", + CMPLDI: "cmpldi", + CMPLW: "cmplw", + CMPLD: "cmpld", + TWI: "twi", + TW: "tw", + TDI: "tdi", + ISEL: "isel", + TD: "td", + ANDI_: "andi.", + ANDIS_: "andis.", + ORI: "ori", + ORIS: "oris", + XORI: "xori", + XORIS: "xoris", + AND: "and", + AND_: "and.", + XOR: "xor", + XOR_: "xor.", + NAND: "nand", + NAND_: "nand.", + OR: "or", + OR_: "or.", + NOR: "nor", + NOR_: "nor.", + ANDC: "andc", + ANDC_: "andc.", + EXTSB: "extsb", + EXTSB_: "extsb.", + EQV: "eqv", + EQV_: "eqv.", + ORC: "orc", + ORC_: "orc.", + EXTSH: "extsh", + EXTSH_: "extsh.", + CMPB: "cmpb", + POPCNTB: "popcntb", + POPCNTW: "popcntw", + PRTYD: "prtyd", + PRTYW: "prtyw", + EXTSW: "extsw", + EXTSW_: "extsw.", + CNTLZD: "cntlzd", + CNTLZD_: "cntlzd.", + POPCNTD: "popcntd", + BPERMD: "bpermd", + RLWINM: "rlwinm", + RLWINM_: "rlwinm.", + RLWNM: "rlwnm", + RLWNM_: "rlwnm.", + RLWIMI: "rlwimi", + RLWIMI_: "rlwimi.", + RLDICL: "rldicl", + RLDICL_: "rldicl.", + RLDICR: "rldicr", + RLDICR_: "rldicr.", + RLDIC: "rldic", + RLDIC_: "rldic.", + RLDCL: "rldcl", + RLDCL_: "rldcl.", + RLDCR: "rldcr", + RLDCR_: "rldcr.", + RLDIMI: "rldimi", + RLDIMI_: "rldimi.", + SLW: "slw", + SLW_: "slw.", + SRW: "srw", + SRW_: "srw.", + SRAWI: "srawi", + SRAWI_: "srawi.", + SRAW: "sraw", + SRAW_: "sraw.", + SLD: "sld", + SLD_: "sld.", + SRD: "srd", + SRD_: "srd.", + SRADI: "sradi", + SRADI_: "sradi.", + SRAD: "srad", + SRAD_: "srad.", + CDTBCD: "cdtbcd", + CBCDTD: "cbcdtd", + ADDG6S: "addg6s", + MTSPR: "mtspr", + MFSPR: "mfspr", + MTCRF: "mtcrf", + MFCR: "mfcr", + MTSLE: "mtsle", + MFVSRD: "mfvsrd", + MFVSRWZ: "mfvsrwz", + MTVSRD: "mtvsrd", + MTVSRWA: "mtvsrwa", + MTVSRWZ: "mtvsrwz", + MTOCRF: "mtocrf", + MFOCRF: "mfocrf", + MCRXR: "mcrxr", + MTDCRUX: "mtdcrux", + MFDCRUX: "mfdcrux", + LFS: "lfs", + LFSU: "lfsu", + LFSX: "lfsx", + LFSUX: "lfsux", + LFD: "lfd", + LFDU: "lfdu", + LFDX: "lfdx", + LFDUX: "lfdux", + LFIWAX: "lfiwax", + LFIWZX: "lfiwzx", + STFS: "stfs", + STFSU: "stfsu", + STFSX: "stfsx", + STFSUX: "stfsux", + STFD: "stfd", + STFDU: "stfdu", + STFDX: "stfdx", + STFDUX: "stfdux", + STFIWX: "stfiwx", + LFDP: "lfdp", + LFDPX: "lfdpx", + STFDP: "stfdp", + STFDPX: "stfdpx", + FMR: "fmr", + FMR_: "fmr.", + FABS: "fabs", + FABS_: "fabs.", + FNABS: "fnabs", + FNABS_: "fnabs.", + FNEG: "fneg", + FNEG_: "fneg.", + FCPSGN: "fcpsgn", + FCPSGN_: "fcpsgn.", + FMRGEW: "fmrgew", + FMRGOW: "fmrgow", + FADD: "fadd", + FADD_: "fadd.", + FADDS: "fadds", + FADDS_: "fadds.", + FSUB: "fsub", + FSUB_: "fsub.", + FSUBS: "fsubs", + FSUBS_: "fsubs.", + FMUL: "fmul", + FMUL_: "fmul.", + FMULS: "fmuls", + FMULS_: "fmuls.", + FDIV: "fdiv", + FDIV_: "fdiv.", + FDIVS: "fdivs", + FDIVS_: "fdivs.", + FSQRT: "fsqrt", + FSQRT_: "fsqrt.", + FSQRTS: "fsqrts", + FSQRTS_: "fsqrts.", + FRE: "fre", + FRE_: "fre.", + FRES: "fres", + FRES_: "fres.", + FRSQRTE: "frsqrte", + FRSQRTE_: "frsqrte.", + FRSQRTES: "frsqrtes", + FRSQRTES_: "frsqrtes.", + FTDIV: "ftdiv", + FTSQRT: "ftsqrt", + FMADD: "fmadd", + FMADD_: "fmadd.", + FMADDS: "fmadds", + FMADDS_: "fmadds.", + FMSUB: "fmsub", + FMSUB_: "fmsub.", + FMSUBS: "fmsubs", + FMSUBS_: "fmsubs.", + FNMADD: "fnmadd", + FNMADD_: "fnmadd.", + FNMADDS: "fnmadds", + FNMADDS_: "fnmadds.", + FNMSUB: "fnmsub", + FNMSUB_: "fnmsub.", + FNMSUBS: "fnmsubs", + FNMSUBS_: "fnmsubs.", + FRSP: "frsp", + FRSP_: "frsp.", + FCTID: "fctid", + FCTID_: "fctid.", + FCTIDZ: "fctidz", + FCTIDZ_: "fctidz.", + FCTIDU: "fctidu", + FCTIDU_: "fctidu.", + FCTIDUZ: "fctiduz", + FCTIDUZ_: "fctiduz.", + FCTIW: "fctiw", + FCTIW_: "fctiw.", + FCTIWZ: "fctiwz", + FCTIWZ_: "fctiwz.", + FCTIWU: "fctiwu", + FCTIWU_: "fctiwu.", + FCTIWUZ: "fctiwuz", + FCTIWUZ_: "fctiwuz.", + FCFID: "fcfid", + FCFID_: "fcfid.", + FCFIDU: "fcfidu", + FCFIDU_: "fcfidu.", + FCFIDS: "fcfids", + FCFIDS_: "fcfids.", + FCFIDUS: "fcfidus", + FCFIDUS_: "fcfidus.", + FRIN: "frin", + FRIN_: "frin.", + FRIZ: "friz", + FRIZ_: "friz.", + FRIP: "frip", + FRIP_: "frip.", + FRIM: "frim", + FRIM_: "frim.", + FCMPU: "fcmpu", + FCMPO: "fcmpo", + FSEL: "fsel", + FSEL_: "fsel.", + MFFS: "mffs", + MFFS_: "mffs.", + MCRFS: "mcrfs", + MTFSFI: "mtfsfi", + MTFSFI_: "mtfsfi.", + MTFSF: "mtfsf", + MTFSF_: "mtfsf.", + MTFSB0: "mtfsb0", + MTFSB0_: "mtfsb0.", + MTFSB1: "mtfsb1", + MTFSB1_: "mtfsb1.", + LVEBX: "lvebx", + LVEHX: "lvehx", + LVEWX: "lvewx", + LVX: "lvx", + LVXL: "lvxl", + STVEBX: "stvebx", + STVEHX: "stvehx", + STVEWX: "stvewx", + STVX: "stvx", + STVXL: "stvxl", + LVSL: "lvsl", + LVSR: "lvsr", + VPKPX: "vpkpx", + VPKSDSS: "vpksdss", + VPKSDUS: "vpksdus", + VPKSHSS: "vpkshss", + VPKSHUS: "vpkshus", + VPKSWSS: "vpkswss", + VPKSWUS: "vpkswus", + VPKUDUM: "vpkudum", + VPKUDUS: "vpkudus", + VPKUHUM: "vpkuhum", + VPKUHUS: "vpkuhus", + VPKUWUM: "vpkuwum", + VPKUWUS: "vpkuwus", + VUPKHPX: "vupkhpx", + VUPKLPX: "vupklpx", + VUPKHSB: "vupkhsb", + VUPKHSH: "vupkhsh", + VUPKHSW: "vupkhsw", + VUPKLSB: "vupklsb", + VUPKLSH: "vupklsh", + VUPKLSW: "vupklsw", + VMRGHB: "vmrghb", + VMRGHH: "vmrghh", + VMRGLB: "vmrglb", + VMRGLH: "vmrglh", + VMRGHW: "vmrghw", + VMRGLW: "vmrglw", + VMRGEW: "vmrgew", + VMRGOW: "vmrgow", + VSPLTB: "vspltb", + VSPLTH: "vsplth", + VSPLTW: "vspltw", + VSPLTISB: "vspltisb", + VSPLTISH: "vspltish", + VSPLTISW: "vspltisw", + VPERM: "vperm", + VSEL: "vsel", + VSL: "vsl", + VSLDOI: "vsldoi", + VSLO: "vslo", + VSR: "vsr", + VSRO: "vsro", + VADDCUW: "vaddcuw", + VADDSBS: "vaddsbs", + VADDSHS: "vaddshs", + VADDSWS: "vaddsws", + VADDUBM: "vaddubm", + VADDUDM: "vaddudm", + VADDUHM: "vadduhm", + VADDUWM: "vadduwm", + VADDUBS: "vaddubs", + VADDUHS: "vadduhs", + VADDUWS: "vadduws", + VADDUQM: "vadduqm", + VADDEUQM: "vaddeuqm", + VADDCUQ: "vaddcuq", + VADDECUQ: "vaddecuq", + VSUBCUW: "vsubcuw", + VSUBSBS: "vsubsbs", + VSUBSHS: "vsubshs", + VSUBSWS: "vsubsws", + VSUBUBM: "vsububm", + VSUBUDM: "vsubudm", + VSUBUHM: "vsubuhm", + VSUBUWM: "vsubuwm", + VSUBUBS: "vsububs", + VSUBUHS: "vsubuhs", + VSUBUWS: "vsubuws", + VSUBUQM: "vsubuqm", + VSUBEUQM: "vsubeuqm", + VSUBCUQ: "vsubcuq", + VSUBECUQ: "vsubecuq", + VMULESB: "vmulesb", + VMULEUB: "vmuleub", + VMULOSB: "vmulosb", + VMULOUB: "vmuloub", + VMULESH: "vmulesh", + VMULEUH: "vmuleuh", + VMULOSH: "vmulosh", + VMULOUH: "vmulouh", + VMULESW: "vmulesw", + VMULEUW: "vmuleuw", + VMULOSW: "vmulosw", + VMULOUW: "vmulouw", + VMULUWM: "vmuluwm", + VMHADDSHS: "vmhaddshs", + VMHRADDSHS: "vmhraddshs", + VMLADDUHM: "vmladduhm", + VMSUMUBM: "vmsumubm", + VMSUMMBM: "vmsummbm", + VMSUMSHM: "vmsumshm", + VMSUMSHS: "vmsumshs", + VMSUMUHM: "vmsumuhm", + VMSUMUHS: "vmsumuhs", + VSUMSWS: "vsumsws", + VSUM2SWS: "vsum2sws", + VSUM4SBS: "vsum4sbs", + VSUM4SHS: "vsum4shs", + VSUM4UBS: "vsum4ubs", + VAVGSB: "vavgsb", + VAVGSH: "vavgsh", + VAVGSW: "vavgsw", + VAVGUB: "vavgub", + VAVGUW: "vavguw", + VAVGUH: "vavguh", + VMAXSB: "vmaxsb", + VMAXSD: "vmaxsd", + VMAXUB: "vmaxub", + VMAXUD: "vmaxud", + VMAXSH: "vmaxsh", + VMAXSW: "vmaxsw", + VMAXUH: "vmaxuh", + VMAXUW: "vmaxuw", + VMINSB: "vminsb", + VMINSD: "vminsd", + VMINUB: "vminub", + VMINUD: "vminud", + VMINSH: "vminsh", + VMINSW: "vminsw", + VMINUH: "vminuh", + VMINUW: "vminuw", + VCMPEQUB: "vcmpequb", + VCMPEQUB_: "vcmpequb.", + VCMPEQUH: "vcmpequh", + VCMPEQUH_: "vcmpequh.", + VCMPEQUW: "vcmpequw", + VCMPEQUW_: "vcmpequw.", + VCMPEQUD: "vcmpequd", + VCMPEQUD_: "vcmpequd.", + VCMPGTSB: "vcmpgtsb", + VCMPGTSB_: "vcmpgtsb.", + VCMPGTSD: "vcmpgtsd", + VCMPGTSD_: "vcmpgtsd.", + VCMPGTSH: "vcmpgtsh", + VCMPGTSH_: "vcmpgtsh.", + VCMPGTSW: "vcmpgtsw", + VCMPGTSW_: "vcmpgtsw.", + VCMPGTUB: "vcmpgtub", + VCMPGTUB_: "vcmpgtub.", + VCMPGTUD: "vcmpgtud", + VCMPGTUD_: "vcmpgtud.", + VCMPGTUH: "vcmpgtuh", + VCMPGTUH_: "vcmpgtuh.", + VCMPGTUW: "vcmpgtuw", + VCMPGTUW_: "vcmpgtuw.", + VAND: "vand", + VANDC: "vandc", + VEQV: "veqv", + VNAND: "vnand", + VORC: "vorc", + VNOR: "vnor", + VOR: "vor", + VXOR: "vxor", + VRLB: "vrlb", + VRLH: "vrlh", + VRLW: "vrlw", + VRLD: "vrld", + VSLB: "vslb", + VSLH: "vslh", + VSLW: "vslw", + VSLD: "vsld", + VSRB: "vsrb", + VSRH: "vsrh", + VSRW: "vsrw", + VSRD: "vsrd", + VSRAB: "vsrab", + VSRAH: "vsrah", + VSRAW: "vsraw", + VSRAD: "vsrad", + VADDFP: "vaddfp", + VSUBFP: "vsubfp", + VMADDFP: "vmaddfp", + VNMSUBFP: "vnmsubfp", + VMAXFP: "vmaxfp", + VMINFP: "vminfp", + VCTSXS: "vctsxs", + VCTUXS: "vctuxs", + VCFSX: "vcfsx", + VCFUX: "vcfux", + VRFIM: "vrfim", + VRFIN: "vrfin", + VRFIP: "vrfip", + VRFIZ: "vrfiz", + VCMPBFP: "vcmpbfp", + VCMPBFP_: "vcmpbfp.", + VCMPEQFP: "vcmpeqfp", + VCMPEQFP_: "vcmpeqfp.", + VCMPGEFP: "vcmpgefp", + VCMPGEFP_: "vcmpgefp.", + VCMPGTFP: "vcmpgtfp", + VCMPGTFP_: "vcmpgtfp.", + VEXPTEFP: "vexptefp", + VLOGEFP: "vlogefp", + VREFP: "vrefp", + VRSQRTEFP: "vrsqrtefp", + VCIPHER: "vcipher", + VCIPHERLAST: "vcipherlast", + VNCIPHER: "vncipher", + VNCIPHERLAST: "vncipherlast", + VSBOX: "vsbox", + VSHASIGMAD: "vshasigmad", + VSHASIGMAW: "vshasigmaw", + VPMSUMB: "vpmsumb", + VPMSUMD: "vpmsumd", + VPMSUMH: "vpmsumh", + VPMSUMW: "vpmsumw", + VPERMXOR: "vpermxor", + VGBBD: "vgbbd", + VCLZB: "vclzb", + VCLZH: "vclzh", + VCLZW: "vclzw", + VCLZD: "vclzd", + VPOPCNTB: "vpopcntb", + VPOPCNTD: "vpopcntd", + VPOPCNTH: "vpopcnth", + VPOPCNTW: "vpopcntw", + VBPERMQ: "vbpermq", + BCDADD_: "bcdadd.", + BCDSUB_: "bcdsub.", + MTVSCR: "mtvscr", + MFVSCR: "mfvscr", + DADD: "dadd", + DADD_: "dadd.", + DSUB: "dsub", + DSUB_: "dsub.", + DMUL: "dmul", + DMUL_: "dmul.", + DDIV: "ddiv", + DDIV_: "ddiv.", + DCMPU: "dcmpu", + DCMPO: "dcmpo", + DTSTDC: "dtstdc", + DTSTDG: "dtstdg", + DTSTEX: "dtstex", + DTSTSF: "dtstsf", + DQUAI: "dquai", + DQUAI_: "dquai.", + DQUA: "dqua", + DQUA_: "dqua.", + DRRND: "drrnd", + DRRND_: "drrnd.", + DRINTX: "drintx", + DRINTX_: "drintx.", + DRINTN: "drintn", + DRINTN_: "drintn.", + DCTDP: "dctdp", + DCTDP_: "dctdp.", + DCTQPQ: "dctqpq", + DCTQPQ_: "dctqpq.", + DRSP: "drsp", + DRSP_: "drsp.", + DRDPQ: "drdpq", + DRDPQ_: "drdpq.", + DCFFIX: "dcffix", + DCFFIX_: "dcffix.", + DCFFIXQ: "dcffixq", + DCFFIXQ_: "dcffixq.", + DCTFIX: "dctfix", + DCTFIX_: "dctfix.", + DDEDPD: "ddedpd", + DDEDPD_: "ddedpd.", + DENBCD: "denbcd", + DENBCD_: "denbcd.", + DXEX: "dxex", + DXEX_: "dxex.", + DIEX: "diex", + DIEX_: "diex.", + DSCLI: "dscli", + DSCLI_: "dscli.", + DSCRI: "dscri", + DSCRI_: "dscri.", + LXSDX: "lxsdx", + LXSIWAX: "lxsiwax", + LXSIWZX: "lxsiwzx", + LXSSPX: "lxsspx", + LXVD2X: "lxvd2x", + LXVDSX: "lxvdsx", + LXVW4X: "lxvw4x", + STXSDX: "stxsdx", + STXSIWX: "stxsiwx", + STXSSPX: "stxsspx", + STXVD2X: "stxvd2x", + STXVW4X: "stxvw4x", + XSABSDP: "xsabsdp", + XSADDDP: "xsadddp", + XSADDSP: "xsaddsp", + XSCMPODP: "xscmpodp", + XSCMPUDP: "xscmpudp", + XSCPSGNDP: "xscpsgndp", + XSCVDPSP: "xscvdpsp", + XSCVDPSPN: "xscvdpspn", + XSCVDPSXDS: "xscvdpsxds", + XSCVDPSXWS: "xscvdpsxws", + XSCVDPUXDS: "xscvdpuxds", + XSCVDPUXWS: "xscvdpuxws", + XSCVSPDP: "xscvspdp", + XSCVSPDPN: "xscvspdpn", + XSCVSXDDP: "xscvsxddp", + XSCVSXDSP: "xscvsxdsp", + XSCVUXDDP: "xscvuxddp", + XSCVUXDSP: "xscvuxdsp", + XSDIVDP: "xsdivdp", + XSDIVSP: "xsdivsp", + XSMADDADP: "xsmaddadp", + XSMADDASP: "xsmaddasp", + XSMAXDP: "xsmaxdp", + XSMINDP: "xsmindp", + XSMSUBADP: "xsmsubadp", + XSMSUBASP: "xsmsubasp", + XSMULDP: "xsmuldp", + XSMULSP: "xsmulsp", + XSNABSDP: "xsnabsdp", + XSNEGDP: "xsnegdp", + XSNMADDADP: "xsnmaddadp", + XSNMADDASP: "xsnmaddasp", + XSNMSUBADP: "xsnmsubadp", + XSNMSUBASP: "xsnmsubasp", + XSRDPI: "xsrdpi", + XSRDPIC: "xsrdpic", + XSRDPIM: "xsrdpim", + XSRDPIP: "xsrdpip", + XSRDPIZ: "xsrdpiz", + XSREDP: "xsredp", + XSRESP: "xsresp", + XSRSP: "xsrsp", + XSRSQRTEDP: "xsrsqrtedp", + XSRSQRTESP: "xsrsqrtesp", + XSSQRTDP: "xssqrtdp", + XSSQRTSP: "xssqrtsp", + XSSUBDP: "xssubdp", + XSSUBSP: "xssubsp", + XSTDIVDP: "xstdivdp", + XSTSQRTDP: "xstsqrtdp", + XVABSDP: "xvabsdp", + XVABSSP: "xvabssp", + XVADDDP: "xvadddp", + XVADDSP: "xvaddsp", + XVCMPEQDP: "xvcmpeqdp", + XVCMPEQDP_: "xvcmpeqdp.", + XVCMPEQSP: "xvcmpeqsp", + XVCMPEQSP_: "xvcmpeqsp.", + XVCMPGEDP: "xvcmpgedp", + XVCMPGEDP_: "xvcmpgedp.", + XVCMPGESP: "xvcmpgesp", + XVCMPGESP_: "xvcmpgesp.", + XVCMPGTDP: "xvcmpgtdp", + XVCMPGTDP_: "xvcmpgtdp.", + XVCMPGTSP: "xvcmpgtsp", + XVCMPGTSP_: "xvcmpgtsp.", + XVCPSGNDP: "xvcpsgndp", + XVCPSGNSP: "xvcpsgnsp", + XVCVDPSP: "xvcvdpsp", + XVCVDPSXDS: "xvcvdpsxds", + XVCVDPSXWS: "xvcvdpsxws", + XVCVDPUXDS: "xvcvdpuxds", + XVCVDPUXWS: "xvcvdpuxws", + XVCVSPDP: "xvcvspdp", + XVCVSPSXDS: "xvcvspsxds", + XVCVSPSXWS: "xvcvspsxws", + XVCVSPUXDS: "xvcvspuxds", + XVCVSPUXWS: "xvcvspuxws", + XVCVSXDDP: "xvcvsxddp", + XVCVSXDSP: "xvcvsxdsp", + XVCVSXWDP: "xvcvsxwdp", + XVCVSXWSP: "xvcvsxwsp", + XVCVUXDDP: "xvcvuxddp", + XVCVUXDSP: "xvcvuxdsp", + XVCVUXWDP: "xvcvuxwdp", + XVCVUXWSP: "xvcvuxwsp", + XVDIVDP: "xvdivdp", + XVDIVSP: "xvdivsp", + XVMADDADP: "xvmaddadp", + XVMADDASP: "xvmaddasp", + XVMAXDP: "xvmaxdp", + XVMAXSP: "xvmaxsp", + XVMINDP: "xvmindp", + XVMINSP: "xvminsp", + XVMSUBADP: "xvmsubadp", + XVMSUBASP: "xvmsubasp", + XVMULDP: "xvmuldp", + XVMULSP: "xvmulsp", + XVNABSDP: "xvnabsdp", + XVNABSSP: "xvnabssp", + XVNEGDP: "xvnegdp", + XVNEGSP: "xvnegsp", + XVNMADDADP: "xvnmaddadp", + XVNMADDASP: "xvnmaddasp", + XVNMSUBADP: "xvnmsubadp", + XVNMSUBASP: "xvnmsubasp", + XVRDPI: "xvrdpi", + XVRDPIC: "xvrdpic", + XVRDPIM: "xvrdpim", + XVRDPIP: "xvrdpip", + XVRDPIZ: "xvrdpiz", + XVREDP: "xvredp", + XVRESP: "xvresp", + XVRSPI: "xvrspi", + XVRSPIC: "xvrspic", + XVRSPIM: "xvrspim", + XVRSPIP: "xvrspip", + XVRSPIZ: "xvrspiz", + XVRSQRTEDP: "xvrsqrtedp", + XVRSQRTESP: "xvrsqrtesp", + XVSQRTDP: "xvsqrtdp", + XVSQRTSP: "xvsqrtsp", + XVSUBDP: "xvsubdp", + XVSUBSP: "xvsubsp", + XVTDIVDP: "xvtdivdp", + XVTDIVSP: "xvtdivsp", + XVTSQRTDP: "xvtsqrtdp", + XVTSQRTSP: "xvtsqrtsp", + XXLAND: "xxland", + XXLANDC: "xxlandc", + XXLEQV: "xxleqv", + XXLNAND: "xxlnand", + XXLORC: "xxlorc", + XXLNOR: "xxlnor", + XXLOR: "xxlor", + XXLXOR: "xxlxor", + XXMRGHW: "xxmrghw", + XXMRGLW: "xxmrglw", + XXPERMDI: "xxpermdi", + XXSEL: "xxsel", + XXSLDWI: "xxsldwi", + XXSPLTW: "xxspltw", + BRINC: "brinc", + EVABS: "evabs", + EVADDIW: "evaddiw", + EVADDSMIAAW: "evaddsmiaaw", + EVADDSSIAAW: "evaddssiaaw", + EVADDUMIAAW: "evaddumiaaw", + EVADDUSIAAW: "evaddusiaaw", + EVADDW: "evaddw", + EVAND: "evand", + EVCMPEQ: "evcmpeq", + EVANDC: "evandc", + EVCMPGTS: "evcmpgts", + EVCMPGTU: "evcmpgtu", + EVCMPLTU: "evcmpltu", + EVCMPLTS: "evcmplts", + EVCNTLSW: "evcntlsw", + EVCNTLZW: "evcntlzw", + EVDIVWS: "evdivws", + EVDIVWU: "evdivwu", + EVEQV: "eveqv", + EVEXTSB: "evextsb", + EVEXTSH: "evextsh", + EVLDD: "evldd", + EVLDH: "evldh", + EVLDDX: "evlddx", + EVLDHX: "evldhx", + EVLDW: "evldw", + EVLHHESPLAT: "evlhhesplat", + EVLDWX: "evldwx", + EVLHHESPLATX: "evlhhesplatx", + EVLHHOSSPLAT: "evlhhossplat", + EVLHHOUSPLAT: "evlhhousplat", + EVLHHOSSPLATX: "evlhhossplatx", + EVLHHOUSPLATX: "evlhhousplatx", + EVLWHE: "evlwhe", + EVLWHOS: "evlwhos", + EVLWHEX: "evlwhex", + EVLWHOSX: "evlwhosx", + EVLWHOU: "evlwhou", + EVLWHSPLAT: "evlwhsplat", + EVLWHOUX: "evlwhoux", + EVLWHSPLATX: "evlwhsplatx", + EVLWWSPLAT: "evlwwsplat", + EVMERGEHI: "evmergehi", + EVLWWSPLATX: "evlwwsplatx", + EVMERGELO: "evmergelo", + EVMERGEHILO: "evmergehilo", + EVMHEGSMFAA: "evmhegsmfaa", + EVMERGELOHI: "evmergelohi", + EVMHEGSMFAN: "evmhegsmfan", + EVMHEGSMIAA: "evmhegsmiaa", + EVMHEGUMIAA: "evmhegumiaa", + EVMHEGSMIAN: "evmhegsmian", + EVMHEGUMIAN: "evmhegumian", + EVMHESMF: "evmhesmf", + EVMHESMFAAW: "evmhesmfaaw", + EVMHESMFA: "evmhesmfa", + EVMHESMFANW: "evmhesmfanw", + EVMHESMI: "evmhesmi", + EVMHESMIAAW: "evmhesmiaaw", + EVMHESMIA: "evmhesmia", + EVMHESMIANW: "evmhesmianw", + EVMHESSF: "evmhessf", + EVMHESSFA: "evmhessfa", + EVMHESSFAAW: "evmhessfaaw", + EVMHESSFANW: "evmhessfanw", + EVMHESSIAAW: "evmhessiaaw", + EVMHESSIANW: "evmhessianw", + EVMHEUMI: "evmheumi", + EVMHEUMIAAW: "evmheumiaaw", + EVMHEUMIA: "evmheumia", + EVMHEUMIANW: "evmheumianw", + EVMHEUSIAAW: "evmheusiaaw", + EVMHEUSIANW: "evmheusianw", + EVMHOGSMFAA: "evmhogsmfaa", + EVMHOGSMIAA: "evmhogsmiaa", + EVMHOGSMFAN: "evmhogsmfan", + EVMHOGSMIAN: "evmhogsmian", + EVMHOGUMIAA: "evmhogumiaa", + EVMHOSMF: "evmhosmf", + EVMHOGUMIAN: "evmhogumian", + EVMHOSMFA: "evmhosmfa", + EVMHOSMFAAW: "evmhosmfaaw", + EVMHOSMI: "evmhosmi", + EVMHOSMFANW: "evmhosmfanw", + EVMHOSMIA: "evmhosmia", + EVMHOSMIAAW: "evmhosmiaaw", + EVMHOSMIANW: "evmhosmianw", + EVMHOSSF: "evmhossf", + EVMHOSSFA: "evmhossfa", + EVMHOSSFAAW: "evmhossfaaw", + EVMHOSSFANW: "evmhossfanw", + EVMHOSSIAAW: "evmhossiaaw", + EVMHOUMI: "evmhoumi", + EVMHOSSIANW: "evmhossianw", + EVMHOUMIA: "evmhoumia", + EVMHOUMIAAW: "evmhoumiaaw", + EVMHOUSIAAW: "evmhousiaaw", + EVMHOUMIANW: "evmhoumianw", + EVMHOUSIANW: "evmhousianw", + EVMRA: "evmra", + EVMWHSMF: "evmwhsmf", + EVMWHSMI: "evmwhsmi", + EVMWHSMFA: "evmwhsmfa", + EVMWHSMIA: "evmwhsmia", + EVMWHSSF: "evmwhssf", + EVMWHUMI: "evmwhumi", + EVMWHSSFA: "evmwhssfa", + EVMWHUMIA: "evmwhumia", + EVMWLSMIAAW: "evmwlsmiaaw", + EVMWLSSIAAW: "evmwlssiaaw", + EVMWLSMIANW: "evmwlsmianw", + EVMWLSSIANW: "evmwlssianw", + EVMWLUMI: "evmwlumi", + EVMWLUMIAAW: "evmwlumiaaw", + EVMWLUMIA: "evmwlumia", + EVMWLUMIANW: "evmwlumianw", + EVMWLUSIAAW: "evmwlusiaaw", + EVMWSMF: "evmwsmf", + EVMWLUSIANW: "evmwlusianw", + EVMWSMFA: "evmwsmfa", + EVMWSMFAA: "evmwsmfaa", + EVMWSMI: "evmwsmi", + EVMWSMIAA: "evmwsmiaa", + EVMWSMFAN: "evmwsmfan", + EVMWSMIA: "evmwsmia", + EVMWSMIAN: "evmwsmian", + EVMWSSF: "evmwssf", + EVMWSSFA: "evmwssfa", + EVMWSSFAA: "evmwssfaa", + EVMWUMI: "evmwumi", + EVMWSSFAN: "evmwssfan", + EVMWUMIA: "evmwumia", + EVMWUMIAA: "evmwumiaa", + EVNAND: "evnand", + EVMWUMIAN: "evmwumian", + EVNEG: "evneg", + EVNOR: "evnor", + EVORC: "evorc", + EVOR: "evor", + EVRLW: "evrlw", + EVRLWI: "evrlwi", + EVSEL: "evsel", + EVRNDW: "evrndw", + EVSLW: "evslw", + EVSPLATFI: "evsplatfi", + EVSRWIS: "evsrwis", + EVSLWI: "evslwi", + EVSPLATI: "evsplati", + EVSRWIU: "evsrwiu", + EVSRWS: "evsrws", + EVSTDD: "evstdd", + EVSRWU: "evsrwu", + EVSTDDX: "evstddx", + EVSTDH: "evstdh", + EVSTDW: "evstdw", + EVSTDHX: "evstdhx", + EVSTDWX: "evstdwx", + EVSTWHE: "evstwhe", + EVSTWHO: "evstwho", + EVSTWWE: "evstwwe", + EVSTWHEX: "evstwhex", + EVSTWHOX: "evstwhox", + EVSTWWEX: "evstwwex", + EVSTWWO: "evstwwo", + EVSUBFSMIAAW: "evsubfsmiaaw", + EVSTWWOX: "evstwwox", + EVSUBFSSIAAW: "evsubfssiaaw", + EVSUBFUMIAAW: "evsubfumiaaw", + EVSUBFUSIAAW: "evsubfusiaaw", + EVSUBFW: "evsubfw", + EVSUBIFW: "evsubifw", + EVXOR: "evxor", + EVFSABS: "evfsabs", + EVFSNABS: "evfsnabs", + EVFSNEG: "evfsneg", + EVFSADD: "evfsadd", + EVFSMUL: "evfsmul", + EVFSSUB: "evfssub", + EVFSDIV: "evfsdiv", + EVFSCMPGT: "evfscmpgt", + EVFSCMPLT: "evfscmplt", + EVFSCMPEQ: "evfscmpeq", + EVFSTSTGT: "evfststgt", + EVFSTSTLT: "evfststlt", + EVFSTSTEQ: "evfststeq", + EVFSCFSI: "evfscfsi", + EVFSCFSF: "evfscfsf", + EVFSCFUI: "evfscfui", + EVFSCFUF: "evfscfuf", + EVFSCTSI: "evfsctsi", + EVFSCTUI: "evfsctui", + EVFSCTSIZ: "evfsctsiz", + EVFSCTUIZ: "evfsctuiz", + EVFSCTSF: "evfsctsf", + EVFSCTUF: "evfsctuf", + EFSABS: "efsabs", + EFSNEG: "efsneg", + EFSNABS: "efsnabs", + EFSADD: "efsadd", + EFSMUL: "efsmul", + EFSSUB: "efssub", + EFSDIV: "efsdiv", + EFSCMPGT: "efscmpgt", + EFSCMPLT: "efscmplt", + EFSCMPEQ: "efscmpeq", + EFSTSTGT: "efststgt", + EFSTSTLT: "efststlt", + EFSTSTEQ: "efststeq", + EFSCFSI: "efscfsi", + EFSCFSF: "efscfsf", + EFSCTSI: "efsctsi", + EFSCFUI: "efscfui", + EFSCFUF: "efscfuf", + EFSCTUI: "efsctui", + EFSCTSIZ: "efsctsiz", + EFSCTSF: "efsctsf", + EFSCTUIZ: "efsctuiz", + EFSCTUF: "efsctuf", + EFDABS: "efdabs", + EFDNEG: "efdneg", + EFDNABS: "efdnabs", + EFDADD: "efdadd", + EFDMUL: "efdmul", + EFDSUB: "efdsub", + EFDDIV: "efddiv", + EFDCMPGT: "efdcmpgt", + EFDCMPEQ: "efdcmpeq", + EFDCMPLT: "efdcmplt", + EFDTSTGT: "efdtstgt", + EFDTSTLT: "efdtstlt", + EFDCFSI: "efdcfsi", + EFDTSTEQ: "efdtsteq", + EFDCFUI: "efdcfui", + EFDCFSID: "efdcfsid", + EFDCFSF: "efdcfsf", + EFDCFUF: "efdcfuf", + EFDCFUID: "efdcfuid", + EFDCTSI: "efdctsi", + EFDCTUI: "efdctui", + EFDCTSIDZ: "efdctsidz", + EFDCTUIDZ: "efdctuidz", + EFDCTSIZ: "efdctsiz", + EFDCTSF: "efdctsf", + EFDCTUF: "efdctuf", + EFDCTUIZ: "efdctuiz", + EFDCFS: "efdcfs", + EFSCFD: "efscfd", + DLMZB: "dlmzb", + DLMZB_: "dlmzb.", + MACCHW: "macchw", + MACCHW_: "macchw.", + MACCHWO: "macchwo", + MACCHWO_: "macchwo.", + MACCHWS: "macchws", + MACCHWS_: "macchws.", + MACCHWSO: "macchwso", + MACCHWSO_: "macchwso.", + MACCHWU: "macchwu", + MACCHWU_: "macchwu.", + MACCHWUO: "macchwuo", + MACCHWUO_: "macchwuo.", + MACCHWSU: "macchwsu", + MACCHWSU_: "macchwsu.", + MACCHWSUO: "macchwsuo", + MACCHWSUO_: "macchwsuo.", + MACHHW: "machhw", + MACHHW_: "machhw.", + MACHHWO: "machhwo", + MACHHWO_: "machhwo.", + MACHHWS: "machhws", + MACHHWS_: "machhws.", + MACHHWSO: "machhwso", + MACHHWSO_: "machhwso.", + MACHHWU: "machhwu", + MACHHWU_: "machhwu.", + MACHHWUO: "machhwuo", + MACHHWUO_: "machhwuo.", + MACHHWSU: "machhwsu", + MACHHWSU_: "machhwsu.", + MACHHWSUO: "machhwsuo", + MACHHWSUO_: "machhwsuo.", + MACLHW: "maclhw", + MACLHW_: "maclhw.", + MACLHWO: "maclhwo", + MACLHWO_: "maclhwo.", + MACLHWS: "maclhws", + MACLHWS_: "maclhws.", + MACLHWSO: "maclhwso", + MACLHWSO_: "maclhwso.", + MACLHWU: "maclhwu", + MACLHWU_: "maclhwu.", + MACLHWUO: "maclhwuo", + MACLHWUO_: "maclhwuo.", + MULCHW: "mulchw", + MULCHW_: "mulchw.", + MACLHWSU: "maclhwsu", + MACLHWSU_: "maclhwsu.", + MACLHWSUO: "maclhwsuo", + MACLHWSUO_: "maclhwsuo.", + MULCHWU: "mulchwu", + MULCHWU_: "mulchwu.", + MULHHW: "mulhhw", + MULHHW_: "mulhhw.", + MULLHW: "mullhw", + MULLHW_: "mullhw.", + MULHHWU: "mulhhwu", + MULHHWU_: "mulhhwu.", + MULLHWU: "mullhwu", + MULLHWU_: "mullhwu.", + NMACCHW: "nmacchw", + NMACCHW_: "nmacchw.", + NMACCHWO: "nmacchwo", + NMACCHWO_: "nmacchwo.", + NMACCHWS: "nmacchws", + NMACCHWS_: "nmacchws.", + NMACCHWSO: "nmacchwso", + NMACCHWSO_: "nmacchwso.", + NMACHHW: "nmachhw", + NMACHHW_: "nmachhw.", + NMACHHWO: "nmachhwo", + NMACHHWO_: "nmachhwo.", + NMACHHWS: "nmachhws", + NMACHHWS_: "nmachhws.", + NMACHHWSO: "nmachhwso", + NMACHHWSO_: "nmachhwso.", + NMACLHW: "nmaclhw", + NMACLHW_: "nmaclhw.", + NMACLHWO: "nmaclhwo", + NMACLHWO_: "nmaclhwo.", + NMACLHWS: "nmaclhws", + NMACLHWS_: "nmaclhws.", + NMACLHWSO: "nmaclhwso", + NMACLHWSO_: "nmaclhwso.", + ICBI: "icbi", + ICBT: "icbt", + DCBA: "dcba", + DCBT: "dcbt", + DCBTST: "dcbtst", + DCBZ: "dcbz", + DCBST: "dcbst", + DCBF: "dcbf", + ISYNC: "isync", + LBARX: "lbarx", + LHARX: "lharx", + LWARX: "lwarx", + STBCX_: "stbcx.", + STHCX_: "sthcx.", + STWCX_: "stwcx.", + LDARX: "ldarx", + STDCX_: "stdcx.", + LQARX: "lqarx", + STQCX_: "stqcx.", + SYNC: "sync", + EIEIO: "eieio", + MBAR: "mbar", + WAIT: "wait", + TBEGIN_: "tbegin.", + TEND_: "tend.", + TABORT_: "tabort.", + TABORTWC_: "tabortwc.", + TABORTWCI_: "tabortwci.", + TABORTDC_: "tabortdc.", + TABORTDCI_: "tabortdci.", + TSR_: "tsr.", + TCHECK: "tcheck", + MFTB: "mftb", + RFEBB: "rfebb", + LBDX: "lbdx", + LHDX: "lhdx", + LWDX: "lwdx", + LDDX: "lddx", + LFDDX: "lfddx", + STBDX: "stbdx", + STHDX: "sthdx", + STWDX: "stwdx", + STDDX: "stddx", + STFDDX: "stfddx", + DSN: "dsn", + ECIWX: "eciwx", + ECOWX: "ecowx", + RFID: "rfid", + HRFID: "hrfid", + DOZE: "doze", + NAP: "nap", + SLEEP: "sleep", + RVWINKLE: "rvwinkle", + LBZCIX: "lbzcix", + LWZCIX: "lwzcix", + LHZCIX: "lhzcix", + LDCIX: "ldcix", + STBCIX: "stbcix", + STWCIX: "stwcix", + STHCIX: "sthcix", + STDCIX: "stdcix", + TRECLAIM_: "treclaim.", + TRECHKPT_: "trechkpt.", + MTMSR: "mtmsr", + MTMSRD: "mtmsrd", + MFMSR: "mfmsr", + SLBIE: "slbie", + SLBIA: "slbia", + SLBMTE: "slbmte", + SLBMFEV: "slbmfev", + SLBMFEE: "slbmfee", + SLBFEE_: "slbfee.", + MTSR: "mtsr", + MTSRIN: "mtsrin", + MFSR: "mfsr", + MFSRIN: "mfsrin", + TLBIE: "tlbie", + TLBIEL: "tlbiel", + TLBIA: "tlbia", + TLBSYNC: "tlbsync", + MSGSND: "msgsnd", + MSGCLR: "msgclr", + MSGSNDP: "msgsndp", + MSGCLRP: "msgclrp", + MTTMR: "mttmr", + RFI: "rfi", + RFCI: "rfci", + RFDI: "rfdi", + RFMCI: "rfmci", + RFGI: "rfgi", + EHPRIV: "ehpriv", + MTDCR: "mtdcr", + MTDCRX: "mtdcrx", + MFDCR: "mfdcr", + MFDCRX: "mfdcrx", + WRTEE: "wrtee", + WRTEEI: "wrteei", + LBEPX: "lbepx", + LHEPX: "lhepx", + LWEPX: "lwepx", + LDEPX: "ldepx", + STBEPX: "stbepx", + STHEPX: "sthepx", + STWEPX: "stwepx", + STDEPX: "stdepx", + DCBSTEP: "dcbstep", + DCBTEP: "dcbtep", + DCBFEP: "dcbfep", + DCBTSTEP: "dcbtstep", + ICBIEP: "icbiep", + DCBZEP: "dcbzep", + LFDEPX: "lfdepx", + STFDEPX: "stfdepx", + EVLDDEPX: "evlddepx", + EVSTDDEPX: "evstddepx", + LVEPX: "lvepx", + LVEPXL: "lvepxl", + STVEPX: "stvepx", + STVEPXL: "stvepxl", + DCBI: "dcbi", + DCBLQ_: "dcblq.", + ICBLQ_: "icblq.", + DCBTLS: "dcbtls", + DCBTSTLS: "dcbtstls", + ICBTLS: "icbtls", + ICBLC: "icblc", + DCBLC: "dcblc", + TLBIVAX: "tlbivax", + TLBILX: "tlbilx", + TLBSX: "tlbsx", + TLBSRX_: "tlbsrx.", + TLBRE: "tlbre", + TLBWE: "tlbwe", + DNH: "dnh", + DCI: "dci", + ICI: "ici", + DCREAD: "dcread", + ICREAD: "icread", + MFPMR: "mfpmr", + MTPMR: "mtpmr", +} + +var ( + ap_Reg_11_15 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{11, 5}}} + ap_Reg_6_10 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{6, 5}}} + ap_PCRel_6_29_shift2 = &argField{Type: TypePCRel, Shift: 2, BitFields: BitFields{{6, 24}}} + ap_Label_6_29_shift2 = &argField{Type: TypeLabel, Shift: 2, BitFields: BitFields{{6, 24}}} + ap_ImmUnsigned_6_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 5}}} + ap_CondRegBit_11_15 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{11, 5}}} + ap_PCRel_16_29_shift2 = &argField{Type: TypePCRel, Shift: 2, BitFields: BitFields{{16, 14}}} + ap_Label_16_29_shift2 = &argField{Type: TypeLabel, Shift: 2, BitFields: BitFields{{16, 14}}} + ap_ImmUnsigned_19_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{19, 2}}} + ap_CondRegBit_6_10 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{6, 5}}} + ap_CondRegBit_16_20 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{16, 5}}} + ap_CondRegField_6_8 = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{6, 3}}} + ap_CondRegField_11_13 = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{11, 3}}} + ap_ImmUnsigned_20_26 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{20, 7}}} + ap_SpReg_11_20 = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{11, 10}}} + ap_Offset_16_31 = &argField{Type: TypeOffset, Shift: 0, BitFields: BitFields{{16, 16}}} + ap_Reg_16_20 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{16, 5}}} + ap_Offset_16_29_shift2 = &argField{Type: TypeOffset, Shift: 2, BitFields: BitFields{{16, 14}}} + ap_Offset_16_27_shift4 = &argField{Type: TypeOffset, Shift: 4, BitFields: BitFields{{16, 12}}} + ap_ImmUnsigned_16_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 5}}} + ap_ImmSigned_16_31 = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{16, 16}}} + ap_ImmUnsigned_16_31 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 16}}} + ap_CondRegBit_21_25 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{21, 5}}} + ap_ImmUnsigned_21_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 5}}} + ap_ImmUnsigned_26_30 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{26, 5}}} + ap_ImmUnsigned_30_30_16_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{30, 1}, {16, 5}}} + ap_ImmUnsigned_26_26_21_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{26, 1}, {21, 5}}} + ap_SpReg_16_20_11_15 = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{16, 5}, {11, 5}}} + ap_ImmUnsigned_12_19 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 8}}} + ap_ImmUnsigned_10_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{10, 1}}} + ap_VecSReg_31_31_6_10 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{31, 1}, {6, 5}}} + ap_FPReg_6_10 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{6, 5}}} + ap_FPReg_16_20 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{16, 5}}} + ap_FPReg_11_15 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{11, 5}}} + ap_FPReg_21_25 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{21, 5}}} + ap_ImmUnsigned_16_19 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 4}}} + ap_ImmUnsigned_15_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{15, 1}}} + ap_ImmUnsigned_7_14 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{7, 8}}} + ap_ImmUnsigned_6_6 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 1}}} + ap_VecReg_6_10 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{6, 5}}} + ap_VecReg_11_15 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{11, 5}}} + ap_VecReg_16_20 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{16, 5}}} + ap_ImmUnsigned_12_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 4}}} + ap_ImmUnsigned_13_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{13, 3}}} + ap_ImmUnsigned_14_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{14, 2}}} + ap_ImmSigned_11_15 = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{11, 5}}} + ap_VecReg_21_25 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{21, 5}}} + ap_ImmUnsigned_22_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 4}}} + ap_ImmUnsigned_11_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 5}}} + ap_ImmUnsigned_16_16 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 1}}} + ap_ImmUnsigned_17_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{17, 4}}} + ap_ImmUnsigned_22_22 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 1}}} + ap_ImmUnsigned_16_21 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 6}}} + ap_ImmUnsigned_21_22 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 2}}} + ap_ImmUnsigned_11_12 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 2}}} + ap_ImmUnsigned_11_11 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 1}}} + ap_VecSReg_30_30_16_20 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{30, 1}, {16, 5}}} + ap_VecSReg_29_29_11_15 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{29, 1}, {11, 5}}} + ap_ImmUnsigned_22_23 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 2}}} + ap_VecSReg_28_28_21_25 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{28, 1}, {21, 5}}} + ap_CondRegField_29_31 = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{29, 3}}} + ap_ImmUnsigned_7_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{7, 4}}} + ap_ImmUnsigned_9_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{9, 2}}} + ap_ImmUnsigned_31_31 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{31, 1}}} + ap_ImmSigned_16_20 = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{16, 5}}} + ap_ImmUnsigned_20_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{20, 1}}} + ap_ImmUnsigned_8_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{8, 3}}} + ap_SpReg_12_15 = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{12, 4}}} + ap_ImmUnsigned_6_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 15}}} + ap_ImmUnsigned_11_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 10}}} +) + +var instFormats = [...]instFormat{ + {CNTLZW, 0xfc0007ff, 0x7c000034, 0xf800, // Count Leading Zeros Word X-form (cntlzw RA, RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {CNTLZW_, 0xfc0007ff, 0x7c000035, 0xf800, // Count Leading Zeros Word X-form (cntlzw. RA, RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {B, 0xfc000003, 0x48000000, 0x0, // Branch I-form (b target_addr) + [5]*argField{ap_PCRel_6_29_shift2}}, + {BA, 0xfc000003, 0x48000002, 0x0, // Branch I-form (ba target_addr) + [5]*argField{ap_Label_6_29_shift2}}, + {BL, 0xfc000003, 0x48000001, 0x0, // Branch I-form (bl target_addr) + [5]*argField{ap_PCRel_6_29_shift2}}, + {BLA, 0xfc000003, 0x48000003, 0x0, // Branch I-form (bla target_addr) + [5]*argField{ap_Label_6_29_shift2}}, + {BC, 0xfc000003, 0x40000000, 0x0, // Branch Conditional B-form (bc BO,BI,target_addr) + [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_PCRel_16_29_shift2}}, + {BCA, 0xfc000003, 0x40000002, 0x0, // Branch Conditional B-form (bca BO,BI,target_addr) + [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_Label_16_29_shift2}}, + {BCL, 0xfc000003, 0x40000001, 0x0, // Branch Conditional B-form (bcl BO,BI,target_addr) + [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_PCRel_16_29_shift2}}, + {BCLA, 0xfc000003, 0x40000003, 0x0, // Branch Conditional B-form (bcla BO,BI,target_addr) + [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_Label_16_29_shift2}}, + {BCLR, 0xfc0007ff, 0x4c000020, 0xe000, // Branch Conditional to Link Register XL-form (bclr BO,BI,BH) + [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, + {BCLRL, 0xfc0007ff, 0x4c000021, 0xe000, // Branch Conditional to Link Register XL-form (bclrl BO,BI,BH) + [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, + {BCCTR, 0xfc0007ff, 0x4c000420, 0xe000, // Branch Conditional to Count Register XL-form (bcctr BO,BI,BH) + [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, + {BCCTRL, 0xfc0007ff, 0x4c000421, 0xe000, // Branch Conditional to Count Register XL-form (bcctrl BO,BI,BH) + [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, + {BCTAR, 0xfc0007ff, 0x4c000460, 0xe000, // Branch Conditional to Branch Target Address Register XL-form (bctar BO,BI,BH) + [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, + {BCTARL, 0xfc0007ff, 0x4c000461, 0xe000, // Branch Conditional to Branch Target Address Register XL-form (bctarl BO,BI,BH) + [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, + {CRAND, 0xfc0007fe, 0x4c000202, 0x1, // Condition Register AND XL-form (crand BT,BA,BB) + [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, + {CROR, 0xfc0007fe, 0x4c000382, 0x1, // Condition Register OR XL-form (cror BT,BA,BB) + [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, + {CRNAND, 0xfc0007fe, 0x4c0001c2, 0x1, // Condition Register NAND XL-form (crnand BT,BA,BB) + [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, + {CRXOR, 0xfc0007fe, 0x4c000182, 0x1, // Condition Register XOR XL-form (crxor BT,BA,BB) + [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, + {CRNOR, 0xfc0007fe, 0x4c000042, 0x1, // Condition Register NOR XL-form (crnor BT,BA,BB) + [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, + {CRANDC, 0xfc0007fe, 0x4c000102, 0x1, // Condition Register AND with Complement XL-form (crandc BT,BA,BB) + [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, + {MCRF, 0xfc0007fe, 0x4c000000, 0x63f801, // Move Condition Register Field XL-form (mcrf BF,BFA) + [5]*argField{ap_CondRegField_6_8, ap_CondRegField_11_13}}, + {CREQV, 0xfc0007fe, 0x4c000242, 0x1, // Condition Register Equivalent XL-form (creqv BT,BA,BB) + [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, + {CRORC, 0xfc0007fe, 0x4c000342, 0x1, // Condition Register OR with Complement XL-form (crorc BT,BA,BB) + [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, + {SC, 0xfc000002, 0x44000002, 0x3fff01d, // System Call SC-form (sc LEV) + [5]*argField{ap_ImmUnsigned_20_26}}, + {CLRBHRB, 0xfc0007fe, 0x7c00035c, 0x3fff801, // Clear BHRB X-form (clrbhrb) + [5]*argField{}}, + {MFBHRBE, 0xfc0007fe, 0x7c00025c, 0x1, // Move From Branch History Rolling Buffer XFX-form (mfbhrbe RT,BHRBE) + [5]*argField{ap_Reg_6_10, ap_SpReg_11_20}}, + {LBZ, 0xfc000000, 0x88000000, 0x0, // Load Byte and Zero D-form (lbz RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LBZU, 0xfc000000, 0x8c000000, 0x0, // Load Byte and Zero with Update D-form (lbzu RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LBZX, 0xfc0007fe, 0x7c0000ae, 0x1, // Load Byte and Zero Indexed X-form (lbzx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LBZUX, 0xfc0007fe, 0x7c0000ee, 0x1, // Load Byte and Zero with Update Indexed X-form (lbzux RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LHZ, 0xfc000000, 0xa0000000, 0x0, // Load Halfword and Zero D-form (lhz RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LHZU, 0xfc000000, 0xa4000000, 0x0, // Load Halfword and Zero with Update D-form (lhzu RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LHZX, 0xfc0007fe, 0x7c00022e, 0x1, // Load Halfword and Zero Indexed X-form (lhzx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LHZUX, 0xfc0007fe, 0x7c00026e, 0x1, // Load Halfword and Zero with Update Indexed X-form (lhzux RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LHA, 0xfc000000, 0xa8000000, 0x0, // Load Halfword Algebraic D-form (lha RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LHAU, 0xfc000000, 0xac000000, 0x0, // Load Halfword Algebraic with Update D-form (lhau RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LHAX, 0xfc0007fe, 0x7c0002ae, 0x1, // Load Halfword Algebraic Indexed X-form (lhax RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LHAUX, 0xfc0007fe, 0x7c0002ee, 0x1, // Load Halfword Algebraic with Update Indexed X-form (lhaux RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LWZ, 0xfc000000, 0x80000000, 0x0, // Load Word and Zero D-form (lwz RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LWZU, 0xfc000000, 0x84000000, 0x0, // Load Word and Zero with Update D-form (lwzu RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LWZX, 0xfc0007fe, 0x7c00002e, 0x1, // Load Word and Zero Indexed X-form (lwzx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LWZUX, 0xfc0007fe, 0x7c00006e, 0x1, // Load Word and Zero with Update Indexed X-form (lwzux RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LWA, 0xfc000003, 0xe8000002, 0x0, // Load Word Algebraic DS-form (lwa RT,DS(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, + {LWAX, 0xfc0007fe, 0x7c0002aa, 0x1, // Load Word Algebraic Indexed X-form (lwax RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LWAUX, 0xfc0007fe, 0x7c0002ea, 0x1, // Load Word Algebraic with Update Indexed X-form (lwaux RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LD, 0xfc000003, 0xe8000000, 0x0, // Load Doubleword DS-form (ld RT,DS(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, + {LDU, 0xfc000003, 0xe8000001, 0x0, // Load Doubleword with Update DS-form (ldu RT,DS(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, + {LDX, 0xfc0007fe, 0x7c00002a, 0x1, // Load Doubleword Indexed X-form (ldx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LDUX, 0xfc0007fe, 0x7c00006a, 0x1, // Load Doubleword with Update Indexed X-form (ldux RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STB, 0xfc000000, 0x98000000, 0x0, // Store Byte D-form (stb RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {STBU, 0xfc000000, 0x9c000000, 0x0, // Store Byte with Update D-form (stbu RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {STBX, 0xfc0007fe, 0x7c0001ae, 0x1, // Store Byte Indexed X-form (stbx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STBUX, 0xfc0007fe, 0x7c0001ee, 0x1, // Store Byte with Update Indexed X-form (stbux RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STH, 0xfc000000, 0xb0000000, 0x0, // Store Halfword D-form (sth RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {STHU, 0xfc000000, 0xb4000000, 0x0, // Store Halfword with Update D-form (sthu RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {STHX, 0xfc0007fe, 0x7c00032e, 0x1, // Store Halfword Indexed X-form (sthx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STHUX, 0xfc0007fe, 0x7c00036e, 0x1, // Store Halfword with Update Indexed X-form (sthux RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STW, 0xfc000000, 0x90000000, 0x0, // Store Word D-form (stw RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {STWU, 0xfc000000, 0x94000000, 0x0, // Store Word with Update D-form (stwu RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {STWX, 0xfc0007fe, 0x7c00012e, 0x1, // Store Word Indexed X-form (stwx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STWUX, 0xfc0007fe, 0x7c00016e, 0x1, // Store Word with Update Indexed X-form (stwux RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STD, 0xfc000003, 0xf8000000, 0x0, // Store Doubleword DS-form (std RS,DS(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, + {STDU, 0xfc000003, 0xf8000001, 0x0, // Store Doubleword with Update DS-form (stdu RS,DS(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, + {STDX, 0xfc0007fe, 0x7c00012a, 0x1, // Store Doubleword Indexed X-form (stdx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STDUX, 0xfc0007fe, 0x7c00016a, 0x1, // Store Doubleword with Update Indexed X-form (stdux RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LQ, 0xfc000000, 0xe0000000, 0xf, // Load Quadword DQ-form (lq RTp,DQ(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}}, + {STQ, 0xfc000003, 0xf8000002, 0x0, // Store Quadword DS-form (stq RSp,DS(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, + {LHBRX, 0xfc0007fe, 0x7c00062c, 0x1, // Load Halfword Byte-Reverse Indexed X-form (lhbrx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LWBRX, 0xfc0007fe, 0x7c00042c, 0x1, // Load Word Byte-Reverse Indexed X-form (lwbrx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STHBRX, 0xfc0007fe, 0x7c00072c, 0x1, // Store Halfword Byte-Reverse Indexed X-form (sthbrx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STWBRX, 0xfc0007fe, 0x7c00052c, 0x1, // Store Word Byte-Reverse Indexed X-form (stwbrx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LDBRX, 0xfc0007fe, 0x7c000428, 0x1, // Load Doubleword Byte-Reverse Indexed X-form (ldbrx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STDBRX, 0xfc0007fe, 0x7c000528, 0x1, // Store Doubleword Byte-Reverse Indexed X-form (stdbrx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LMW, 0xfc000000, 0xb8000000, 0x0, // Load Multiple Word D-form (lmw RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {STMW, 0xfc000000, 0xbc000000, 0x0, // Store Multiple Word D-form (stmw RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LSWI, 0xfc0007fe, 0x7c0004aa, 0x1, // Load String Word Immediate X-form (lswi RT,RA,NB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, + {LSWX, 0xfc0007fe, 0x7c00042a, 0x1, // Load String Word Indexed X-form (lswx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STSWI, 0xfc0007fe, 0x7c0005aa, 0x1, // Store String Word Immediate X-form (stswi RS,RA,NB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, + {STSWX, 0xfc0007fe, 0x7c00052a, 0x1, // Store String Word Indexed X-form (stswx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LI, 0xfc1f0000, 0x38000000, 0x0, // Add Immediate D-form (li RT,SI) + [5]*argField{ap_Reg_6_10, ap_ImmSigned_16_31}}, + {ADDI, 0xfc000000, 0x38000000, 0x0, // Add Immediate D-form (addi RT,RA,SI) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, + {LIS, 0xfc1f0000, 0x3c000000, 0x0, // Add Immediate Shifted D-form (lis RT, SI) + [5]*argField{ap_Reg_6_10, ap_ImmSigned_16_31}}, + {ADDIS, 0xfc000000, 0x3c000000, 0x0, // Add Immediate Shifted D-form (addis RT,RA,SI) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, + {ADD, 0xfc0007ff, 0x7c000214, 0x0, // Add XO-form (add RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADD_, 0xfc0007ff, 0x7c000215, 0x0, // Add XO-form (add. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDO, 0xfc0007ff, 0x7c000614, 0x0, // Add XO-form (addo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDO_, 0xfc0007ff, 0x7c000615, 0x0, // Add XO-form (addo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDIC, 0xfc000000, 0x30000000, 0x0, // Add Immediate Carrying D-form (addic RT,RA,SI) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, + {SUBF, 0xfc0007ff, 0x7c000050, 0x0, // Subtract From XO-form (subf RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SUBF_, 0xfc0007ff, 0x7c000051, 0x0, // Subtract From XO-form (subf. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SUBFO, 0xfc0007ff, 0x7c000450, 0x0, // Subtract From XO-form (subfo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SUBFO_, 0xfc0007ff, 0x7c000451, 0x0, // Subtract From XO-form (subfo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDIC_, 0xfc000000, 0x34000000, 0x0, // Add Immediate Carrying and Record D-form (addic. RT,RA,SI) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, + {SUBFIC, 0xfc000000, 0x20000000, 0x0, // Subtract From Immediate Carrying D-form (subfic RT,RA,SI) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, + {ADDC, 0xfc0007ff, 0x7c000014, 0x0, // Add Carrying XO-form (addc RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDC_, 0xfc0007ff, 0x7c000015, 0x0, // Add Carrying XO-form (addc. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDCO, 0xfc0007ff, 0x7c000414, 0x0, // Add Carrying XO-form (addco RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDCO_, 0xfc0007ff, 0x7c000415, 0x0, // Add Carrying XO-form (addco. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SUBFC, 0xfc0007ff, 0x7c000010, 0x0, // Subtract From Carrying XO-form (subfc RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SUBFC_, 0xfc0007ff, 0x7c000011, 0x0, // Subtract From Carrying XO-form (subfc. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SUBFCO, 0xfc0007ff, 0x7c000410, 0x0, // Subtract From Carrying XO-form (subfco RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SUBFCO_, 0xfc0007ff, 0x7c000411, 0x0, // Subtract From Carrying XO-form (subfco. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDE, 0xfc0007ff, 0x7c000114, 0x0, // Add Extended XO-form (adde RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDE_, 0xfc0007ff, 0x7c000115, 0x0, // Add Extended XO-form (adde. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDEO, 0xfc0007ff, 0x7c000514, 0x0, // Add Extended XO-form (addeo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDEO_, 0xfc0007ff, 0x7c000515, 0x0, // Add Extended XO-form (addeo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ADDME, 0xfc0007ff, 0x7c0001d4, 0xf800, // Add to Minus One Extended XO-form (addme RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {ADDME_, 0xfc0007ff, 0x7c0001d5, 0xf800, // Add to Minus One Extended XO-form (addme. RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {ADDMEO, 0xfc0007ff, 0x7c0005d4, 0xf800, // Add to Minus One Extended XO-form (addmeo RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {ADDMEO_, 0xfc0007ff, 0x7c0005d5, 0xf800, // Add to Minus One Extended XO-form (addmeo. RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {SUBFE, 0xfc0007ff, 0x7c000110, 0x0, // Subtract From Extended XO-form (subfe RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SUBFE_, 0xfc0007ff, 0x7c000111, 0x0, // Subtract From Extended XO-form (subfe. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SUBFEO, 0xfc0007ff, 0x7c000510, 0x0, // Subtract From Extended XO-form (subfeo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SUBFEO_, 0xfc0007ff, 0x7c000511, 0x0, // Subtract From Extended XO-form (subfeo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SUBFME, 0xfc0007ff, 0x7c0001d0, 0xf800, // Subtract From Minus One Extended XO-form (subfme RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {SUBFME_, 0xfc0007ff, 0x7c0001d1, 0xf800, // Subtract From Minus One Extended XO-form (subfme. RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {SUBFMEO, 0xfc0007ff, 0x7c0005d0, 0xf800, // Subtract From Minus One Extended XO-form (subfmeo RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {SUBFMEO_, 0xfc0007ff, 0x7c0005d1, 0xf800, // Subtract From Minus One Extended XO-form (subfmeo. RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {ADDZE, 0xfc0007ff, 0x7c000194, 0xf800, // Add to Zero Extended XO-form (addze RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {ADDZE_, 0xfc0007ff, 0x7c000195, 0xf800, // Add to Zero Extended XO-form (addze. RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {ADDZEO, 0xfc0007ff, 0x7c000594, 0xf800, // Add to Zero Extended XO-form (addzeo RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {ADDZEO_, 0xfc0007ff, 0x7c000595, 0xf800, // Add to Zero Extended XO-form (addzeo. RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {SUBFZE, 0xfc0007ff, 0x7c000190, 0xf800, // Subtract From Zero Extended XO-form (subfze RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {SUBFZE_, 0xfc0007ff, 0x7c000191, 0xf800, // Subtract From Zero Extended XO-form (subfze. RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {SUBFZEO, 0xfc0007ff, 0x7c000590, 0xf800, // Subtract From Zero Extended XO-form (subfzeo RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {SUBFZEO_, 0xfc0007ff, 0x7c000591, 0xf800, // Subtract From Zero Extended XO-form (subfzeo. RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {NEG, 0xfc0007ff, 0x7c0000d0, 0xf800, // Negate XO-form (neg RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {NEG_, 0xfc0007ff, 0x7c0000d1, 0xf800, // Negate XO-form (neg. RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {NEGO, 0xfc0007ff, 0x7c0004d0, 0xf800, // Negate XO-form (nego RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {NEGO_, 0xfc0007ff, 0x7c0004d1, 0xf800, // Negate XO-form (nego. RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {MULLI, 0xfc000000, 0x1c000000, 0x0, // Multiply Low Immediate D-form (mulli RT,RA,SI) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, + {MULLW, 0xfc0007ff, 0x7c0001d6, 0x0, // Multiply Low Word XO-form (mullw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULLW_, 0xfc0007ff, 0x7c0001d7, 0x0, // Multiply Low Word XO-form (mullw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULLWO, 0xfc0007ff, 0x7c0005d6, 0x0, // Multiply Low Word XO-form (mullwo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULLWO_, 0xfc0007ff, 0x7c0005d7, 0x0, // Multiply Low Word XO-form (mullwo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHW, 0xfc0003ff, 0x7c000096, 0x400, // Multiply High Word XO-form (mulhw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHW_, 0xfc0003ff, 0x7c000097, 0x400, // Multiply High Word XO-form (mulhw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHWU, 0xfc0003ff, 0x7c000016, 0x400, // Multiply High Word Unsigned XO-form (mulhwu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHWU_, 0xfc0003ff, 0x7c000017, 0x400, // Multiply High Word Unsigned XO-form (mulhwu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVW, 0xfc0007ff, 0x7c0003d6, 0x0, // Divide Word XO-form (divw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVW_, 0xfc0007ff, 0x7c0003d7, 0x0, // Divide Word XO-form (divw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWO, 0xfc0007ff, 0x7c0007d6, 0x0, // Divide Word XO-form (divwo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWO_, 0xfc0007ff, 0x7c0007d7, 0x0, // Divide Word XO-form (divwo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWU, 0xfc0007ff, 0x7c000396, 0x0, // Divide Word Unsigned XO-form (divwu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWU_, 0xfc0007ff, 0x7c000397, 0x0, // Divide Word Unsigned XO-form (divwu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWUO, 0xfc0007ff, 0x7c000796, 0x0, // Divide Word Unsigned XO-form (divwuo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWUO_, 0xfc0007ff, 0x7c000797, 0x0, // Divide Word Unsigned XO-form (divwuo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWE, 0xfc0007ff, 0x7c000356, 0x0, // Divide Word Extended XO-form (divwe RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWE_, 0xfc0007ff, 0x7c000357, 0x0, // Divide Word Extended XO-form (divwe. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWEO, 0xfc0007ff, 0x7c000756, 0x0, // Divide Word Extended XO-form (divweo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWEO_, 0xfc0007ff, 0x7c000757, 0x0, // Divide Word Extended XO-form (divweo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWEU, 0xfc0007ff, 0x7c000316, 0x0, // Divide Word Extended Unsigned XO-form (divweu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWEU_, 0xfc0007ff, 0x7c000317, 0x0, // Divide Word Extended Unsigned XO-form (divweu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWEUO, 0xfc0007ff, 0x7c000716, 0x0, // Divide Word Extended Unsigned XO-form (divweuo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVWEUO_, 0xfc0007ff, 0x7c000717, 0x0, // Divide Word Extended Unsigned XO-form (divweuo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULLD, 0xfc0007ff, 0x7c0001d2, 0x0, // Multiply Low Doubleword XO-form (mulld RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULLD_, 0xfc0007ff, 0x7c0001d3, 0x0, // Multiply Low Doubleword XO-form (mulld. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULLDO, 0xfc0007ff, 0x7c0005d2, 0x0, // Multiply Low Doubleword XO-form (mulldo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULLDO_, 0xfc0007ff, 0x7c0005d3, 0x0, // Multiply Low Doubleword XO-form (mulldo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHDU, 0xfc0003ff, 0x7c000012, 0x400, // Multiply High Doubleword Unsigned XO-form (mulhdu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHDU_, 0xfc0003ff, 0x7c000013, 0x400, // Multiply High Doubleword Unsigned XO-form (mulhdu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHD, 0xfc0003ff, 0x7c000092, 0x400, // Multiply High Doubleword XO-form (mulhd RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHD_, 0xfc0003ff, 0x7c000093, 0x400, // Multiply High Doubleword XO-form (mulhd. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVD, 0xfc0007ff, 0x7c0003d2, 0x0, // Divide Doubleword XO-form (divd RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVD_, 0xfc0007ff, 0x7c0003d3, 0x0, // Divide Doubleword XO-form (divd. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDO, 0xfc0007ff, 0x7c0007d2, 0x0, // Divide Doubleword XO-form (divdo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDO_, 0xfc0007ff, 0x7c0007d3, 0x0, // Divide Doubleword XO-form (divdo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDU, 0xfc0007ff, 0x7c000392, 0x0, // Divide Doubleword Unsigned XO-form (divdu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDU_, 0xfc0007ff, 0x7c000393, 0x0, // Divide Doubleword Unsigned XO-form (divdu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDUO, 0xfc0007ff, 0x7c000792, 0x0, // Divide Doubleword Unsigned XO-form (divduo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDUO_, 0xfc0007ff, 0x7c000793, 0x0, // Divide Doubleword Unsigned XO-form (divduo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDE, 0xfc0007ff, 0x7c000352, 0x0, // Divide Doubleword Extended XO-form (divde RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDE_, 0xfc0007ff, 0x7c000353, 0x0, // Divide Doubleword Extended XO-form (divde. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDEO, 0xfc0007ff, 0x7c000752, 0x0, // Divide Doubleword Extended XO-form (divdeo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDEO_, 0xfc0007ff, 0x7c000753, 0x0, // Divide Doubleword Extended XO-form (divdeo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDEU, 0xfc0007ff, 0x7c000312, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDEU_, 0xfc0007ff, 0x7c000313, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDEUO, 0xfc0007ff, 0x7c000712, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DIVDEUO_, 0xfc0007ff, 0x7c000713, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {CMPWI, 0xfc200000, 0x2c000000, 0x400000, // Compare Immediate D-form (cmpwi BF,RA,SI) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}}, + {CMPDI, 0xfc200000, 0x2c200000, 0x400000, // Compare Immediate D-form (cmpdi BF,RA,SI) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}}, + {CMPW, 0xfc2007fe, 0x7c000000, 0x400001, // Compare X-form (cmpw BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {CMPD, 0xfc2007fe, 0x7c200000, 0x400001, // Compare X-form (cmpd BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {CMPLWI, 0xfc200000, 0x28000000, 0x400000, // Compare Logical Immediate D-form (cmplwi BF,RA,UI) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmUnsigned_16_31}}, + {CMPLDI, 0xfc200000, 0x28200000, 0x400000, // Compare Logical Immediate D-form (cmpldi BF,RA,UI) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmUnsigned_16_31}}, + {CMPLW, 0xfc2007fe, 0x7c000040, 0x400001, // Compare Logical X-form (cmplw BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {CMPLD, 0xfc2007fe, 0x7c200040, 0x400001, // Compare Logical X-form (cmpld BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {TWI, 0xfc000000, 0xc000000, 0x0, // Trap Word Immediate D-form (twi TO,RA,SI) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, + {TW, 0xfc0007fe, 0x7c000008, 0x1, // Trap Word X-form (tw TO,RA,RB) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {TDI, 0xfc000000, 0x8000000, 0x0, // Trap Doubleword Immediate D-form (tdi TO,RA,SI) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, + {ISEL, 0xfc00003e, 0x7c00001e, 0x1, // Integer Select A-form (isel RT,RA,RB,BC) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_CondRegBit_21_25}}, + {TD, 0xfc0007fe, 0x7c000088, 0x1, // Trap Doubleword X-form (td TO,RA,RB) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ANDI_, 0xfc000000, 0x70000000, 0x0, // AND Immediate D-form (andi. RA,RS,UI) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, + {ANDIS_, 0xfc000000, 0x74000000, 0x0, // AND Immediate Shifted D-form (andis. RA,RS,UI) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, + {ORI, 0xfc000000, 0x60000000, 0x0, // OR Immediate D-form (ori RA,RS,UI) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, + {ORIS, 0xfc000000, 0x64000000, 0x0, // OR Immediate Shifted D-form (oris RA,RS,UI) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, + {XORI, 0xfc000000, 0x68000000, 0x0, // XOR Immediate D-form (xori RA,RS,UI) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, + {XORIS, 0xfc000000, 0x6c000000, 0x0, // XOR Immediate Shifted D-form (xoris RA,RS,UI) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, + {AND, 0xfc0007ff, 0x7c000038, 0x0, // AND X-form (and RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {AND_, 0xfc0007ff, 0x7c000039, 0x0, // AND X-form (and. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {XOR, 0xfc0007ff, 0x7c000278, 0x0, // XOR X-form (xor RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {XOR_, 0xfc0007ff, 0x7c000279, 0x0, // XOR X-form (xor. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {NAND, 0xfc0007ff, 0x7c0003b8, 0x0, // NAND X-form (nand RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {NAND_, 0xfc0007ff, 0x7c0003b9, 0x0, // NAND X-form (nand. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {OR, 0xfc0007ff, 0x7c000378, 0x0, // OR X-form (or RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {OR_, 0xfc0007ff, 0x7c000379, 0x0, // OR X-form (or. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {NOR, 0xfc0007ff, 0x7c0000f8, 0x0, // NOR X-form (nor RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {NOR_, 0xfc0007ff, 0x7c0000f9, 0x0, // NOR X-form (nor. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {ANDC, 0xfc0007ff, 0x7c000078, 0x0, // AND with Complement X-form (andc RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {ANDC_, 0xfc0007ff, 0x7c000079, 0x0, // AND with Complement X-form (andc. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {EXTSB, 0xfc0007ff, 0x7c000774, 0xf800, // Extend Sign Byte X-form (extsb RA,RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {EXTSB_, 0xfc0007ff, 0x7c000775, 0xf800, // Extend Sign Byte X-form (extsb. RA,RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {EQV, 0xfc0007ff, 0x7c000238, 0x0, // Equivalent X-form (eqv RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {EQV_, 0xfc0007ff, 0x7c000239, 0x0, // Equivalent X-form (eqv. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {ORC, 0xfc0007ff, 0x7c000338, 0x0, // OR with Complement X-form (orc RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {ORC_, 0xfc0007ff, 0x7c000339, 0x0, // OR with Complement X-form (orc. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {EXTSH, 0xfc0007ff, 0x7c000734, 0xf800, // Extend Sign Halfword X-form (extsh RA,RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {EXTSH_, 0xfc0007ff, 0x7c000735, 0xf800, // Extend Sign Halfword X-form (extsh. RA,RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {CMPB, 0xfc0007fe, 0x7c0003f8, 0x1, // Compare Bytes X-form (cmpb RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {POPCNTB, 0xfc0007fe, 0x7c0000f4, 0xf801, // Population Count Bytes X-form (popcntb RA, RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {POPCNTW, 0xfc0007fe, 0x7c0002f4, 0xf801, // Population Count Words X-form (popcntw RA, RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {PRTYD, 0xfc0007fe, 0x7c000174, 0xf801, // Parity Doubleword X-form (prtyd RA,RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {PRTYW, 0xfc0007fe, 0x7c000134, 0xf801, // Parity Word X-form (prtyw RA,RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {EXTSW, 0xfc0007ff, 0x7c0007b4, 0xf800, // Extend Sign Word X-form (extsw RA,RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {EXTSW_, 0xfc0007ff, 0x7c0007b5, 0xf800, // Extend Sign Word X-form (extsw. RA,RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {CNTLZD, 0xfc0007ff, 0x7c000074, 0xf800, // Count Leading Zeros Doubleword X-form (cntlzd RA,RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {CNTLZD_, 0xfc0007ff, 0x7c000075, 0xf800, // Count Leading Zeros Doubleword X-form (cntlzd. RA,RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {POPCNTD, 0xfc0007fe, 0x7c0003f4, 0xf801, // Population Count Doubleword X-form (popcntd RA, RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {BPERMD, 0xfc0007fe, 0x7c0001f8, 0x1, // Bit Permute Doubleword X-form (bpermd RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {RLWINM, 0xfc000001, 0x54000000, 0x0, // Rotate Left Word Immediate then AND with Mask M-form (rlwinm RA,RS,SH,MB,ME) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, + {RLWINM_, 0xfc000001, 0x54000001, 0x0, // Rotate Left Word Immediate then AND with Mask M-form (rlwinm. RA,RS,SH,MB,ME) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, + {RLWNM, 0xfc000001, 0x5c000000, 0x0, // Rotate Left Word then AND with Mask M-form (rlwnm RA,RS,RB,MB,ME) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, + {RLWNM_, 0xfc000001, 0x5c000001, 0x0, // Rotate Left Word then AND with Mask M-form (rlwnm. RA,RS,RB,MB,ME) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, + {RLWIMI, 0xfc000001, 0x50000000, 0x0, // Rotate Left Word Immediate then Mask Insert M-form (rlwimi RA,RS,SH,MB,ME) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, + {RLWIMI_, 0xfc000001, 0x50000001, 0x0, // Rotate Left Word Immediate then Mask Insert M-form (rlwimi. RA,RS,SH,MB,ME) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, + {RLDICL, 0xfc00001d, 0x78000000, 0x0, // Rotate Left Doubleword Immediate then Clear Left MD-form (rldicl RA,RS,SH,MB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, + {RLDICL_, 0xfc00001d, 0x78000001, 0x0, // Rotate Left Doubleword Immediate then Clear Left MD-form (rldicl. RA,RS,SH,MB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, + {RLDICR, 0xfc00001d, 0x78000004, 0x0, // Rotate Left Doubleword Immediate then Clear Right MD-form (rldicr RA,RS,SH,ME) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, + {RLDICR_, 0xfc00001d, 0x78000005, 0x0, // Rotate Left Doubleword Immediate then Clear Right MD-form (rldicr. RA,RS,SH,ME) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, + {RLDIC, 0xfc00001d, 0x78000008, 0x0, // Rotate Left Doubleword Immediate then Clear MD-form (rldic RA,RS,SH,MB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, + {RLDIC_, 0xfc00001d, 0x78000009, 0x0, // Rotate Left Doubleword Immediate then Clear MD-form (rldic. RA,RS,SH,MB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, + {RLDCL, 0xfc00001f, 0x78000010, 0x0, // Rotate Left Doubleword then Clear Left MDS-form (rldcl RA,RS,RB,MB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}}, + {RLDCL_, 0xfc00001f, 0x78000011, 0x0, // Rotate Left Doubleword then Clear Left MDS-form (rldcl. RA,RS,RB,MB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}}, + {RLDCR, 0xfc00001f, 0x78000012, 0x0, // Rotate Left Doubleword then Clear Right MDS-form (rldcr RA,RS,RB,ME) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}}, + {RLDCR_, 0xfc00001f, 0x78000013, 0x0, // Rotate Left Doubleword then Clear Right MDS-form (rldcr. RA,RS,RB,ME) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}}, + {RLDIMI, 0xfc00001d, 0x7800000c, 0x0, // Rotate Left Doubleword Immediate then Mask Insert MD-form (rldimi RA,RS,SH,MB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, + {RLDIMI_, 0xfc00001d, 0x7800000d, 0x0, // Rotate Left Doubleword Immediate then Mask Insert MD-form (rldimi. RA,RS,SH,MB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, + {SLW, 0xfc0007ff, 0x7c000030, 0x0, // Shift Left Word X-form (slw RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {SLW_, 0xfc0007ff, 0x7c000031, 0x0, // Shift Left Word X-form (slw. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {SRW, 0xfc0007ff, 0x7c000430, 0x0, // Shift Right Word X-form (srw RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {SRW_, 0xfc0007ff, 0x7c000431, 0x0, // Shift Right Word X-form (srw. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {SRAWI, 0xfc0007ff, 0x7c000670, 0x0, // Shift Right Algebraic Word Immediate X-form (srawi RA,RS,SH) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}}, + {SRAWI_, 0xfc0007ff, 0x7c000671, 0x0, // Shift Right Algebraic Word Immediate X-form (srawi. RA,RS,SH) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}}, + {SRAW, 0xfc0007ff, 0x7c000630, 0x0, // Shift Right Algebraic Word X-form (sraw RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {SRAW_, 0xfc0007ff, 0x7c000631, 0x0, // Shift Right Algebraic Word X-form (sraw. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {SLD, 0xfc0007ff, 0x7c000036, 0x0, // Shift Left Doubleword X-form (sld RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {SLD_, 0xfc0007ff, 0x7c000037, 0x0, // Shift Left Doubleword X-form (sld. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {SRD, 0xfc0007ff, 0x7c000436, 0x0, // Shift Right Doubleword X-form (srd RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {SRD_, 0xfc0007ff, 0x7c000437, 0x0, // Shift Right Doubleword X-form (srd. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {SRADI, 0xfc0007fd, 0x7c000674, 0x0, // Shift Right Algebraic Doubleword Immediate XS-form (sradi RA,RS,SH) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}}, + {SRADI_, 0xfc0007fd, 0x7c000675, 0x0, // Shift Right Algebraic Doubleword Immediate XS-form (sradi. RA,RS,SH) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}}, + {SRAD, 0xfc0007ff, 0x7c000634, 0x0, // Shift Right Algebraic Doubleword X-form (srad RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {SRAD_, 0xfc0007ff, 0x7c000635, 0x0, // Shift Right Algebraic Doubleword X-form (srad. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {CDTBCD, 0xfc0007fe, 0x7c000234, 0xf801, // Convert Declets To Binary Coded Decimal X-form (cdtbcd RA, RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {CBCDTD, 0xfc0007fe, 0x7c000274, 0xf801, // Convert Binary Coded Decimal To Declets X-form (cbcdtd RA, RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {ADDG6S, 0xfc0003fe, 0x7c000094, 0x401, // Add and Generate Sixes XO-form (addg6s RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MTSPR, 0xfc0007fe, 0x7c0003a6, 0x1, // Move To Special Purpose Register XFX-form (mtspr SPR,RS) + [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}}, + {MFSPR, 0xfc0007fe, 0x7c0002a6, 0x1, // Move From Special Purpose Register XFX-form (mfspr RT,SPR) + [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}}, + {MTCRF, 0xfc1007fe, 0x7c000120, 0x801, // Move To Condition Register Fields XFX-form (mtcrf FXM,RS) + [5]*argField{ap_ImmUnsigned_12_19, ap_Reg_6_10}}, + {MFCR, 0xfc1007fe, 0x7c000026, 0xff801, // Move From Condition Register XFX-form (mfcr RT) + [5]*argField{ap_Reg_6_10}}, + {MTSLE, 0xfc0007fe, 0x7c000126, 0x3dff801, // Move To Split Little Endian X-form (mtsle L) + [5]*argField{ap_ImmUnsigned_10_10}}, + {MFVSRD, 0xfc0007fe, 0x7c000066, 0xf800, // Move From VSR Doubleword XX1-form (mfvsrd RA,XS) + [5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}}, + {MFVSRWZ, 0xfc0007fe, 0x7c0000e6, 0xf800, // Move From VSR Word and Zero XX1-form (mfvsrwz RA,XS) + [5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}}, + {MTVSRD, 0xfc0007fe, 0x7c000166, 0xf800, // Move To VSR Doubleword XX1-form (mtvsrd XT,RA) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}}, + {MTVSRWA, 0xfc0007fe, 0x7c0001a6, 0xf800, // Move To VSR Word Algebraic XX1-form (mtvsrwa XT,RA) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}}, + {MTVSRWZ, 0xfc0007fe, 0x7c0001e6, 0xf800, // Move To VSR Word and Zero XX1-form (mtvsrwz XT,RA) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}}, + {MTOCRF, 0xfc1007fe, 0x7c100120, 0x801, // Move To One Condition Register Field XFX-form (mtocrf FXM,RS) + [5]*argField{ap_ImmUnsigned_12_19, ap_Reg_6_10}}, + {MFOCRF, 0xfc1007fe, 0x7c100026, 0x801, // Move From One Condition Register Field XFX-form (mfocrf RT,FXM) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_12_19}}, + {MCRXR, 0xfc0007fe, 0x7c000400, 0x7ff801, // Move to Condition Register from XER X-form (mcrxr BF) + [5]*argField{ap_CondRegField_6_8}}, + {MTDCRUX, 0xfc0007fe, 0x7c000346, 0xf801, // Move To Device Control Register User-mode Indexed X-form (mtdcrux RS,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {MFDCRUX, 0xfc0007fe, 0x7c000246, 0xf801, // Move From Device Control Register User-mode Indexed X-form (mfdcrux RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {LFS, 0xfc000000, 0xc0000000, 0x0, // Load Floating-Point Single D-form (lfs FRT,D(RA)) + [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LFSU, 0xfc000000, 0xc4000000, 0x0, // Load Floating-Point Single with Update D-form (lfsu FRT,D(RA)) + [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LFSX, 0xfc0007fe, 0x7c00042e, 0x1, // Load Floating-Point Single Indexed X-form (lfsx FRT,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LFSUX, 0xfc0007fe, 0x7c00046e, 0x1, // Load Floating-Point Single with Update Indexed X-form (lfsux FRT,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LFD, 0xfc000000, 0xc8000000, 0x0, // Load Floating-Point Double D-form (lfd FRT,D(RA)) + [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LFDU, 0xfc000000, 0xcc000000, 0x0, // Load Floating-Point Double with Update D-form (lfdu FRT,D(RA)) + [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {LFDX, 0xfc0007fe, 0x7c0004ae, 0x1, // Load Floating-Point Double Indexed X-form (lfdx FRT,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LFDUX, 0xfc0007fe, 0x7c0004ee, 0x1, // Load Floating-Point Double with Update Indexed X-form (lfdux FRT,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LFIWAX, 0xfc0007fe, 0x7c0006ae, 0x1, // Load Floating-Point as Integer Word Algebraic Indexed X-form (lfiwax FRT,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LFIWZX, 0xfc0007fe, 0x7c0006ee, 0x1, // Load Floating-Point as Integer Word and Zero Indexed X-form (lfiwzx FRT,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STFS, 0xfc000000, 0xd0000000, 0x0, // Store Floating-Point Single D-form (stfs FRS,D(RA)) + [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {STFSU, 0xfc000000, 0xd4000000, 0x0, // Store Floating-Point Single with Update D-form (stfsu FRS,D(RA)) + [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {STFSX, 0xfc0007fe, 0x7c00052e, 0x1, // Store Floating-Point Single Indexed X-form (stfsx FRS,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STFSUX, 0xfc0007fe, 0x7c00056e, 0x1, // Store Floating-Point Single with Update Indexed X-form (stfsux FRS,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STFD, 0xfc000000, 0xd8000000, 0x0, // Store Floating-Point Double D-form (stfd FRS,D(RA)) + [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {STFDU, 0xfc000000, 0xdc000000, 0x0, // Store Floating-Point Double with Update D-form (stfdu FRS,D(RA)) + [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, + {STFDX, 0xfc0007fe, 0x7c0005ae, 0x1, // Store Floating-Point Double Indexed X-form (stfdx FRS,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STFDUX, 0xfc0007fe, 0x7c0005ee, 0x1, // Store Floating-Point Double with Update Indexed X-form (stfdux FRS,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STFIWX, 0xfc0007fe, 0x7c0007ae, 0x1, // Store Floating-Point as Integer Word Indexed X-form (stfiwx FRS,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LFDP, 0xfc000003, 0xe4000000, 0x0, // Load Floating-Point Double Pair DS-form (lfdp FRTp,DS(RA)) + [5]*argField{ap_FPReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, + {LFDPX, 0xfc0007fe, 0x7c00062e, 0x1, // Load Floating-Point Double Pair Indexed X-form (lfdpx FRTp,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STFDP, 0xfc000003, 0xf4000000, 0x0, // Store Floating-Point Double Pair DS-form (stfdp FRSp,DS(RA)) + [5]*argField{ap_FPReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, + {STFDPX, 0xfc0007fe, 0x7c00072e, 0x1, // Store Floating-Point Double Pair Indexed X-form (stfdpx FRSp,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {FMR, 0xfc0007ff, 0xfc000090, 0x1f0000, // Floating Move Register X-form (fmr FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FMR_, 0xfc0007ff, 0xfc000091, 0x1f0000, // Floating Move Register X-form (fmr. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FABS, 0xfc0007ff, 0xfc000210, 0x1f0000, // Floating Absolute Value X-form (fabs FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FABS_, 0xfc0007ff, 0xfc000211, 0x1f0000, // Floating Absolute Value X-form (fabs. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FNABS, 0xfc0007ff, 0xfc000110, 0x1f0000, // Floating Negative Absolute Value X-form (fnabs FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FNABS_, 0xfc0007ff, 0xfc000111, 0x1f0000, // Floating Negative Absolute Value X-form (fnabs. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FNEG, 0xfc0007ff, 0xfc000050, 0x1f0000, // Floating Negate X-form (fneg FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FNEG_, 0xfc0007ff, 0xfc000051, 0x1f0000, // Floating Negate X-form (fneg. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCPSGN, 0xfc0007ff, 0xfc000010, 0x0, // Floating Copy Sign X-form (fcpsgn FRT, FRA, FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FCPSGN_, 0xfc0007ff, 0xfc000011, 0x0, // Floating Copy Sign X-form (fcpsgn. FRT, FRA, FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FMRGEW, 0xfc0007fe, 0xfc00078c, 0x1, // Floating Merge Even Word X-form (fmrgew FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FMRGOW, 0xfc0007fe, 0xfc00068c, 0x1, // Floating Merge Odd Word X-form (fmrgow FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FADD, 0xfc00003f, 0xfc00002a, 0x7c0, // Floating Add [Single] A-form (fadd FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FADD_, 0xfc00003f, 0xfc00002b, 0x7c0, // Floating Add [Single] A-form (fadd. FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FADDS, 0xfc00003f, 0xec00002a, 0x7c0, // Floating Add [Single] A-form (fadds FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FADDS_, 0xfc00003f, 0xec00002b, 0x7c0, // Floating Add [Single] A-form (fadds. FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FSUB, 0xfc00003f, 0xfc000028, 0x7c0, // Floating Subtract [Single] A-form (fsub FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FSUB_, 0xfc00003f, 0xfc000029, 0x7c0, // Floating Subtract [Single] A-form (fsub. FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FSUBS, 0xfc00003f, 0xec000028, 0x7c0, // Floating Subtract [Single] A-form (fsubs FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FSUBS_, 0xfc00003f, 0xec000029, 0x7c0, // Floating Subtract [Single] A-form (fsubs. FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FMUL, 0xfc00003f, 0xfc000032, 0xf800, // Floating Multiply [Single] A-form (fmul FRT,FRA,FRC) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}}, + {FMUL_, 0xfc00003f, 0xfc000033, 0xf800, // Floating Multiply [Single] A-form (fmul. FRT,FRA,FRC) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}}, + {FMULS, 0xfc00003f, 0xec000032, 0xf800, // Floating Multiply [Single] A-form (fmuls FRT,FRA,FRC) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}}, + {FMULS_, 0xfc00003f, 0xec000033, 0xf800, // Floating Multiply [Single] A-form (fmuls. FRT,FRA,FRC) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}}, + {FDIV, 0xfc00003f, 0xfc000024, 0x7c0, // Floating Divide [Single] A-form (fdiv FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FDIV_, 0xfc00003f, 0xfc000025, 0x7c0, // Floating Divide [Single] A-form (fdiv. FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FDIVS, 0xfc00003f, 0xec000024, 0x7c0, // Floating Divide [Single] A-form (fdivs FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FDIVS_, 0xfc00003f, 0xec000025, 0x7c0, // Floating Divide [Single] A-form (fdivs. FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FSQRT, 0xfc00003f, 0xfc00002c, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrt FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FSQRT_, 0xfc00003f, 0xfc00002d, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrt. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FSQRTS, 0xfc00003f, 0xec00002c, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrts FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FSQRTS_, 0xfc00003f, 0xec00002d, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrts. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRE, 0xfc00003f, 0xfc000030, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fre FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRE_, 0xfc00003f, 0xfc000031, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fre. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRES, 0xfc00003f, 0xec000030, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fres FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRES_, 0xfc00003f, 0xec000031, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fres. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRSQRTE, 0xfc00003f, 0xfc000034, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrte FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRSQRTE_, 0xfc00003f, 0xfc000035, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrte. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRSQRTES, 0xfc00003f, 0xec000034, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrtes FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRSQRTES_, 0xfc00003f, 0xec000035, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrtes. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FTDIV, 0xfc0007fe, 0xfc000100, 0x600001, // Floating Test for software Divide X-form (ftdiv BF,FRA,FRB) + [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FTSQRT, 0xfc0007fe, 0xfc000140, 0x7f0001, // Floating Test for software Square Root X-form (ftsqrt BF,FRB) + [5]*argField{ap_CondRegField_6_8, ap_FPReg_16_20}}, + {FMADD, 0xfc00003f, 0xfc00003a, 0x0, // Floating Multiply-Add [Single] A-form (fmadd FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FMADD_, 0xfc00003f, 0xfc00003b, 0x0, // Floating Multiply-Add [Single] A-form (fmadd. FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FMADDS, 0xfc00003f, 0xec00003a, 0x0, // Floating Multiply-Add [Single] A-form (fmadds FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FMADDS_, 0xfc00003f, 0xec00003b, 0x0, // Floating Multiply-Add [Single] A-form (fmadds. FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FMSUB, 0xfc00003f, 0xfc000038, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsub FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FMSUB_, 0xfc00003f, 0xfc000039, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsub. FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FMSUBS, 0xfc00003f, 0xec000038, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsubs FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FMSUBS_, 0xfc00003f, 0xec000039, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsubs. FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FNMADD, 0xfc00003f, 0xfc00003e, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadd FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FNMADD_, 0xfc00003f, 0xfc00003f, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadd. FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FNMADDS, 0xfc00003f, 0xec00003e, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadds FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FNMADDS_, 0xfc00003f, 0xec00003f, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadds. FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FNMSUB, 0xfc00003f, 0xfc00003c, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsub FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FNMSUB_, 0xfc00003f, 0xfc00003d, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsub. FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FNMSUBS, 0xfc00003f, 0xec00003c, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsubs FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FNMSUBS_, 0xfc00003f, 0xec00003d, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsubs. FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FRSP, 0xfc0007ff, 0xfc000018, 0x1f0000, // Floating Round to Single-Precision X-form (frsp FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRSP_, 0xfc0007ff, 0xfc000019, 0x1f0000, // Floating Round to Single-Precision X-form (frsp. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTID, 0xfc0007ff, 0xfc00065c, 0x1f0000, // Floating Convert To Integer Doubleword X-form (fctid FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTID_, 0xfc0007ff, 0xfc00065d, 0x1f0000, // Floating Convert To Integer Doubleword X-form (fctid. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIDZ, 0xfc0007ff, 0xfc00065e, 0x1f0000, // Floating Convert To Integer Doubleword with round toward Zero X-form (fctidz FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIDZ_, 0xfc0007ff, 0xfc00065f, 0x1f0000, // Floating Convert To Integer Doubleword with round toward Zero X-form (fctidz. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIDU, 0xfc0007ff, 0xfc00075c, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned X-form (fctidu FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIDU_, 0xfc0007ff, 0xfc00075d, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned X-form (fctidu. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIDUZ, 0xfc0007ff, 0xfc00075e, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned with round toward Zero X-form (fctiduz FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIDUZ_, 0xfc0007ff, 0xfc00075f, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned with round toward Zero X-form (fctiduz. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIW, 0xfc0007ff, 0xfc00001c, 0x1f0000, // Floating Convert To Integer Word X-form (fctiw FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIW_, 0xfc0007ff, 0xfc00001d, 0x1f0000, // Floating Convert To Integer Word X-form (fctiw. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIWZ, 0xfc0007ff, 0xfc00001e, 0x1f0000, // Floating Convert To Integer Word with round toward Zero X-form (fctiwz FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIWZ_, 0xfc0007ff, 0xfc00001f, 0x1f0000, // Floating Convert To Integer Word with round toward Zero X-form (fctiwz. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIWU, 0xfc0007ff, 0xfc00011c, 0x1f0000, // Floating Convert To Integer Word Unsigned X-form (fctiwu FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIWU_, 0xfc0007ff, 0xfc00011d, 0x1f0000, // Floating Convert To Integer Word Unsigned X-form (fctiwu. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIWUZ, 0xfc0007ff, 0xfc00011e, 0x1f0000, // Floating Convert To Integer Word Unsigned with round toward Zero X-form (fctiwuz FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCTIWUZ_, 0xfc0007ff, 0xfc00011f, 0x1f0000, // Floating Convert To Integer Word Unsigned with round toward Zero X-form (fctiwuz. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCFID, 0xfc0007ff, 0xfc00069c, 0x1f0000, // Floating Convert From Integer Doubleword X-form (fcfid FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCFID_, 0xfc0007ff, 0xfc00069d, 0x1f0000, // Floating Convert From Integer Doubleword X-form (fcfid. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCFIDU, 0xfc0007ff, 0xfc00079c, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned X-form (fcfidu FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCFIDU_, 0xfc0007ff, 0xfc00079d, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned X-form (fcfidu. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCFIDS, 0xfc0007ff, 0xec00069c, 0x1f0000, // Floating Convert From Integer Doubleword Single X-form (fcfids FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCFIDS_, 0xfc0007ff, 0xec00069d, 0x1f0000, // Floating Convert From Integer Doubleword Single X-form (fcfids. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCFIDUS, 0xfc0007ff, 0xec00079c, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned Single X-form (fcfidus FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCFIDUS_, 0xfc0007ff, 0xec00079d, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned Single X-form (fcfidus. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRIN, 0xfc0007ff, 0xfc000310, 0x1f0000, // Floating Round to Integer Nearest X-form (frin FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRIN_, 0xfc0007ff, 0xfc000311, 0x1f0000, // Floating Round to Integer Nearest X-form (frin. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRIZ, 0xfc0007ff, 0xfc000350, 0x1f0000, // Floating Round to Integer Toward Zero X-form (friz FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRIZ_, 0xfc0007ff, 0xfc000351, 0x1f0000, // Floating Round to Integer Toward Zero X-form (friz. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRIP, 0xfc0007ff, 0xfc000390, 0x1f0000, // Floating Round to Integer Plus X-form (frip FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRIP_, 0xfc0007ff, 0xfc000391, 0x1f0000, // Floating Round to Integer Plus X-form (frip. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRIM, 0xfc0007ff, 0xfc0003d0, 0x1f0000, // Floating Round to Integer Minus X-form (frim FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FRIM_, 0xfc0007ff, 0xfc0003d1, 0x1f0000, // Floating Round to Integer Minus X-form (frim. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {FCMPU, 0xfc0007fe, 0xfc000000, 0x600001, // Floating Compare Unordered X-form (fcmpu BF,FRA,FRB) + [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FCMPO, 0xfc0007fe, 0xfc000040, 0x600001, // Floating Compare Ordered X-form (fcmpo BF,FRA,FRB) + [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, + {FSEL, 0xfc00003f, 0xfc00002e, 0x0, // Floating Select A-form (fsel FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {FSEL_, 0xfc00003f, 0xfc00002f, 0x0, // Floating Select A-form (fsel. FRT,FRA,FRC,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, + {MFFS, 0xfc0007ff, 0xfc00048e, 0x1ff800, // Move From FPSCR X-form (mffs FRT) + [5]*argField{ap_FPReg_6_10}}, + {MFFS_, 0xfc0007ff, 0xfc00048f, 0x1ff800, // Move From FPSCR X-form (mffs. FRT) + [5]*argField{ap_FPReg_6_10}}, + {MCRFS, 0xfc0007fe, 0xfc000080, 0x63f801, // Move to Condition Register from FPSCR X-form (mcrfs BF,BFA) + [5]*argField{ap_CondRegField_6_8, ap_CondRegField_11_13}}, + {MTFSFI, 0xfc0007ff, 0xfc00010c, 0x7e0800, // Move To FPSCR Field Immediate X-form (mtfsfi BF,U,W) + [5]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}}, + {MTFSFI_, 0xfc0007ff, 0xfc00010d, 0x7e0800, // Move To FPSCR Field Immediate X-form (mtfsfi. BF,U,W) + [5]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}}, + {MTFSF, 0xfc0007ff, 0xfc00058e, 0x0, // Move To FPSCR Fields XFL-form (mtfsf FLM,FRB,L,W) + [5]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}}, + {MTFSF_, 0xfc0007ff, 0xfc00058f, 0x0, // Move To FPSCR Fields XFL-form (mtfsf. FLM,FRB,L,W) + [5]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}}, + {MTFSB0, 0xfc0007ff, 0xfc00008c, 0x1ff800, // Move To FPSCR Bit 0 X-form (mtfsb0 BT) + [5]*argField{ap_CondRegBit_6_10}}, + {MTFSB0_, 0xfc0007ff, 0xfc00008d, 0x1ff800, // Move To FPSCR Bit 0 X-form (mtfsb0. BT) + [5]*argField{ap_CondRegBit_6_10}}, + {MTFSB1, 0xfc0007ff, 0xfc00004c, 0x1ff800, // Move To FPSCR Bit 1 X-form (mtfsb1 BT) + [5]*argField{ap_CondRegBit_6_10}}, + {MTFSB1_, 0xfc0007ff, 0xfc00004d, 0x1ff800, // Move To FPSCR Bit 1 X-form (mtfsb1. BT) + [5]*argField{ap_CondRegBit_6_10}}, + {LVEBX, 0xfc0007fe, 0x7c00000e, 0x1, // Load Vector Element Byte Indexed X-form (lvebx VRT,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LVEHX, 0xfc0007fe, 0x7c00004e, 0x1, // Load Vector Element Halfword Indexed X-form (lvehx VRT,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LVEWX, 0xfc0007fe, 0x7c00008e, 0x1, // Load Vector Element Word Indexed X-form (lvewx VRT,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LVX, 0xfc0007fe, 0x7c0000ce, 0x1, // Load Vector Indexed X-form (lvx VRT,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LVXL, 0xfc0007fe, 0x7c0002ce, 0x1, // Load Vector Indexed LRU X-form (lvxl VRT,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STVEBX, 0xfc0007fe, 0x7c00010e, 0x1, // Store Vector Element Byte Indexed X-form (stvebx VRS,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STVEHX, 0xfc0007fe, 0x7c00014e, 0x1, // Store Vector Element Halfword Indexed X-form (stvehx VRS,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STVEWX, 0xfc0007fe, 0x7c00018e, 0x1, // Store Vector Element Word Indexed X-form (stvewx VRS,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STVX, 0xfc0007fe, 0x7c0001ce, 0x1, // Store Vector Indexed X-form (stvx VRS,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STVXL, 0xfc0007fe, 0x7c0003ce, 0x1, // Store Vector Indexed LRU X-form (stvxl VRS,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LVSL, 0xfc0007fe, 0x7c00000c, 0x1, // Load Vector for Shift Left Indexed X-form (lvsl VRT,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LVSR, 0xfc0007fe, 0x7c00004c, 0x1, // Load Vector for Shift Right Indexed X-form (lvsr VRT,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {VPKPX, 0xfc0007ff, 0x1000030e, 0x0, // Vector Pack Pixel VX-form (vpkpx VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKSDSS, 0xfc0007ff, 0x100005ce, 0x0, // Vector Pack Signed Doubleword Signed Saturate VX-form (vpksdss VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKSDUS, 0xfc0007ff, 0x1000054e, 0x0, // Vector Pack Signed Doubleword Unsigned Saturate VX-form (vpksdus VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKSHSS, 0xfc0007ff, 0x1000018e, 0x0, // Vector Pack Signed Halfword Signed Saturate VX-form (vpkshss VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKSHUS, 0xfc0007ff, 0x1000010e, 0x0, // Vector Pack Signed Halfword Unsigned Saturate VX-form (vpkshus VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKSWSS, 0xfc0007ff, 0x100001ce, 0x0, // Vector Pack Signed Word Signed Saturate VX-form (vpkswss VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKSWUS, 0xfc0007ff, 0x1000014e, 0x0, // Vector Pack Signed Word Unsigned Saturate VX-form (vpkswus VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKUDUM, 0xfc0007ff, 0x1000044e, 0x0, // Vector Pack Unsigned Doubleword Unsigned Modulo VX-form (vpkudum VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKUDUS, 0xfc0007ff, 0x100004ce, 0x0, // Vector Pack Unsigned Doubleword Unsigned Saturate VX-form (vpkudus VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKUHUM, 0xfc0007ff, 0x1000000e, 0x0, // Vector Pack Unsigned Halfword Unsigned Modulo VX-form (vpkuhum VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKUHUS, 0xfc0007ff, 0x1000008e, 0x0, // Vector Pack Unsigned Halfword Unsigned Saturate VX-form (vpkuhus VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKUWUM, 0xfc0007ff, 0x1000004e, 0x0, // Vector Pack Unsigned Word Unsigned Modulo VX-form (vpkuwum VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPKUWUS, 0xfc0007ff, 0x100000ce, 0x0, // Vector Pack Unsigned Word Unsigned Saturate VX-form (vpkuwus VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VUPKHPX, 0xfc0007ff, 0x1000034e, 0x1f0000, // Vector Unpack High Pixel VX-form (vupkhpx VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VUPKLPX, 0xfc0007ff, 0x100003ce, 0x1f0000, // Vector Unpack Low Pixel VX-form (vupklpx VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VUPKHSB, 0xfc0007ff, 0x1000020e, 0x1f0000, // Vector Unpack High Signed Byte VX-form (vupkhsb VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VUPKHSH, 0xfc0007ff, 0x1000024e, 0x1f0000, // Vector Unpack High Signed Halfword VX-form (vupkhsh VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VUPKHSW, 0xfc0007ff, 0x1000064e, 0x1f0000, // Vector Unpack High Signed Word VX-form (vupkhsw VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VUPKLSB, 0xfc0007ff, 0x1000028e, 0x1f0000, // Vector Unpack Low Signed Byte VX-form (vupklsb VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VUPKLSH, 0xfc0007ff, 0x100002ce, 0x1f0000, // Vector Unpack Low Signed Halfword VX-form (vupklsh VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VUPKLSW, 0xfc0007ff, 0x100006ce, 0x1f0000, // Vector Unpack Low Signed Word VX-form (vupklsw VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VMRGHB, 0xfc0007ff, 0x1000000c, 0x0, // Vector Merge High Byte VX-form (vmrghb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMRGHH, 0xfc0007ff, 0x1000004c, 0x0, // Vector Merge High Halfword VX-form (vmrghh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMRGLB, 0xfc0007ff, 0x1000010c, 0x0, // Vector Merge Low Byte VX-form (vmrglb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMRGLH, 0xfc0007ff, 0x1000014c, 0x0, // Vector Merge Low Halfword VX-form (vmrglh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMRGHW, 0xfc0007ff, 0x1000008c, 0x0, // Vector Merge High Word VX-form (vmrghw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMRGLW, 0xfc0007ff, 0x1000018c, 0x0, // Vector Merge Low Word VX-form (vmrglw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMRGEW, 0xfc0007ff, 0x1000078c, 0x0, // Vector Merge Even Word VX-form (vmrgew VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMRGOW, 0xfc0007ff, 0x1000068c, 0x0, // Vector Merge Odd Word VX-form (vmrgow VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSPLTB, 0xfc0007ff, 0x1000020c, 0x100000, // Vector Splat Byte VX-form (vspltb VRT,VRB,UIM) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}}, + {VSPLTH, 0xfc0007ff, 0x1000024c, 0x180000, // Vector Splat Halfword VX-form (vsplth VRT,VRB,UIM) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_13_15}}, + {VSPLTW, 0xfc0007ff, 0x1000028c, 0x1c0000, // Vector Splat Word VX-form (vspltw VRT,VRB,UIM) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_14_15}}, + {VSPLTISB, 0xfc0007ff, 0x1000030c, 0xf800, // Vector Splat Immediate Signed Byte VX-form (vspltisb VRT,SIM) + [5]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}}, + {VSPLTISH, 0xfc0007ff, 0x1000034c, 0xf800, // Vector Splat Immediate Signed Halfword VX-form (vspltish VRT,SIM) + [5]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}}, + {VSPLTISW, 0xfc0007ff, 0x1000038c, 0xf800, // Vector Splat Immediate Signed Word VX-form (vspltisw VRT,SIM) + [5]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}}, + {VPERM, 0xfc00003f, 0x1000002b, 0x0, // Vector Permute VA-form (vperm VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VSEL, 0xfc00003f, 0x1000002a, 0x0, // Vector Select VA-form (vsel VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VSL, 0xfc0007ff, 0x100001c4, 0x0, // Vector Shift Left VX-form (vsl VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSLDOI, 0xfc00003f, 0x1000002c, 0x400, // Vector Shift Left Double by Octet Immediate VA-form (vsldoi VRT,VRA,VRB,SHB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_25}}, + {VSLO, 0xfc0007ff, 0x1000040c, 0x0, // Vector Shift Left by Octet VX-form (vslo VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSR, 0xfc0007ff, 0x100002c4, 0x0, // Vector Shift Right VX-form (vsr VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSRO, 0xfc0007ff, 0x1000044c, 0x0, // Vector Shift Right by Octet VX-form (vsro VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDCUW, 0xfc0007ff, 0x10000180, 0x0, // Vector Add and Write Carry-Out Unsigned Word VX-form (vaddcuw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDSBS, 0xfc0007ff, 0x10000300, 0x0, // Vector Add Signed Byte Saturate VX-form (vaddsbs VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDSHS, 0xfc0007ff, 0x10000340, 0x0, // Vector Add Signed Halfword Saturate VX-form (vaddshs VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDSWS, 0xfc0007ff, 0x10000380, 0x0, // Vector Add Signed Word Saturate VX-form (vaddsws VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDUBM, 0xfc0007ff, 0x10000000, 0x0, // Vector Add Unsigned Byte Modulo VX-form (vaddubm VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDUDM, 0xfc0007ff, 0x100000c0, 0x0, // Vector Add Unsigned Doubleword Modulo VX-form (vaddudm VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDUHM, 0xfc0007ff, 0x10000040, 0x0, // Vector Add Unsigned Halfword Modulo VX-form (vadduhm VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDUWM, 0xfc0007ff, 0x10000080, 0x0, // Vector Add Unsigned Word Modulo VX-form (vadduwm VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDUBS, 0xfc0007ff, 0x10000200, 0x0, // Vector Add Unsigned Byte Saturate VX-form (vaddubs VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDUHS, 0xfc0007ff, 0x10000240, 0x0, // Vector Add Unsigned Halfword Saturate VX-form (vadduhs VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDUWS, 0xfc0007ff, 0x10000280, 0x0, // Vector Add Unsigned Word Saturate VX-form (vadduws VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDUQM, 0xfc0007ff, 0x10000100, 0x0, // Vector Add Unsigned Quadword Modulo VX-form (vadduqm VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDEUQM, 0xfc00003f, 0x1000003c, 0x0, // Vector Add Extended Unsigned Quadword Modulo VA-form (vaddeuqm VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VADDCUQ, 0xfc0007ff, 0x10000140, 0x0, // Vector Add & write Carry Unsigned Quadword VX-form (vaddcuq VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDECUQ, 0xfc00003f, 0x1000003d, 0x0, // Vector Add Extended & write Carry Unsigned Quadword VA-form (vaddecuq VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VSUBCUW, 0xfc0007ff, 0x10000580, 0x0, // Vector Subtract and Write Carry-Out Unsigned Word VX-form (vsubcuw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBSBS, 0xfc0007ff, 0x10000700, 0x0, // Vector Subtract Signed Byte Saturate VX-form (vsubsbs VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBSHS, 0xfc0007ff, 0x10000740, 0x0, // Vector Subtract Signed Halfword Saturate VX-form (vsubshs VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBSWS, 0xfc0007ff, 0x10000780, 0x0, // Vector Subtract Signed Word Saturate VX-form (vsubsws VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBUBM, 0xfc0007ff, 0x10000400, 0x0, // Vector Subtract Unsigned Byte Modulo VX-form (vsububm VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBUDM, 0xfc0007ff, 0x100004c0, 0x0, // Vector Subtract Unsigned Doubleword Modulo VX-form (vsubudm VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBUHM, 0xfc0007ff, 0x10000440, 0x0, // Vector Subtract Unsigned Halfword Modulo VX-form (vsubuhm VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBUWM, 0xfc0007ff, 0x10000480, 0x0, // Vector Subtract Unsigned Word Modulo VX-form (vsubuwm VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBUBS, 0xfc0007ff, 0x10000600, 0x0, // Vector Subtract Unsigned Byte Saturate VX-form (vsububs VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBUHS, 0xfc0007ff, 0x10000640, 0x0, // Vector Subtract Unsigned Halfword Saturate VX-form (vsubuhs VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBUWS, 0xfc0007ff, 0x10000680, 0x0, // Vector Subtract Unsigned Word Saturate VX-form (vsubuws VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBUQM, 0xfc0007ff, 0x10000500, 0x0, // Vector Subtract Unsigned Quadword Modulo VX-form (vsubuqm VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBEUQM, 0xfc00003f, 0x1000003e, 0x0, // Vector Subtract Extended Unsigned Quadword Modulo VA-form (vsubeuqm VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VSUBCUQ, 0xfc0007ff, 0x10000540, 0x0, // Vector Subtract & write Carry Unsigned Quadword VX-form (vsubcuq VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBECUQ, 0xfc00003f, 0x1000003f, 0x0, // Vector Subtract Extended & write Carry Unsigned Quadword VA-form (vsubecuq VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VMULESB, 0xfc0007ff, 0x10000308, 0x0, // Vector Multiply Even Signed Byte VX-form (vmulesb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULEUB, 0xfc0007ff, 0x10000208, 0x0, // Vector Multiply Even Unsigned Byte VX-form (vmuleub VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULOSB, 0xfc0007ff, 0x10000108, 0x0, // Vector Multiply Odd Signed Byte VX-form (vmulosb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULOUB, 0xfc0007ff, 0x10000008, 0x0, // Vector Multiply Odd Unsigned Byte VX-form (vmuloub VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULESH, 0xfc0007ff, 0x10000348, 0x0, // Vector Multiply Even Signed Halfword VX-form (vmulesh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULEUH, 0xfc0007ff, 0x10000248, 0x0, // Vector Multiply Even Unsigned Halfword VX-form (vmuleuh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULOSH, 0xfc0007ff, 0x10000148, 0x0, // Vector Multiply Odd Signed Halfword VX-form (vmulosh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULOUH, 0xfc0007ff, 0x10000048, 0x0, // Vector Multiply Odd Unsigned Halfword VX-form (vmulouh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULESW, 0xfc0007ff, 0x10000388, 0x0, // Vector Multiply Even Signed Word VX-form (vmulesw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULEUW, 0xfc0007ff, 0x10000288, 0x0, // Vector Multiply Even Unsigned Word VX-form (vmuleuw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULOSW, 0xfc0007ff, 0x10000188, 0x0, // Vector Multiply Odd Signed Word VX-form (vmulosw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULOUW, 0xfc0007ff, 0x10000088, 0x0, // Vector Multiply Odd Unsigned Word VX-form (vmulouw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMULUWM, 0xfc0007ff, 0x10000089, 0x0, // Vector Multiply Unsigned Word Modulo VX-form (vmuluwm VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMHADDSHS, 0xfc00003f, 0x10000020, 0x0, // Vector Multiply-High-Add Signed Halfword Saturate VA-form (vmhaddshs VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VMHRADDSHS, 0xfc00003f, 0x10000021, 0x0, // Vector Multiply-High-Round-Add Signed Halfword Saturate VA-form (vmhraddshs VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VMLADDUHM, 0xfc00003f, 0x10000022, 0x0, // Vector Multiply-Low-Add Unsigned Halfword Modulo VA-form (vmladduhm VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VMSUMUBM, 0xfc00003f, 0x10000024, 0x0, // Vector Multiply-Sum Unsigned Byte Modulo VA-form (vmsumubm VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VMSUMMBM, 0xfc00003f, 0x10000025, 0x0, // Vector Multiply-Sum Mixed Byte Modulo VA-form (vmsummbm VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VMSUMSHM, 0xfc00003f, 0x10000028, 0x0, // Vector Multiply-Sum Signed Halfword Modulo VA-form (vmsumshm VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VMSUMSHS, 0xfc00003f, 0x10000029, 0x0, // Vector Multiply-Sum Signed Halfword Saturate VA-form (vmsumshs VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VMSUMUHM, 0xfc00003f, 0x10000026, 0x0, // Vector Multiply-Sum Unsigned Halfword Modulo VA-form (vmsumuhm VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VMSUMUHS, 0xfc00003f, 0x10000027, 0x0, // Vector Multiply-Sum Unsigned Halfword Saturate VA-form (vmsumuhs VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VSUMSWS, 0xfc0007ff, 0x10000788, 0x0, // Vector Sum across Signed Word Saturate VX-form (vsumsws VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUM2SWS, 0xfc0007ff, 0x10000688, 0x0, // Vector Sum across Half Signed Word Saturate VX-form (vsum2sws VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUM4SBS, 0xfc0007ff, 0x10000708, 0x0, // Vector Sum across Quarter Signed Byte Saturate VX-form (vsum4sbs VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUM4SHS, 0xfc0007ff, 0x10000648, 0x0, // Vector Sum across Quarter Signed Halfword Saturate VX-form (vsum4shs VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUM4UBS, 0xfc0007ff, 0x10000608, 0x0, // Vector Sum across Quarter Unsigned Byte Saturate VX-form (vsum4ubs VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VAVGSB, 0xfc0007ff, 0x10000502, 0x0, // Vector Average Signed Byte VX-form (vavgsb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VAVGSH, 0xfc0007ff, 0x10000542, 0x0, // Vector Average Signed Halfword VX-form (vavgsh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VAVGSW, 0xfc0007ff, 0x10000582, 0x0, // Vector Average Signed Word VX-form (vavgsw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VAVGUB, 0xfc0007ff, 0x10000402, 0x0, // Vector Average Unsigned Byte VX-form (vavgub VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VAVGUW, 0xfc0007ff, 0x10000482, 0x0, // Vector Average Unsigned Word VX-form (vavguw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VAVGUH, 0xfc0007ff, 0x10000442, 0x0, // Vector Average Unsigned Halfword VX-form (vavguh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMAXSB, 0xfc0007ff, 0x10000102, 0x0, // Vector Maximum Signed Byte VX-form (vmaxsb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMAXSD, 0xfc0007ff, 0x100001c2, 0x0, // Vector Maximum Signed Doubleword VX-form (vmaxsd VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMAXUB, 0xfc0007ff, 0x10000002, 0x0, // Vector Maximum Unsigned Byte VX-form (vmaxub VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMAXUD, 0xfc0007ff, 0x100000c2, 0x0, // Vector Maximum Unsigned Doubleword VX-form (vmaxud VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMAXSH, 0xfc0007ff, 0x10000142, 0x0, // Vector Maximum Signed Halfword VX-form (vmaxsh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMAXSW, 0xfc0007ff, 0x10000182, 0x0, // Vector Maximum Signed Word VX-form (vmaxsw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMAXUH, 0xfc0007ff, 0x10000042, 0x0, // Vector Maximum Unsigned Halfword VX-form (vmaxuh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMAXUW, 0xfc0007ff, 0x10000082, 0x0, // Vector Maximum Unsigned Word VX-form (vmaxuw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMINSB, 0xfc0007ff, 0x10000302, 0x0, // Vector Minimum Signed Byte VX-form (vminsb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMINSD, 0xfc0007ff, 0x100003c2, 0x0, // Vector Minimum Signed Doubleword VX-form (vminsd VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMINUB, 0xfc0007ff, 0x10000202, 0x0, // Vector Minimum Unsigned Byte VX-form (vminub VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMINUD, 0xfc0007ff, 0x100002c2, 0x0, // Vector Minimum Unsigned Doubleword VX-form (vminud VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMINSH, 0xfc0007ff, 0x10000342, 0x0, // Vector Minimum Signed Halfword VX-form (vminsh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMINSW, 0xfc0007ff, 0x10000382, 0x0, // Vector Minimum Signed Word VX-form (vminsw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMINUH, 0xfc0007ff, 0x10000242, 0x0, // Vector Minimum Unsigned Halfword VX-form (vminuh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMINUW, 0xfc0007ff, 0x10000282, 0x0, // Vector Minimum Unsigned Word VX-form (vminuw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPEQUB, 0xfc0007ff, 0x10000006, 0x0, // Vector Compare Equal To Unsigned Byte VC-form (vcmpequb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPEQUB_, 0xfc0007ff, 0x10000406, 0x0, // Vector Compare Equal To Unsigned Byte VC-form (vcmpequb. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPEQUH, 0xfc0007ff, 0x10000046, 0x0, // Vector Compare Equal To Unsigned Halfword VC-form (vcmpequh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPEQUH_, 0xfc0007ff, 0x10000446, 0x0, // Vector Compare Equal To Unsigned Halfword VC-form (vcmpequh. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPEQUW, 0xfc0007ff, 0x10000086, 0x0, // Vector Compare Equal To Unsigned Word VC-form (vcmpequw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPEQUW_, 0xfc0007ff, 0x10000486, 0x0, // Vector Compare Equal To Unsigned Word VC-form (vcmpequw. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPEQUD, 0xfc0007ff, 0x100000c7, 0x0, // Vector Compare Equal To Unsigned Doubleword VX-form (vcmpequd VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPEQUD_, 0xfc0007ff, 0x100004c7, 0x0, // Vector Compare Equal To Unsigned Doubleword VX-form (vcmpequd. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTSB, 0xfc0007ff, 0x10000306, 0x0, // Vector Compare Greater Than Signed Byte VC-form (vcmpgtsb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTSB_, 0xfc0007ff, 0x10000706, 0x0, // Vector Compare Greater Than Signed Byte VC-form (vcmpgtsb. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTSD, 0xfc0007ff, 0x100003c7, 0x0, // Vector Compare Greater Than Signed Doubleword VX-form (vcmpgtsd VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTSD_, 0xfc0007ff, 0x100007c7, 0x0, // Vector Compare Greater Than Signed Doubleword VX-form (vcmpgtsd. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTSH, 0xfc0007ff, 0x10000346, 0x0, // Vector Compare Greater Than Signed Halfword VC-form (vcmpgtsh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTSH_, 0xfc0007ff, 0x10000746, 0x0, // Vector Compare Greater Than Signed Halfword VC-form (vcmpgtsh. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTSW, 0xfc0007ff, 0x10000386, 0x0, // Vector Compare Greater Than Signed Word VC-form (vcmpgtsw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTSW_, 0xfc0007ff, 0x10000786, 0x0, // Vector Compare Greater Than Signed Word VC-form (vcmpgtsw. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTUB, 0xfc0007ff, 0x10000206, 0x0, // Vector Compare Greater Than Unsigned Byte VC-form (vcmpgtub VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTUB_, 0xfc0007ff, 0x10000606, 0x0, // Vector Compare Greater Than Unsigned Byte VC-form (vcmpgtub. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTUD, 0xfc0007ff, 0x100002c7, 0x0, // Vector Compare Greater Than Unsigned Doubleword VX-form (vcmpgtud VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTUD_, 0xfc0007ff, 0x100006c7, 0x0, // Vector Compare Greater Than Unsigned Doubleword VX-form (vcmpgtud. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTUH, 0xfc0007ff, 0x10000246, 0x0, // Vector Compare Greater Than Unsigned Halfword VC-form (vcmpgtuh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTUH_, 0xfc0007ff, 0x10000646, 0x0, // Vector Compare Greater Than Unsigned Halfword VC-form (vcmpgtuh. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTUW, 0xfc0007ff, 0x10000286, 0x0, // Vector Compare Greater Than Unsigned Word VC-form (vcmpgtuw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTUW_, 0xfc0007ff, 0x10000686, 0x0, // Vector Compare Greater Than Unsigned Word VC-form (vcmpgtuw. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VAND, 0xfc0007ff, 0x10000404, 0x0, // Vector Logical AND VX-form (vand VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VANDC, 0xfc0007ff, 0x10000444, 0x0, // Vector Logical AND with Complement VX-form (vandc VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VEQV, 0xfc0007ff, 0x10000684, 0x0, // Vector Logical Equivalent VX-form (veqv VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VNAND, 0xfc0007ff, 0x10000584, 0x0, // Vector Logical NAND VX-form (vnand VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VORC, 0xfc0007ff, 0x10000544, 0x0, // Vector Logical OR with Complement VX-form (vorc VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VNOR, 0xfc0007ff, 0x10000504, 0x0, // Vector Logical NOR VX-form (vnor VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VOR, 0xfc0007ff, 0x10000484, 0x0, // Vector Logical OR VX-form (vor VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VXOR, 0xfc0007ff, 0x100004c4, 0x0, // Vector Logical XOR VX-form (vxor VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VRLB, 0xfc0007ff, 0x10000004, 0x0, // Vector Rotate Left Byte VX-form (vrlb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VRLH, 0xfc0007ff, 0x10000044, 0x0, // Vector Rotate Left Halfword VX-form (vrlh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VRLW, 0xfc0007ff, 0x10000084, 0x0, // Vector Rotate Left Word VX-form (vrlw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VRLD, 0xfc0007ff, 0x100000c4, 0x0, // Vector Rotate Left Doubleword VX-form (vrld VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSLB, 0xfc0007ff, 0x10000104, 0x0, // Vector Shift Left Byte VX-form (vslb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSLH, 0xfc0007ff, 0x10000144, 0x0, // Vector Shift Left Halfword VX-form (vslh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSLW, 0xfc0007ff, 0x10000184, 0x0, // Vector Shift Left Word VX-form (vslw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSLD, 0xfc0007ff, 0x100005c4, 0x0, // Vector Shift Left Doubleword VX-form (vsld VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSRB, 0xfc0007ff, 0x10000204, 0x0, // Vector Shift Right Byte VX-form (vsrb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSRH, 0xfc0007ff, 0x10000244, 0x0, // Vector Shift Right Halfword VX-form (vsrh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSRW, 0xfc0007ff, 0x10000284, 0x0, // Vector Shift Right Word VX-form (vsrw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSRD, 0xfc0007ff, 0x100006c4, 0x0, // Vector Shift Right Doubleword VX-form (vsrd VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSRAB, 0xfc0007ff, 0x10000304, 0x0, // Vector Shift Right Algebraic Byte VX-form (vsrab VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSRAH, 0xfc0007ff, 0x10000344, 0x0, // Vector Shift Right Algebraic Halfword VX-form (vsrah VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSRAW, 0xfc0007ff, 0x10000384, 0x0, // Vector Shift Right Algebraic Word VX-form (vsraw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSRAD, 0xfc0007ff, 0x100003c4, 0x0, // Vector Shift Right Algebraic Doubleword VX-form (vsrad VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VADDFP, 0xfc0007ff, 0x1000000a, 0x0, // Vector Add Single-Precision VX-form (vaddfp VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSUBFP, 0xfc0007ff, 0x1000004a, 0x0, // Vector Subtract Single-Precision VX-form (vsubfp VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMADDFP, 0xfc00003f, 0x1000002e, 0x0, // Vector Multiply-Add Single-Precision VA-form (vmaddfp VRT,VRA,VRC,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_21_25, ap_VecReg_16_20}}, + {VNMSUBFP, 0xfc00003f, 0x1000002f, 0x0, // Vector Negative Multiply-Subtract Single-Precision VA-form (vnmsubfp VRT,VRA,VRC,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_21_25, ap_VecReg_16_20}}, + {VMAXFP, 0xfc0007ff, 0x1000040a, 0x0, // Vector Maximum Single-Precision VX-form (vmaxfp VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VMINFP, 0xfc0007ff, 0x1000044a, 0x0, // Vector Minimum Single-Precision VX-form (vminfp VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCTSXS, 0xfc0007ff, 0x100003ca, 0x0, // Vector Convert To Signed Fixed-Point Word Saturate VX-form (vctsxs VRT,VRB,UIM) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}}, + {VCTUXS, 0xfc0007ff, 0x1000038a, 0x0, // Vector Convert To Unsigned Fixed-Point Word Saturate VX-form (vctuxs VRT,VRB,UIM) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}}, + {VCFSX, 0xfc0007ff, 0x1000034a, 0x0, // Vector Convert From Signed Fixed-Point Word VX-form (vcfsx VRT,VRB,UIM) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}}, + {VCFUX, 0xfc0007ff, 0x1000030a, 0x0, // Vector Convert From Unsigned Fixed-Point Word VX-form (vcfux VRT,VRB,UIM) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}}, + {VRFIM, 0xfc0007ff, 0x100002ca, 0x1f0000, // Vector Round to Single-Precision Integer toward -Infinity VX-form (vrfim VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VRFIN, 0xfc0007ff, 0x1000020a, 0x1f0000, // Vector Round to Single-Precision Integer Nearest VX-form (vrfin VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VRFIP, 0xfc0007ff, 0x1000028a, 0x1f0000, // Vector Round to Single-Precision Integer toward +Infinity VX-form (vrfip VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VRFIZ, 0xfc0007ff, 0x1000024a, 0x1f0000, // Vector Round to Single-Precision Integer toward Zero VX-form (vrfiz VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VCMPBFP, 0xfc0007ff, 0x100003c6, 0x0, // Vector Compare Bounds Single-Precision VC-form (vcmpbfp VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPBFP_, 0xfc0007ff, 0x100007c6, 0x0, // Vector Compare Bounds Single-Precision VC-form (vcmpbfp. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPEQFP, 0xfc0007ff, 0x100000c6, 0x0, // Vector Compare Equal To Single-Precision VC-form (vcmpeqfp VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPEQFP_, 0xfc0007ff, 0x100004c6, 0x0, // Vector Compare Equal To Single-Precision VC-form (vcmpeqfp. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGEFP, 0xfc0007ff, 0x100001c6, 0x0, // Vector Compare Greater Than or Equal To Single-Precision VC-form (vcmpgefp VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGEFP_, 0xfc0007ff, 0x100005c6, 0x0, // Vector Compare Greater Than or Equal To Single-Precision VC-form (vcmpgefp. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTFP, 0xfc0007ff, 0x100002c6, 0x0, // Vector Compare Greater Than Single-Precision VC-form (vcmpgtfp VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCMPGTFP_, 0xfc0007ff, 0x100006c6, 0x0, // Vector Compare Greater Than Single-Precision VC-form (vcmpgtfp. VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VEXPTEFP, 0xfc0007ff, 0x1000018a, 0x1f0000, // Vector 2 Raised to the Exponent Estimate Floating-Point VX-form (vexptefp VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VLOGEFP, 0xfc0007ff, 0x100001ca, 0x1f0000, // Vector Log Base 2 Estimate Floating-Point VX-form (vlogefp VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VREFP, 0xfc0007ff, 0x1000010a, 0x1f0000, // Vector Reciprocal Estimate Single-Precision VX-form (vrefp VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VRSQRTEFP, 0xfc0007ff, 0x1000014a, 0x1f0000, // Vector Reciprocal Square Root Estimate Single-Precision VX-form (vrsqrtefp VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VCIPHER, 0xfc0007ff, 0x10000508, 0x0, // Vector AES Cipher VX-form (vcipher VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VCIPHERLAST, 0xfc0007ff, 0x10000509, 0x0, // Vector AES Cipher Last VX-form (vcipherlast VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VNCIPHER, 0xfc0007ff, 0x10000548, 0x0, // Vector AES Inverse Cipher VX-form (vncipher VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VNCIPHERLAST, 0xfc0007ff, 0x10000549, 0x0, // Vector AES Inverse Cipher Last VX-form (vncipherlast VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VSBOX, 0xfc0007ff, 0x100005c8, 0xf800, // Vector AES SubBytes VX-form (vsbox VRT,VRA) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15}}, + {VSHASIGMAD, 0xfc0007ff, 0x100006c2, 0x0, // Vector SHA-512 Sigma Doubleword VX-form (vshasigmad VRT,VRA,ST,SIX) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_ImmUnsigned_16_16, ap_ImmUnsigned_17_20}}, + {VSHASIGMAW, 0xfc0007ff, 0x10000682, 0x0, // Vector SHA-256 Sigma Word VX-form (vshasigmaw VRT,VRA,ST,SIX) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_ImmUnsigned_16_16, ap_ImmUnsigned_17_20}}, + {VPMSUMB, 0xfc0007ff, 0x10000408, 0x0, // Vector Polynomial Multiply-Sum Byte VX-form (vpmsumb VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPMSUMD, 0xfc0007ff, 0x100004c8, 0x0, // Vector Polynomial Multiply-Sum Doubleword VX-form (vpmsumd VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPMSUMH, 0xfc0007ff, 0x10000448, 0x0, // Vector Polynomial Multiply-Sum Halfword VX-form (vpmsumh VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPMSUMW, 0xfc0007ff, 0x10000488, 0x0, // Vector Polynomial Multiply-Sum Word VX-form (vpmsumw VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {VPERMXOR, 0xfc00003f, 0x1000002d, 0x0, // Vector Permute and Exclusive-OR VA-form (vpermxor VRT,VRA,VRB,VRC) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, + {VGBBD, 0xfc0007ff, 0x1000050c, 0x1f0000, // Vector Gather Bits by Bytes by Doubleword VX-form (vgbbd VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VCLZB, 0xfc0007ff, 0x10000702, 0x1f0000, // Vector Count Leading Zeros Byte VX-form (vclzb VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VCLZH, 0xfc0007ff, 0x10000742, 0x1f0000, // Vector Count Leading Zeros Halfword VX-form (vclzh VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VCLZW, 0xfc0007ff, 0x10000782, 0x1f0000, // Vector Count Leading Zeros Word VX-form (vclzw VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VCLZD, 0xfc0007ff, 0x100007c2, 0x1f0000, // Vector Count Leading Zeros Doubleword (vclzd VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VPOPCNTB, 0xfc0007ff, 0x10000703, 0x1f0000, // Vector Population Count Byte (vpopcntb VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VPOPCNTD, 0xfc0007ff, 0x100007c3, 0x1f0000, // Vector Population Count Doubleword (vpopcntd VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VPOPCNTH, 0xfc0007ff, 0x10000743, 0x1f0000, // Vector Population Count Halfword (vpopcnth VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VPOPCNTW, 0xfc0007ff, 0x10000783, 0x1f0000, // Vector Population Count Word (vpopcntw VRT,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, + {VBPERMQ, 0xfc0007ff, 0x1000054c, 0x0, // Vector Bit Permute Quadword VX-form (vbpermq VRT,VRA,VRB) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, + {BCDADD_, 0xfc0005ff, 0x10000401, 0x0, // Decimal Add Modulo VX-form (bcdadd. VRT,VRA,VRB,PS) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}}, + {BCDSUB_, 0xfc0005ff, 0x10000441, 0x0, // Decimal Subtract Modulo VX-form (bcdsub. VRT,VRA,VRB,PS) + [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}}, + {MTVSCR, 0xfc0007ff, 0x10000644, 0x3ff0000, // Move To Vector Status and Control Register VX-form (mtvscr VRB) + [5]*argField{ap_VecReg_16_20}}, + {MFVSCR, 0xfc0007ff, 0x10000604, 0x1ff800, // Move From Vector Status and Control Register VX-form (mfvscr VRT) + [5]*argField{ap_VecReg_6_10}}, + {DADD, 0xfc0007ff, 0xec000004, 0x0, // DFP Add [Quad] X-form (dadd FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DADD_, 0xfc0007ff, 0xec000005, 0x0, // DFP Add [Quad] X-form (dadd. FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DSUB, 0xfc0007ff, 0xec000404, 0x0, // DFP Subtract [Quad] X-form (dsub FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DSUB_, 0xfc0007ff, 0xec000405, 0x0, // DFP Subtract [Quad] X-form (dsub. FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DMUL, 0xfc0007ff, 0xec000044, 0x0, // DFP Multiply [Quad] X-form (dmul FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DMUL_, 0xfc0007ff, 0xec000045, 0x0, // DFP Multiply [Quad] X-form (dmul. FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DDIV, 0xfc0007ff, 0xec000444, 0x0, // DFP Divide [Quad] X-form (ddiv FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DDIV_, 0xfc0007ff, 0xec000445, 0x0, // DFP Divide [Quad] X-form (ddiv. FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DCMPU, 0xfc0007fe, 0xec000504, 0x600001, // DFP Compare Unordered [Quad] X-form (dcmpu BF,FRA,FRB) + [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DCMPO, 0xfc0007fe, 0xec000104, 0x600001, // DFP Compare Ordered [Quad] X-form (dcmpo BF,FRA,FRB) + [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DTSTDC, 0xfc0003fe, 0xec000184, 0x600001, // DFP Test Data Class [Quad] Z22-form (dtstdc BF,FRA,DCM) + [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, + {DTSTDG, 0xfc0003fe, 0xec0001c4, 0x600001, // DFP Test Data Group [Quad] Z22-form (dtstdg BF,FRA,DGM) + [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, + {DTSTEX, 0xfc0007fe, 0xec000144, 0x600001, // DFP Test Exponent [Quad] X-form (dtstex BF,FRA,FRB) + [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DTSTSF, 0xfc0007fe, 0xec000544, 0x600001, // DFP Test Significance [Quad] X-form (dtstsf BF,FRA,FRB) + [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DQUAI, 0xfc0001ff, 0xec000086, 0x0, // DFP Quantize Immediate [Quad] Z23-form (dquai TE,FRT,FRB,RMC) + [5]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, + {DQUAI_, 0xfc0001ff, 0xec000087, 0x0, // DFP Quantize Immediate [Quad] Z23-form (dquai. TE,FRT,FRB,RMC) + [5]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, + {DQUA, 0xfc0001ff, 0xec000006, 0x0, // DFP Quantize [Quad] Z23-form (dqua FRT,FRA,FRB,RMC) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, + {DQUA_, 0xfc0001ff, 0xec000007, 0x0, // DFP Quantize [Quad] Z23-form (dqua. FRT,FRA,FRB,RMC) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, + {DRRND, 0xfc0001ff, 0xec000046, 0x0, // DFP Reround [Quad] Z23-form (drrnd FRT,FRA,FRB,RMC) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, + {DRRND_, 0xfc0001ff, 0xec000047, 0x0, // DFP Reround [Quad] Z23-form (drrnd. FRT,FRA,FRB,RMC) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, + {DRINTX, 0xfc0001ff, 0xec0000c6, 0x1e0000, // DFP Round To FP Integer With Inexact [Quad] Z23-form (drintx R,FRT,FRB,RMC) + [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, + {DRINTX_, 0xfc0001ff, 0xec0000c7, 0x1e0000, // DFP Round To FP Integer With Inexact [Quad] Z23-form (drintx. R,FRT,FRB,RMC) + [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, + {DRINTN, 0xfc0001ff, 0xec0001c6, 0x1e0000, // DFP Round To FP Integer Without Inexact [Quad] Z23-form (drintn R,FRT,FRB,RMC) + [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, + {DRINTN_, 0xfc0001ff, 0xec0001c7, 0x1e0000, // DFP Round To FP Integer Without Inexact [Quad] Z23-form (drintn. R,FRT,FRB,RMC) + [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, + {DCTDP, 0xfc0007ff, 0xec000204, 0x1f0000, // DFP Convert To DFP Long X-form (dctdp FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DCTDP_, 0xfc0007ff, 0xec000205, 0x1f0000, // DFP Convert To DFP Long X-form (dctdp. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DCTQPQ, 0xfc0007ff, 0xfc000204, 0x1f0000, // DFP Convert To DFP Extended X-form (dctqpq FRTp,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DCTQPQ_, 0xfc0007ff, 0xfc000205, 0x1f0000, // DFP Convert To DFP Extended X-form (dctqpq. FRTp,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DRSP, 0xfc0007ff, 0xec000604, 0x1f0000, // DFP Round To DFP Short X-form (drsp FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DRSP_, 0xfc0007ff, 0xec000605, 0x1f0000, // DFP Round To DFP Short X-form (drsp. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DRDPQ, 0xfc0007ff, 0xfc000604, 0x1f0000, // DFP Round To DFP Long X-form (drdpq FRTp,FRBp) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DRDPQ_, 0xfc0007ff, 0xfc000605, 0x1f0000, // DFP Round To DFP Long X-form (drdpq. FRTp,FRBp) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DCFFIX, 0xfc0007ff, 0xec000644, 0x1f0000, // DFP Convert From Fixed X-form (dcffix FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DCFFIX_, 0xfc0007ff, 0xec000645, 0x1f0000, // DFP Convert From Fixed X-form (dcffix. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DCFFIXQ, 0xfc0007ff, 0xfc000644, 0x1f0000, // DFP Convert From Fixed Quad X-form (dcffixq FRTp,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DCFFIXQ_, 0xfc0007ff, 0xfc000645, 0x1f0000, // DFP Convert From Fixed Quad X-form (dcffixq. FRTp,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DCTFIX, 0xfc0007ff, 0xec000244, 0x1f0000, // DFP Convert To Fixed [Quad] X-form (dctfix FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DCTFIX_, 0xfc0007ff, 0xec000245, 0x1f0000, // DFP Convert To Fixed [Quad] X-form (dctfix. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DDEDPD, 0xfc0007ff, 0xec000284, 0x70000, // DFP Decode DPD To BCD [Quad] X-form (ddedpd SP,FRT,FRB) + [5]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}}, + {DDEDPD_, 0xfc0007ff, 0xec000285, 0x70000, // DFP Decode DPD To BCD [Quad] X-form (ddedpd. SP,FRT,FRB) + [5]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}}, + {DENBCD, 0xfc0007ff, 0xec000684, 0xf0000, // DFP Encode BCD To DPD [Quad] X-form (denbcd S,FRT,FRB) + [5]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}}, + {DENBCD_, 0xfc0007ff, 0xec000685, 0xf0000, // DFP Encode BCD To DPD [Quad] X-form (denbcd. S,FRT,FRB) + [5]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}}, + {DXEX, 0xfc0007ff, 0xec0002c4, 0x1f0000, // DFP Extract Biased Exponent [Quad] X-form (dxex FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DXEX_, 0xfc0007ff, 0xec0002c5, 0x1f0000, // DFP Extract Biased Exponent [Quad] X-form (dxex. FRT,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, + {DIEX, 0xfc0007ff, 0xec0006c4, 0x0, // DFP Insert Biased Exponent [Quad] X-form (diex FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DIEX_, 0xfc0007ff, 0xec0006c5, 0x0, // DFP Insert Biased Exponent [Quad] X-form (diex. FRT,FRA,FRB) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, + {DSCLI, 0xfc0003ff, 0xec000084, 0x0, // DFP Shift Significand Left Immediate [Quad] Z22-form (dscli FRT,FRA,SH) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, + {DSCLI_, 0xfc0003ff, 0xec000085, 0x0, // DFP Shift Significand Left Immediate [Quad] Z22-form (dscli. FRT,FRA,SH) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, + {DSCRI, 0xfc0003ff, 0xec0000c4, 0x0, // DFP Shift Significand Right Immediate [Quad] Z22-form (dscri FRT,FRA,SH) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, + {DSCRI_, 0xfc0003ff, 0xec0000c5, 0x0, // DFP Shift Significand Right Immediate [Quad] Z22-form (dscri. FRT,FRA,SH) + [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, + {LXSDX, 0xfc0007fe, 0x7c000498, 0x0, // Load VSX Scalar Doubleword Indexed XX1-form (lxsdx XT,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LXSIWAX, 0xfc0007fe, 0x7c000098, 0x0, // Load VSX Scalar as Integer Word Algebraic Indexed XX1-form (lxsiwax XT,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LXSIWZX, 0xfc0007fe, 0x7c000018, 0x0, // Load VSX Scalar as Integer Word and Zero Indexed XX1-form (lxsiwzx XT,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LXSSPX, 0xfc0007fe, 0x7c000418, 0x0, // Load VSX Scalar Single-Precision Indexed XX1-form (lxsspx XT,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LXVD2X, 0xfc0007fe, 0x7c000698, 0x0, // Load VSX Vector Doubleword*2 Indexed XX1-form (lxvd2x XT,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LXVDSX, 0xfc0007fe, 0x7c000298, 0x0, // Load VSX Vector Doubleword & Splat Indexed XX1-form (lxvdsx XT,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LXVW4X, 0xfc0007fe, 0x7c000618, 0x0, // Load VSX Vector Word*4 Indexed XX1-form (lxvw4x XT,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STXSDX, 0xfc0007fe, 0x7c000598, 0x0, // Store VSX Scalar Doubleword Indexed XX1-form (stxsdx XS,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STXSIWX, 0xfc0007fe, 0x7c000118, 0x0, // Store VSX Scalar as Integer Word Indexed XX1-form (stxsiwx XS,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STXSSPX, 0xfc0007fe, 0x7c000518, 0x0, // Store VSX Scalar Single-Precision Indexed XX1-form (stxsspx XS,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STXVD2X, 0xfc0007fe, 0x7c000798, 0x0, // Store VSX Vector Doubleword*2 Indexed XX1-form (stxvd2x XS,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STXVW4X, 0xfc0007fe, 0x7c000718, 0x0, // Store VSX Vector Word*4 Indexed XX1-form (stxvw4x XS,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {XSABSDP, 0xfc0007fc, 0xf0000564, 0x1f0000, // VSX Scalar Absolute Value Double-Precision XX2-form (xsabsdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSADDDP, 0xfc0007f8, 0xf0000100, 0x0, // VSX Scalar Add Double-Precision XX3-form (xsadddp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSADDSP, 0xfc0007f8, 0xf0000000, 0x0, // VSX Scalar Add Single-Precision XX3-form (xsaddsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSCMPODP, 0xfc0007f8, 0xf0000158, 0x600001, // VSX Scalar Compare Ordered Double-Precision XX3-form (xscmpodp BF,XA,XB) + [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSCMPUDP, 0xfc0007f8, 0xf0000118, 0x600001, // VSX Scalar Compare Unordered Double-Precision XX3-form (xscmpudp BF,XA,XB) + [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSCPSGNDP, 0xfc0007f8, 0xf0000580, 0x0, // VSX Scalar Copy Sign Double-Precision XX3-form (xscpsgndp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSCVDPSP, 0xfc0007fc, 0xf0000424, 0x1f0000, // VSX Scalar round Double-Precision to single-precision and Convert to Single-Precision format XX2-form (xscvdpsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSCVDPSPN, 0xfc0007fc, 0xf000042c, 0x1f0000, // VSX Scalar Convert Scalar Single-Precision to Vector Single-Precision format Non-signalling XX2-form (xscvdpspn XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSCVDPSXDS, 0xfc0007fc, 0xf0000560, 0x1f0000, // VSX Scalar truncate Double-Precision to integer and Convert to Signed Integer Doubleword format with Saturate XX2-form (xscvdpsxds XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSCVDPSXWS, 0xfc0007fc, 0xf0000160, 0x1f0000, // VSX Scalar truncate Double-Precision to integer and Convert to Signed Integer Word format with Saturate XX2-form (xscvdpsxws XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSCVDPUXDS, 0xfc0007fc, 0xf0000520, 0x1f0000, // VSX Scalar truncate Double-Precision integer and Convert to Unsigned Integer Doubleword format with Saturate XX2-form (xscvdpuxds XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSCVDPUXWS, 0xfc0007fc, 0xf0000120, 0x1f0000, // VSX Scalar truncate Double-Precision to integer and Convert to Unsigned Integer Word format with Saturate XX2-form (xscvdpuxws XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSCVSPDP, 0xfc0007fc, 0xf0000524, 0x1f0000, // VSX Scalar Convert Single-Precision to Double-Precision format XX2-form (xscvspdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSCVSPDPN, 0xfc0007fc, 0xf000052c, 0x1f0000, // VSX Scalar Convert Single-Precision to Double-Precision format Non-signalling XX2-form (xscvspdpn XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSCVSXDDP, 0xfc0007fc, 0xf00005e0, 0x1f0000, // VSX Scalar Convert Signed Integer Doubleword to floating-point format and round to Double-Precision format XX2-form (xscvsxddp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSCVSXDSP, 0xfc0007fc, 0xf00004e0, 0x1f0000, // VSX Scalar Convert Signed Integer Doubleword to floating-point format and round to Single-Precision XX2-form (xscvsxdsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSCVUXDDP, 0xfc0007fc, 0xf00005a0, 0x1f0000, // VSX Scalar Convert Unsigned Integer Doubleword to floating-point format and round to Double-Precision format XX2-form (xscvuxddp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSCVUXDSP, 0xfc0007fc, 0xf00004a0, 0x1f0000, // VSX Scalar Convert Unsigned Integer Doubleword to floating-point format and round to Single-Precision XX2-form (xscvuxdsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSDIVDP, 0xfc0007f8, 0xf00001c0, 0x0, // VSX Scalar Divide Double-Precision XX3-form (xsdivdp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSDIVSP, 0xfc0007f8, 0xf00000c0, 0x0, // VSX Scalar Divide Single-Precision XX3-form (xsdivsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSMADDADP, 0xfc0007f8, 0xf0000108, 0x0, // VSX Scalar Multiply-Add Double-Precision XX3-form (xsmaddadp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSMADDASP, 0xfc0007f8, 0xf0000008, 0x0, // VSX Scalar Multiply-Add Single-Precision XX3-form (xsmaddasp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSMAXDP, 0xfc0007f8, 0xf0000500, 0x0, // VSX Scalar Maximum Double-Precision XX3-form (xsmaxdp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSMINDP, 0xfc0007f8, 0xf0000540, 0x0, // VSX Scalar Minimum Double-Precision XX3-form (xsmindp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSMSUBADP, 0xfc0007f8, 0xf0000188, 0x0, // VSX Scalar Multiply-Subtract Double-Precision XX3-form (xsmsubadp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSMSUBASP, 0xfc0007f8, 0xf0000088, 0x0, // VSX Scalar Multiply-Subtract Single-Precision XX3-form (xsmsubasp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSMULDP, 0xfc0007f8, 0xf0000180, 0x0, // VSX Scalar Multiply Double-Precision XX3-form (xsmuldp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSMULSP, 0xfc0007f8, 0xf0000080, 0x0, // VSX Scalar Multiply Single-Precision XX3-form (xsmulsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSNABSDP, 0xfc0007fc, 0xf00005a4, 0x1f0000, // VSX Scalar Negative Absolute Value Double-Precision XX2-form (xsnabsdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSNEGDP, 0xfc0007fc, 0xf00005e4, 0x1f0000, // VSX Scalar Negate Double-Precision XX2-form (xsnegdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSNMADDADP, 0xfc0007f8, 0xf0000508, 0x0, // VSX Scalar Negative Multiply-Add Double-Precision XX3-form (xsnmaddadp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSNMADDASP, 0xfc0007f8, 0xf0000408, 0x0, // VSX Scalar Negative Multiply-Add Single-Precision XX3-form (xsnmaddasp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSNMSUBADP, 0xfc0007f8, 0xf0000588, 0x0, // VSX Scalar Negative Multiply-Subtract Double-Precision XX3-form (xsnmsubadp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSNMSUBASP, 0xfc0007f8, 0xf0000488, 0x0, // VSX Scalar Negative Multiply-Subtract Single-Precision XX3-form (xsnmsubasp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSRDPI, 0xfc0007fc, 0xf0000124, 0x1f0000, // VSX Scalar Round to Double-Precision Integer using round to Nearest Away XX2-form (xsrdpi XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSRDPIC, 0xfc0007fc, 0xf00001ac, 0x1f0000, // VSX Scalar Round to Double-Precision Integer exact using Current rounding mode XX2-form (xsrdpic XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSRDPIM, 0xfc0007fc, 0xf00001e4, 0x1f0000, // VSX Scalar Round to Double-Precision Integer using round toward -Infinity XX2-form (xsrdpim XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSRDPIP, 0xfc0007fc, 0xf00001a4, 0x1f0000, // VSX Scalar Round to Double-Precision Integer using round toward +Infinity XX2-form (xsrdpip XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSRDPIZ, 0xfc0007fc, 0xf0000164, 0x1f0000, // VSX Scalar Round to Double-Precision Integer using round toward Zero XX2-form (xsrdpiz XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSREDP, 0xfc0007fc, 0xf0000168, 0x1f0000, // VSX Scalar Reciprocal Estimate Double-Precision XX2-form (xsredp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSRESP, 0xfc0007fc, 0xf0000068, 0x1f0000, // VSX Scalar Reciprocal Estimate Single-Precision XX2-form (xsresp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSRSP, 0xfc0007fc, 0xf0000464, 0x1f0000, // VSX Scalar Round to Single-Precision XX2-form (xsrsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSRSQRTEDP, 0xfc0007fc, 0xf0000128, 0x1f0000, // VSX Scalar Reciprocal Square Root Estimate Double-Precision XX2-form (xsrsqrtedp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSRSQRTESP, 0xfc0007fc, 0xf0000028, 0x1f0000, // VSX Scalar Reciprocal Square Root Estimate Single-Precision XX2-form (xsrsqrtesp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSSQRTDP, 0xfc0007fc, 0xf000012c, 0x1f0000, // VSX Scalar Square Root Double-Precision XX2-form (xssqrtdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSSQRTSP, 0xfc0007fc, 0xf000002c, 0x1f0000, // VSX Scalar Square Root Single-Precision XX-form (xssqrtsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XSSUBDP, 0xfc0007f8, 0xf0000140, 0x0, // VSX Scalar Subtract Double-Precision XX3-form (xssubdp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSSUBSP, 0xfc0007f8, 0xf0000040, 0x0, // VSX Scalar Subtract Single-Precision XX3-form (xssubsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSTDIVDP, 0xfc0007f8, 0xf00001e8, 0x600001, // VSX Scalar Test for software Divide Double-Precision XX3-form (xstdivdp BF,XA,XB) + [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XSTSQRTDP, 0xfc0007fc, 0xf00001a8, 0x7f0001, // VSX Scalar Test for software Square Root Double-Precision XX2-form (xstsqrtdp BF,XB) + [5]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}}, + {XVABSDP, 0xfc0007fc, 0xf0000764, 0x1f0000, // VSX Vector Absolute Value Double-Precision XX2-form (xvabsdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVABSSP, 0xfc0007fc, 0xf0000664, 0x1f0000, // VSX Vector Absolute Value Single-Precision XX2-form (xvabssp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVADDDP, 0xfc0007f8, 0xf0000300, 0x0, // VSX Vector Add Double-Precision XX3-form (xvadddp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVADDSP, 0xfc0007f8, 0xf0000200, 0x0, // VSX Vector Add Single-Precision XX3-form (xvaddsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPEQDP, 0xfc0007f8, 0xf0000318, 0x0, // VSX Vector Compare Equal To Double-Precision [ & Record ] XX3-form (xvcmpeqdp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPEQDP_, 0xfc0007f8, 0xf0000718, 0x0, // VSX Vector Compare Equal To Double-Precision [ & Record ] XX3-form (xvcmpeqdp. XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPEQSP, 0xfc0007f8, 0xf0000218, 0x0, // VSX Vector Compare Equal To Single-Precision [ & Record ] XX3-form (xvcmpeqsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPEQSP_, 0xfc0007f8, 0xf0000618, 0x0, // VSX Vector Compare Equal To Single-Precision [ & Record ] XX3-form (xvcmpeqsp. XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPGEDP, 0xfc0007f8, 0xf0000398, 0x0, // VSX Vector Compare Greater Than or Equal To Double-Precision [ & Record ] XX3-form (xvcmpgedp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPGEDP_, 0xfc0007f8, 0xf0000798, 0x0, // VSX Vector Compare Greater Than or Equal To Double-Precision [ & Record ] XX3-form (xvcmpgedp. XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPGESP, 0xfc0007f8, 0xf0000298, 0x0, // VSX Vector Compare Greater Than or Equal To Single-Precision [ & record CR6 ] XX3-form (xvcmpgesp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPGESP_, 0xfc0007f8, 0xf0000698, 0x0, // VSX Vector Compare Greater Than or Equal To Single-Precision [ & record CR6 ] XX3-form (xvcmpgesp. XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPGTDP, 0xfc0007f8, 0xf0000358, 0x0, // VSX Vector Compare Greater Than Double-Precision [ & record CR6 ] XX3-form (xvcmpgtdp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPGTDP_, 0xfc0007f8, 0xf0000758, 0x0, // VSX Vector Compare Greater Than Double-Precision [ & record CR6 ] XX3-form (xvcmpgtdp. XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPGTSP, 0xfc0007f8, 0xf0000258, 0x0, // VSX Vector Compare Greater Than Single-Precision [ & record CR6 ] XX3-form (xvcmpgtsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCMPGTSP_, 0xfc0007f8, 0xf0000658, 0x0, // VSX Vector Compare Greater Than Single-Precision [ & record CR6 ] XX3-form (xvcmpgtsp. XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCPSGNDP, 0xfc0007f8, 0xf0000780, 0x0, // VSX Vector Copy Sign Double-Precision XX3-form (xvcpsgndp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCPSGNSP, 0xfc0007f8, 0xf0000680, 0x0, // VSX Vector Copy Sign Single-Precision XX3-form (xvcpsgnsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVCVDPSP, 0xfc0007fc, 0xf0000624, 0x1f0000, // VSX Vector round Double-Precision to single-precision and Convert to Single-Precision format XX2-form (xvcvdpsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVDPSXDS, 0xfc0007fc, 0xf0000760, 0x1f0000, // VSX Vector truncate Double-Precision to integer and Convert to Signed Integer Doubleword format with Saturate XX2-form (xvcvdpsxds XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVDPSXWS, 0xfc0007fc, 0xf0000360, 0x1f0000, // VSX Vector truncate Double-Precision to integer and Convert to Signed Integer Word format with Saturate XX2-form (xvcvdpsxws XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVDPUXDS, 0xfc0007fc, 0xf0000720, 0x1f0000, // VSX Vector truncate Double-Precision to integer and Convert to Unsigned Integer Doubleword format with Saturate XX2-form (xvcvdpuxds XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVDPUXWS, 0xfc0007fc, 0xf0000320, 0x1f0000, // VSX Vector truncate Double-Precision to integer and Convert to Unsigned Integer Word format with Saturate XX2-form (xvcvdpuxws XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVSPDP, 0xfc0007fc, 0xf0000724, 0x1f0000, // VSX Vector Convert Single-Precision to Double-Precision format XX2-form (xvcvspdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVSPSXDS, 0xfc0007fc, 0xf0000660, 0x1f0000, // VSX Vector truncate Single-Precision to integer and Convert to Signed Integer Doubleword format with Saturate XX2-form (xvcvspsxds XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVSPSXWS, 0xfc0007fc, 0xf0000260, 0x1f0000, // VSX Vector truncate Single-Precision to integer and Convert to Signed Integer Word format with Saturate XX2-form (xvcvspsxws XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVSPUXDS, 0xfc0007fc, 0xf0000620, 0x1f0000, // VSX Vector truncate Single-Precision to integer and Convert to Unsigned Integer Doubleword format with Saturate XX2-form (xvcvspuxds XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVSPUXWS, 0xfc0007fc, 0xf0000220, 0x1f0000, // VSX Vector truncate Single-Precision to integer and Convert to Unsigned Integer Word format with Saturate XX2-form (xvcvspuxws XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVSXDDP, 0xfc0007fc, 0xf00007e0, 0x1f0000, // VSX Vector Convert and round Signed Integer Doubleword to Double-Precision format XX2-form (xvcvsxddp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVSXDSP, 0xfc0007fc, 0xf00006e0, 0x1f0000, // VSX Vector Convert and round Signed Integer Doubleword to Single-Precision format XX2-form (xvcvsxdsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVSXWDP, 0xfc0007fc, 0xf00003e0, 0x1f0000, // VSX Vector Convert Signed Integer Word to Double-Precision format XX2-form (xvcvsxwdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVSXWSP, 0xfc0007fc, 0xf00002e0, 0x1f0000, // VSX Vector Convert and round Signed Integer Word to Single-Precision format XX2-form (xvcvsxwsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVUXDDP, 0xfc0007fc, 0xf00007a0, 0x1f0000, // VSX Vector Convert and round Unsigned Integer Doubleword to Double-Precision format XX2-form (xvcvuxddp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVUXDSP, 0xfc0007fc, 0xf00006a0, 0x1f0000, // VSX Vector Convert and round Unsigned Integer Doubleword to Single-Precision format XX2-form (xvcvuxdsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVUXWDP, 0xfc0007fc, 0xf00003a0, 0x1f0000, // VSX Vector Convert and round Unsigned Integer Word to Double-Precision format XX2-form (xvcvuxwdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVCVUXWSP, 0xfc0007fc, 0xf00002a0, 0x1f0000, // VSX Vector Convert and round Unsigned Integer Word to Single-Precision format XX2-form (xvcvuxwsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVDIVDP, 0xfc0007f8, 0xf00003c0, 0x0, // VSX Vector Divide Double-Precision XX3-form (xvdivdp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVDIVSP, 0xfc0007f8, 0xf00002c0, 0x0, // VSX Vector Divide Single-Precision XX3-form (xvdivsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVMADDADP, 0xfc0007f8, 0xf0000308, 0x0, // VSX Vector Multiply-Add Double-Precision XX3-form (xvmaddadp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVMADDASP, 0xfc0007f8, 0xf0000208, 0x0, // VSX Vector Multiply-Add Single-Precision XX3-form (xvmaddasp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVMAXDP, 0xfc0007f8, 0xf0000700, 0x0, // VSX Vector Maximum Double-Precision XX3-form (xvmaxdp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVMAXSP, 0xfc0007f8, 0xf0000600, 0x0, // VSX Vector Maximum Single-Precision XX3-form (xvmaxsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVMINDP, 0xfc0007f8, 0xf0000740, 0x0, // VSX Vector Minimum Double-Precision XX3-form (xvmindp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVMINSP, 0xfc0007f8, 0xf0000640, 0x0, // VSX Vector Minimum Single-Precision XX3-form (xvminsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVMSUBADP, 0xfc0007f8, 0xf0000388, 0x0, // VSX Vector Multiply-Subtract Double-Precision XX3-form (xvmsubadp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVMSUBASP, 0xfc0007f8, 0xf0000288, 0x0, // VSX Vector Multiply-Subtract Single-Precision XX3-form (xvmsubasp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVMULDP, 0xfc0007f8, 0xf0000380, 0x0, // VSX Vector Multiply Double-Precision XX3-form (xvmuldp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVMULSP, 0xfc0007f8, 0xf0000280, 0x0, // VSX Vector Multiply Single-Precision XX3-form (xvmulsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVNABSDP, 0xfc0007fc, 0xf00007a4, 0x1f0000, // VSX Vector Negative Absolute Value Double-Precision XX2-form (xvnabsdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVNABSSP, 0xfc0007fc, 0xf00006a4, 0x1f0000, // VSX Vector Negative Absolute Value Single-Precision XX2-form (xvnabssp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVNEGDP, 0xfc0007fc, 0xf00007e4, 0x1f0000, // VSX Vector Negate Double-Precision XX2-form (xvnegdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVNEGSP, 0xfc0007fc, 0xf00006e4, 0x1f0000, // VSX Vector Negate Single-Precision XX2-form (xvnegsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVNMADDADP, 0xfc0007f8, 0xf0000708, 0x0, // VSX Vector Negative Multiply-Add Double-Precision XX3-form (xvnmaddadp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVNMADDASP, 0xfc0007f8, 0xf0000608, 0x0, // VSX Vector Negative Multiply-Add Single-Precision XX3-form (xvnmaddasp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVNMSUBADP, 0xfc0007f8, 0xf0000788, 0x0, // VSX Vector Negative Multiply-Subtract Double-Precision XX3-form (xvnmsubadp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVNMSUBASP, 0xfc0007f8, 0xf0000688, 0x0, // VSX Vector Negative Multiply-Subtract Single-Precision XX3-form (xvnmsubasp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVRDPI, 0xfc0007fc, 0xf0000324, 0x1f0000, // VSX Vector Round to Double-Precision Integer using round to Nearest Away XX2-form (xvrdpi XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRDPIC, 0xfc0007fc, 0xf00003ac, 0x1f0000, // VSX Vector Round to Double-Precision Integer Exact using Current rounding mode XX2-form (xvrdpic XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRDPIM, 0xfc0007fc, 0xf00003e4, 0x1f0000, // VSX Vector Round to Double-Precision Integer using round toward -Infinity XX2-form (xvrdpim XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRDPIP, 0xfc0007fc, 0xf00003a4, 0x1f0000, // VSX Vector Round to Double-Precision Integer using round toward +Infinity XX2-form (xvrdpip XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRDPIZ, 0xfc0007fc, 0xf0000364, 0x1f0000, // VSX Vector Round to Double-Precision Integer using round toward Zero XX2-form (xvrdpiz XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVREDP, 0xfc0007fc, 0xf0000368, 0x1f0000, // VSX Vector Reciprocal Estimate Double-Precision XX2-form (xvredp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRESP, 0xfc0007fc, 0xf0000268, 0x1f0000, // VSX Vector Reciprocal Estimate Single-Precision XX2-form (xvresp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRSPI, 0xfc0007fc, 0xf0000224, 0x1f0000, // VSX Vector Round to Single-Precision Integer using round to Nearest Away XX2-form (xvrspi XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRSPIC, 0xfc0007fc, 0xf00002ac, 0x1f0000, // VSX Vector Round to Single-Precision Integer Exact using Current rounding mode XX2-form (xvrspic XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRSPIM, 0xfc0007fc, 0xf00002e4, 0x1f0000, // VSX Vector Round to Single-Precision Integer using round toward -Infinity XX2-form (xvrspim XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRSPIP, 0xfc0007fc, 0xf00002a4, 0x1f0000, // VSX Vector Round to Single-Precision Integer using round toward +Infinity XX2-form (xvrspip XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRSPIZ, 0xfc0007fc, 0xf0000264, 0x1f0000, // VSX Vector Round to Single-Precision Integer using round toward Zero XX2-form (xvrspiz XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRSQRTEDP, 0xfc0007fc, 0xf0000328, 0x1f0000, // VSX Vector Reciprocal Square Root Estimate Double-Precision XX2-form (xvrsqrtedp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVRSQRTESP, 0xfc0007fc, 0xf0000228, 0x1f0000, // VSX Vector Reciprocal Square Root Estimate Single-Precision XX2-form (xvrsqrtesp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVSQRTDP, 0xfc0007fc, 0xf000032c, 0x1f0000, // VSX Vector Square Root Double-Precision XX2-form (xvsqrtdp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVSQRTSP, 0xfc0007fc, 0xf000022c, 0x1f0000, // VSX Vector Square Root Single-Precision XX2-form (xvsqrtsp XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XVSUBDP, 0xfc0007f8, 0xf0000340, 0x0, // VSX Vector Subtract Double-Precision XX3-form (xvsubdp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVSUBSP, 0xfc0007f8, 0xf0000240, 0x0, // VSX Vector Subtract Single-Precision XX3-form (xvsubsp XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVTDIVDP, 0xfc0007f8, 0xf00003e8, 0x600001, // VSX Vector Test for software Divide Double-Precision XX3-form (xvtdivdp BF,XA,XB) + [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVTDIVSP, 0xfc0007f8, 0xf00002e8, 0x600001, // VSX Vector Test for software Divide Single-Precision XX3-form (xvtdivsp BF,XA,XB) + [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XVTSQRTDP, 0xfc0007fc, 0xf00003a8, 0x7f0001, // VSX Vector Test for software Square Root Double-Precision XX2-form (xvtsqrtdp BF,XB) + [5]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}}, + {XVTSQRTSP, 0xfc0007fc, 0xf00002a8, 0x7f0001, // VSX Vector Test for software Square Root Single-Precision XX2-form (xvtsqrtsp BF,XB) + [5]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}}, + {XXLAND, 0xfc0007f8, 0xf0000410, 0x0, // VSX Logical AND XX3-form (xxland XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XXLANDC, 0xfc0007f8, 0xf0000450, 0x0, // VSX Logical AND with Complement XX3-form (xxlandc XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XXLEQV, 0xfc0007f8, 0xf00005d0, 0x0, // VSX Logical Equivalence XX3-form (xxleqv XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XXLNAND, 0xfc0007f8, 0xf0000590, 0x0, // VSX Logical NAND XX3-form (xxlnand XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XXLORC, 0xfc0007f8, 0xf0000550, 0x0, // VSX Logical OR with Complement XX3-form (xxlorc XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XXLNOR, 0xfc0007f8, 0xf0000510, 0x0, // VSX Logical NOR XX3-form (xxlnor XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XXLOR, 0xfc0007f8, 0xf0000490, 0x0, // VSX Logical OR XX3-form (xxlor XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XXLXOR, 0xfc0007f8, 0xf00004d0, 0x0, // VSX Logical XOR XX3-form (xxlxor XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XXMRGHW, 0xfc0007f8, 0xf0000090, 0x0, // VSX Merge High Word XX3-form (xxmrghw XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XXMRGLW, 0xfc0007f8, 0xf0000190, 0x0, // VSX Merge Low Word XX3-form (xxmrglw XT,XA,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, + {XXPERMDI, 0xfc0004f8, 0xf0000050, 0x0, // VSX Permute Doubleword Immediate XX3-form (xxpermdi XT,XA,XB,DM) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_22_23}}, + {XXSEL, 0xfc000030, 0xf0000030, 0x0, // VSX Select XX4-form (xxsel XT,XA,XB,XC) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_VecSReg_28_28_21_25}}, + {XXSLDWI, 0xfc0004f8, 0xf0000010, 0x0, // VSX Shift Left Double by Word Immediate XX3-form (xxsldwi XT,XA,XB,SHW) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_22_23}}, + {XXSPLTW, 0xfc0007fc, 0xf0000290, 0x1c0000, // VSX Splat Word XX2-form (xxspltw XT,XB,UIM) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_14_15}}, + {BRINC, 0xfc0007ff, 0x1000020f, 0x0, // Bit Reversed Increment EVX-form (brinc RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVABS, 0xfc0007ff, 0x10000208, 0xf800, // Vector Absolute Value EVX-form (evabs RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVADDIW, 0xfc0007ff, 0x10000202, 0x0, // Vector Add Immediate Word EVX-form (evaddiw RT,RB,UI) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_11_15}}, + {EVADDSMIAAW, 0xfc0007ff, 0x100004c9, 0xf800, // Vector Add Signed, Modulo, Integer to Accumulator Word EVX-form (evaddsmiaaw RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVADDSSIAAW, 0xfc0007ff, 0x100004c1, 0xf800, // Vector Add Signed, Saturate, Integer to Accumulator Word EVX-form (evaddssiaaw RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVADDUMIAAW, 0xfc0007ff, 0x100004c8, 0xf800, // Vector Add Unsigned, Modulo, Integer to Accumulator Word EVX-form (evaddumiaaw RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVADDUSIAAW, 0xfc0007ff, 0x100004c0, 0xf800, // Vector Add Unsigned, Saturate, Integer to Accumulator Word EVX-form (evaddusiaaw RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVADDW, 0xfc0007ff, 0x10000200, 0x0, // Vector Add Word EVX-form (evaddw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVAND, 0xfc0007ff, 0x10000211, 0x0, // Vector AND EVX-form (evand RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVCMPEQ, 0xfc0007ff, 0x10000234, 0x600000, // Vector Compare Equal EVX-form (evcmpeq BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EVANDC, 0xfc0007ff, 0x10000212, 0x0, // Vector AND with Complement EVX-form (evandc RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVCMPGTS, 0xfc0007ff, 0x10000231, 0x600000, // Vector Compare Greater Than Signed EVX-form (evcmpgts BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EVCMPGTU, 0xfc0007ff, 0x10000230, 0x600000, // Vector Compare Greater Than Unsigned EVX-form (evcmpgtu BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EVCMPLTU, 0xfc0007ff, 0x10000232, 0x600000, // Vector Compare Less Than Unsigned EVX-form (evcmpltu BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EVCMPLTS, 0xfc0007ff, 0x10000233, 0x600000, // Vector Compare Less Than Signed EVX-form (evcmplts BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EVCNTLSW, 0xfc0007ff, 0x1000020e, 0xf800, // Vector Count Leading Signed Bits Word EVX-form (evcntlsw RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVCNTLZW, 0xfc0007ff, 0x1000020d, 0xf800, // Vector Count Leading Zeros Word EVX-form (evcntlzw RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVDIVWS, 0xfc0007ff, 0x100004c6, 0x0, // Vector Divide Word Signed EVX-form (evdivws RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVDIVWU, 0xfc0007ff, 0x100004c7, 0x0, // Vector Divide Word Unsigned EVX-form (evdivwu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVEQV, 0xfc0007ff, 0x10000219, 0x0, // Vector Equivalent EVX-form (eveqv RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVEXTSB, 0xfc0007ff, 0x1000020a, 0xf800, // Vector Extend Sign Byte EVX-form (evextsb RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVEXTSH, 0xfc0007ff, 0x1000020b, 0xf800, // Vector Extend Sign Halfword EVX-form (evextsh RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVLDD, 0xfc0007ff, 0x10000301, 0x0, // Vector Load Double Word into Double Word EVX-form (evldd RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVLDH, 0xfc0007ff, 0x10000305, 0x0, // Vector Load Double into Four Halfwords EVX-form (evldh RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVLDDX, 0xfc0007ff, 0x10000300, 0x0, // Vector Load Double Word into Double Word Indexed EVX-form (evlddx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLDHX, 0xfc0007ff, 0x10000304, 0x0, // Vector Load Double into Four Halfwords Indexed EVX-form (evldhx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLDW, 0xfc0007ff, 0x10000303, 0x0, // Vector Load Double into Two Words EVX-form (evldw RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVLHHESPLAT, 0xfc0007ff, 0x10000309, 0x0, // Vector Load Halfword into Halfwords Even and Splat EVX-form (evlhhesplat RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVLDWX, 0xfc0007ff, 0x10000302, 0x0, // Vector Load Double into Two Words Indexed EVX-form (evldwx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLHHESPLATX, 0xfc0007ff, 0x10000308, 0x0, // Vector Load Halfword into Halfwords Even and Splat Indexed EVX-form (evlhhesplatx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLHHOSSPLAT, 0xfc0007ff, 0x1000030f, 0x0, // Vector Load Halfword into Halfword Odd Signed and Splat EVX-form (evlhhossplat RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVLHHOUSPLAT, 0xfc0007ff, 0x1000030d, 0x0, // Vector Load Halfword into Halfword Odd Unsigned and Splat EVX-form (evlhhousplat RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVLHHOSSPLATX, 0xfc0007ff, 0x1000030e, 0x0, // Vector Load Halfword into Halfword Odd Signed and Splat Indexed EVX-form (evlhhossplatx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLHHOUSPLATX, 0xfc0007ff, 0x1000030c, 0x0, // Vector Load Halfword into Halfword Odd Unsigned and Splat Indexed EVX-form (evlhhousplatx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLWHE, 0xfc0007ff, 0x10000311, 0x0, // Vector Load Word into Two Halfwords Even EVX-form (evlwhe RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVLWHOS, 0xfc0007ff, 0x10000317, 0x0, // Vector Load Word into Two Halfwords Odd Signed (with sign extension) EVX-form (evlwhos RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVLWHEX, 0xfc0007ff, 0x10000310, 0x0, // Vector Load Word into Two Halfwords Even Indexed EVX-form (evlwhex RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLWHOSX, 0xfc0007ff, 0x10000316, 0x0, // Vector Load Word into Two Halfwords Odd Signed Indexed (with sign extension) EVX-form (evlwhosx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLWHOU, 0xfc0007ff, 0x10000315, 0x0, // Vector Load Word into Two Halfwords Odd Unsigned (zero-extended) EVX-form (evlwhou RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVLWHSPLAT, 0xfc0007ff, 0x1000031d, 0x0, // Vector Load Word into Two Halfwords and Splat EVX-form (evlwhsplat RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVLWHOUX, 0xfc0007ff, 0x10000314, 0x0, // Vector Load Word into Two Halfwords Odd Unsigned Indexed (zero-extended) EVX-form (evlwhoux RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLWHSPLATX, 0xfc0007ff, 0x1000031c, 0x0, // Vector Load Word into Two Halfwords and Splat Indexed EVX-form (evlwhsplatx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLWWSPLAT, 0xfc0007ff, 0x10000319, 0x0, // Vector Load Word into Word and Splat EVX-form (evlwwsplat RT,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVMERGEHI, 0xfc0007ff, 0x1000022c, 0x0, // Vector Merge High EVX-form (evmergehi RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLWWSPLATX, 0xfc0007ff, 0x10000318, 0x0, // Vector Load Word into Word and Splat Indexed EVX-form (evlwwsplatx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMERGELO, 0xfc0007ff, 0x1000022d, 0x0, // Vector Merge Low EVX-form (evmergelo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMERGEHILO, 0xfc0007ff, 0x1000022e, 0x0, // Vector Merge High/Low EVX-form (evmergehilo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEGSMFAA, 0xfc0007ff, 0x1000052b, 0x0, // Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Fractional and Accumulate EVX-form (evmhegsmfaa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMERGELOHI, 0xfc0007ff, 0x1000022f, 0x0, // Vector Merge Low/High EVX-form (evmergelohi RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEGSMFAN, 0xfc0007ff, 0x100005ab, 0x0, // Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Fractional and Accumulate Negative EVX-form (evmhegsmfan RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEGSMIAA, 0xfc0007ff, 0x10000529, 0x0, // Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Integer and Accumulate EVX-form (evmhegsmiaa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEGUMIAA, 0xfc0007ff, 0x10000528, 0x0, // Vector Multiply Halfwords, Even, Guarded, Unsigned, Modulo, Integer and Accumulate EVX-form (evmhegumiaa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEGSMIAN, 0xfc0007ff, 0x100005a9, 0x0, // Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Integer and Accumulate Negative EVX-form (evmhegsmian RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEGUMIAN, 0xfc0007ff, 0x100005a8, 0x0, // Vector Multiply Halfwords, Even, Guarded, Unsigned, Modulo, Integer and Accumulate Negative EVX-form (evmhegumian RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESMF, 0xfc0007ff, 0x1000040b, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Fractional EVX-form (evmhesmf RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESMFAAW, 0xfc0007ff, 0x1000050b, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Fractional and Accumulate into Words EVX-form (evmhesmfaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESMFA, 0xfc0007ff, 0x1000042b, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Fractional to Accumulator EVX-form (evmhesmfa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESMFANW, 0xfc0007ff, 0x1000058b, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Fractional and Accumulate Negative into Words EVX-form (evmhesmfanw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESMI, 0xfc0007ff, 0x10000409, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Integer EVX-form (evmhesmi RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESMIAAW, 0xfc0007ff, 0x10000509, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Integer and Accumulate into Words EVX-form (evmhesmiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESMIA, 0xfc0007ff, 0x10000429, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Integer to Accumulator EVX-form (evmhesmia RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESMIANW, 0xfc0007ff, 0x10000589, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Integer and Accumulate Negative into Words EVX-form (evmhesmianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESSF, 0xfc0007ff, 0x10000403, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Fractional EVX-form (evmhessf RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESSFA, 0xfc0007ff, 0x10000423, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Fractional to Accumulator EVX-form (evmhessfa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESSFAAW, 0xfc0007ff, 0x10000503, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Fractional and Accumulate into Words EVX-form (evmhessfaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESSFANW, 0xfc0007ff, 0x10000583, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Fractional and Accumulate Negative into Words EVX-form (evmhessfanw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESSIAAW, 0xfc0007ff, 0x10000501, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Integer and Accumulate into Words EVX-form (evmhessiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHESSIANW, 0xfc0007ff, 0x10000581, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Integer and Accumulate Negative into Words EVX-form (evmhessianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEUMI, 0xfc0007ff, 0x10000408, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer EVX-form (evmheumi RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEUMIAAW, 0xfc0007ff, 0x10000508, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer and Accumulate into Words EVX-form (evmheumiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEUMIA, 0xfc0007ff, 0x10000428, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer to Accumulator EVX-form (evmheumia RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEUMIANW, 0xfc0007ff, 0x10000588, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer and Accumulate Negative into Words EVX-form (evmheumianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEUSIAAW, 0xfc0007ff, 0x10000500, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Saturate, Integer and Accumulate into Words EVX-form (evmheusiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHEUSIANW, 0xfc0007ff, 0x10000580, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Saturate, Integer and Accumulate Negative into Words EVX-form (evmheusianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOGSMFAA, 0xfc0007ff, 0x1000052f, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Fractional and Accumulate EVX-form (evmhogsmfaa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOGSMIAA, 0xfc0007ff, 0x1000052d, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Integer and Accumulate EVX-form (evmhogsmiaa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOGSMFAN, 0xfc0007ff, 0x100005af, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Fractional and Accumulate Negative EVX-form (evmhogsmfan RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOGSMIAN, 0xfc0007ff, 0x100005ad, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Integer and Accumulate Negative EVX-form (evmhogsmian RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOGUMIAA, 0xfc0007ff, 0x1000052c, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Unsigned, Modulo, Integer and Accumulate EVX-form (evmhogumiaa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSMF, 0xfc0007ff, 0x1000040f, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional EVX-form (evmhosmf RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOGUMIAN, 0xfc0007ff, 0x100005ac, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Unsigned, Modulo, Integer and Accumulate Negative EVX-form (evmhogumian RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSMFA, 0xfc0007ff, 0x1000042f, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional to Accumulator EVX-form (evmhosmfa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSMFAAW, 0xfc0007ff, 0x1000050f, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional and Accumulate into Words EVX-form (evmhosmfaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSMI, 0xfc0007ff, 0x1000040d, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Integer EVX-form (evmhosmi RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSMFANW, 0xfc0007ff, 0x1000058f, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional and Accumulate Negative into Words EVX-form (evmhosmfanw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSMIA, 0xfc0007ff, 0x1000042d, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Integer to Accumulator EVX-form (evmhosmia RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSMIAAW, 0xfc0007ff, 0x1000050d, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Integer and Accumulate into Words EVX-form (evmhosmiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSMIANW, 0xfc0007ff, 0x1000058d, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Integer and Accumulate Negative into Words EVX-form (evmhosmianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSSF, 0xfc0007ff, 0x10000407, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional EVX-form (evmhossf RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSSFA, 0xfc0007ff, 0x10000427, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional to Accumulator EVX-form (evmhossfa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSSFAAW, 0xfc0007ff, 0x10000507, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional and Accumulate into Words EVX-form (evmhossfaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSSFANW, 0xfc0007ff, 0x10000587, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional and Accumulate Negative into Words EVX-form (evmhossfanw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSSIAAW, 0xfc0007ff, 0x10000505, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Integer and Accumulate into Words EVX-form (evmhossiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOUMI, 0xfc0007ff, 0x1000040c, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer EVX-form (evmhoumi RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOSSIANW, 0xfc0007ff, 0x10000585, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Integer and Accumulate Negative into Words EVX-form (evmhossianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOUMIA, 0xfc0007ff, 0x1000042c, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer to Accumulator EVX-form (evmhoumia RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOUMIAAW, 0xfc0007ff, 0x1000050c, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer and Accumulate into Words EVX-form (evmhoumiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOUSIAAW, 0xfc0007ff, 0x10000504, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Saturate, Integer and Accumulate into Words EVX-form (evmhousiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOUMIANW, 0xfc0007ff, 0x1000058c, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer and Accumulate Negative into Words EVX-form (evmhoumianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMHOUSIANW, 0xfc0007ff, 0x10000584, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Saturate, Integer and Accumulate Negative into Words EVX-form (evmhousianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMRA, 0xfc0007ff, 0x100004c4, 0xf800, // Initialize Accumulator EVX-form (evmra RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVMWHSMF, 0xfc0007ff, 0x1000044f, 0x0, // Vector Multiply Word High Signed, Modulo, Fractional EVX-form (evmwhsmf RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWHSMI, 0xfc0007ff, 0x1000044d, 0x0, // Vector Multiply Word High Signed, Modulo, Integer EVX-form (evmwhsmi RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWHSMFA, 0xfc0007ff, 0x1000046f, 0x0, // Vector Multiply Word High Signed, Modulo, Fractional to Accumulator EVX-form (evmwhsmfa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWHSMIA, 0xfc0007ff, 0x1000046d, 0x0, // Vector Multiply Word High Signed, Modulo, Integer to Accumulator EVX-form (evmwhsmia RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWHSSF, 0xfc0007ff, 0x10000447, 0x0, // Vector Multiply Word High Signed, Saturate, Fractional EVX-form (evmwhssf RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWHUMI, 0xfc0007ff, 0x1000044c, 0x0, // Vector Multiply Word High Unsigned, Modulo, Integer EVX-form (evmwhumi RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWHSSFA, 0xfc0007ff, 0x10000467, 0x0, // Vector Multiply Word High Signed, Saturate, Fractional to Accumulator EVX-form (evmwhssfa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWHUMIA, 0xfc0007ff, 0x1000046c, 0x0, // Vector Multiply Word High Unsigned, Modulo, Integer to Accumulator EVX-form (evmwhumia RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWLSMIAAW, 0xfc0007ff, 0x10000549, 0x0, // Vector Multiply Word Low Signed, Modulo, Integer and Accumulate into Words EVX-form (evmwlsmiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWLSSIAAW, 0xfc0007ff, 0x10000541, 0x0, // Vector Multiply Word Low Signed, Saturate, Integer and Accumulate into Words EVX-form (evmwlssiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWLSMIANW, 0xfc0007ff, 0x100005c9, 0x0, // Vector Multiply Word Low Signed, Modulo, Integer and Accumulate Negative in Words EVX-form (evmwlsmianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWLSSIANW, 0xfc0007ff, 0x100005c1, 0x0, // Vector Multiply Word Low Signed, Saturate, Integer and Accumulate Negative in Words EVX-form (evmwlssianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWLUMI, 0xfc0007ff, 0x10000448, 0x0, // Vector Multiply Word Low Unsigned, Modulo, Integer EVX-form (evmwlumi RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWLUMIAAW, 0xfc0007ff, 0x10000548, 0x0, // Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate into Words EVX-form (evmwlumiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWLUMIA, 0xfc0007ff, 0x10000468, 0x0, // Vector Multiply Word Low Unsigned, Modulo, Integer to Accumulator EVX-form (evmwlumia RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWLUMIANW, 0xfc0007ff, 0x100005c8, 0x0, // Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate Negative in Words EVX-form (evmwlumianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWLUSIAAW, 0xfc0007ff, 0x10000540, 0x0, // Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate into Words EVX-form (evmwlusiaaw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSMF, 0xfc0007ff, 0x1000045b, 0x0, // Vector Multiply Word Signed, Modulo, Fractional EVX-form (evmwsmf RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWLUSIANW, 0xfc0007ff, 0x100005c0, 0x0, // Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate Negative in Words EVX-form (evmwlusianw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSMFA, 0xfc0007ff, 0x1000047b, 0x0, // Vector Multiply Word Signed, Modulo, Fractional to Accumulator EVX-form (evmwsmfa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSMFAA, 0xfc0007ff, 0x1000055b, 0x0, // Vector Multiply Word Signed, Modulo, Fractional and Accumulate EVX-form (evmwsmfaa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSMI, 0xfc0007ff, 0x10000459, 0x0, // Vector Multiply Word Signed, Modulo, Integer EVX-form (evmwsmi RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSMIAA, 0xfc0007ff, 0x10000559, 0x0, // Vector Multiply Word Signed, Modulo, Integer and Accumulate EVX-form (evmwsmiaa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSMFAN, 0xfc0007ff, 0x100005db, 0x0, // Vector Multiply Word Signed, Modulo, Fractional and Accumulate Negative EVX-form (evmwsmfan RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSMIA, 0xfc0007ff, 0x10000479, 0x0, // Vector Multiply Word Signed, Modulo, Integer to Accumulator EVX-form (evmwsmia RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSMIAN, 0xfc0007ff, 0x100005d9, 0x0, // Vector Multiply Word Signed, Modulo, Integer and Accumulate Negative EVX-form (evmwsmian RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSSF, 0xfc0007ff, 0x10000453, 0x0, // Vector Multiply Word Signed, Saturate, Fractional EVX-form (evmwssf RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSSFA, 0xfc0007ff, 0x10000473, 0x0, // Vector Multiply Word Signed, Saturate, Fractional to Accumulator EVX-form (evmwssfa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSSFAA, 0xfc0007ff, 0x10000553, 0x0, // Vector Multiply Word Signed, Saturate, Fractional and Accumulate EVX-form (evmwssfaa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWUMI, 0xfc0007ff, 0x10000458, 0x0, // Vector Multiply Word Unsigned, Modulo, Integer EVX-form (evmwumi RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWSSFAN, 0xfc0007ff, 0x100005d3, 0x0, // Vector Multiply Word Signed, Saturate, Fractional and Accumulate Negative EVX-form (evmwssfan RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWUMIA, 0xfc0007ff, 0x10000478, 0x0, // Vector Multiply Word Unsigned, Modulo, Integer to Accumulator EVX-form (evmwumia RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWUMIAA, 0xfc0007ff, 0x10000558, 0x0, // Vector Multiply Word Unsigned, Modulo, Integer and Accumulate EVX-form (evmwumiaa RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVNAND, 0xfc0007ff, 0x1000021e, 0x0, // Vector NAND EVX-form (evnand RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVMWUMIAN, 0xfc0007ff, 0x100005d8, 0x0, // Vector Multiply Word Unsigned, Modulo, Integer and Accumulate Negative EVX-form (evmwumian RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVNEG, 0xfc0007ff, 0x10000209, 0xf800, // Vector Negate EVX-form (evneg RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVNOR, 0xfc0007ff, 0x10000218, 0x0, // Vector NOR EVX-form (evnor RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVORC, 0xfc0007ff, 0x1000021b, 0x0, // Vector OR with Complement EVX-form (evorc RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVOR, 0xfc0007ff, 0x10000217, 0x0, // Vector OR EVX-form (evor RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVRLW, 0xfc0007ff, 0x10000228, 0x0, // Vector Rotate Left Word EVX-form (evrlw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVRLWI, 0xfc0007ff, 0x1000022a, 0x0, // Vector Rotate Left Word Immediate EVX-form (evrlwi RT,RA,UI) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, + {EVSEL, 0xfc0007f8, 0x10000278, 0x0, // Vector Select EVS-form (evsel RT,RA,RB,BFA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_CondRegField_29_31}}, + {EVRNDW, 0xfc0007ff, 0x1000020c, 0xf800, // Vector Round Word EVX-form (evrndw RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVSLW, 0xfc0007ff, 0x10000224, 0x0, // Vector Shift Left Word EVX-form (evslw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSPLATFI, 0xfc0007ff, 0x1000022b, 0xf800, // Vector Splat Fractional Immediate EVX-form (evsplatfi RT,SI) + [5]*argField{ap_Reg_6_10, ap_ImmSigned_11_15}}, + {EVSRWIS, 0xfc0007ff, 0x10000223, 0x0, // Vector Shift Right Word Immediate Signed EVX-form (evsrwis RT,RA,UI) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, + {EVSLWI, 0xfc0007ff, 0x10000226, 0x0, // Vector Shift Left Word Immediate EVX-form (evslwi RT,RA,UI) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, + {EVSPLATI, 0xfc0007ff, 0x10000229, 0xf800, // Vector Splat Immediate EVX-form (evsplati RT,SI) + [5]*argField{ap_Reg_6_10, ap_ImmSigned_11_15}}, + {EVSRWIU, 0xfc0007ff, 0x10000222, 0x0, // Vector Shift Right Word Immediate Unsigned EVX-form (evsrwiu RT,RA,UI) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, + {EVSRWS, 0xfc0007ff, 0x10000221, 0x0, // Vector Shift Right Word Signed EVX-form (evsrws RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSTDD, 0xfc0007ff, 0x10000321, 0x0, // Vector Store Double of Double EVX-form (evstdd RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVSRWU, 0xfc0007ff, 0x10000220, 0x0, // Vector Shift Right Word Unsigned EVX-form (evsrwu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSTDDX, 0xfc0007ff, 0x10000320, 0x0, // Vector Store Double of Double Indexed EVX-form (evstddx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSTDH, 0xfc0007ff, 0x10000325, 0x0, // Vector Store Double of Four Halfwords EVX-form (evstdh RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVSTDW, 0xfc0007ff, 0x10000323, 0x0, // Vector Store Double of Two Words EVX-form (evstdw RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVSTDHX, 0xfc0007ff, 0x10000324, 0x0, // Vector Store Double of Four Halfwords Indexed EVX-form (evstdhx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSTDWX, 0xfc0007ff, 0x10000322, 0x0, // Vector Store Double of Two Words Indexed EVX-form (evstdwx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSTWHE, 0xfc0007ff, 0x10000331, 0x0, // Vector Store Word of Two Halfwords from Even EVX-form (evstwhe RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVSTWHO, 0xfc0007ff, 0x10000335, 0x0, // Vector Store Word of Two Halfwords from Odd EVX-form (evstwho RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVSTWWE, 0xfc0007ff, 0x10000339, 0x0, // Vector Store Word of Word from Even EVX-form (evstwwe RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVSTWHEX, 0xfc0007ff, 0x10000330, 0x0, // Vector Store Word of Two Halfwords from Even Indexed EVX-form (evstwhex RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSTWHOX, 0xfc0007ff, 0x10000334, 0x0, // Vector Store Word of Two Halfwords from Odd Indexed EVX-form (evstwhox RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSTWWEX, 0xfc0007ff, 0x10000338, 0x0, // Vector Store Word of Word from Even Indexed EVX-form (evstwwex RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSTWWO, 0xfc0007ff, 0x1000033d, 0x0, // Vector Store Word of Word from Odd EVX-form (evstwwo RS,D(RA)) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, + {EVSUBFSMIAAW, 0xfc0007ff, 0x100004cb, 0xf800, // Vector Subtract Signed, Modulo, Integer to Accumulator Word EVX-form (evsubfsmiaaw RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVSTWWOX, 0xfc0007ff, 0x1000033c, 0x0, // Vector Store Word of Word from Odd Indexed EVX-form (evstwwox RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSUBFSSIAAW, 0xfc0007ff, 0x100004c3, 0xf800, // Vector Subtract Signed, Saturate, Integer to Accumulator Word EVX-form (evsubfssiaaw RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVSUBFUMIAAW, 0xfc0007ff, 0x100004ca, 0xf800, // Vector Subtract Unsigned, Modulo, Integer to Accumulator Word EVX-form (evsubfumiaaw RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVSUBFUSIAAW, 0xfc0007ff, 0x100004c2, 0xf800, // Vector Subtract Unsigned, Saturate, Integer to Accumulator Word EVX-form (evsubfusiaaw RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVSUBFW, 0xfc0007ff, 0x10000204, 0x0, // Vector Subtract from Word EVX-form (evsubfw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSUBIFW, 0xfc0007ff, 0x10000206, 0x0, // Vector Subtract Immediate from Word EVX-form (evsubifw RT,UI,RB) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_11_15, ap_Reg_16_20}}, + {EVXOR, 0xfc0007ff, 0x10000216, 0x0, // Vector XOR EVX-form (evxor RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVFSABS, 0xfc0007ff, 0x10000284, 0xf800, // Vector Floating-Point Single-Precision Absolute Value EVX-form (evfsabs RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVFSNABS, 0xfc0007ff, 0x10000285, 0xf800, // Vector Floating-Point Single-Precision Negative Absolute Value EVX-form (evfsnabs RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVFSNEG, 0xfc0007ff, 0x10000286, 0xf800, // Vector Floating-Point Single-Precision Negate EVX-form (evfsneg RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EVFSADD, 0xfc0007ff, 0x10000280, 0x0, // Vector Floating-Point Single-Precision Add EVX-form (evfsadd RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVFSMUL, 0xfc0007ff, 0x10000288, 0x0, // Vector Floating-Point Single-Precision Multiply EVX-form (evfsmul RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVFSSUB, 0xfc0007ff, 0x10000281, 0x0, // Vector Floating-Point Single-Precision Subtract EVX-form (evfssub RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVFSDIV, 0xfc0007ff, 0x10000289, 0x0, // Vector Floating-Point Single-Precision Divide EVX-form (evfsdiv RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVFSCMPGT, 0xfc0007ff, 0x1000028c, 0x600000, // Vector Floating-Point Single-Precision Compare Greater Than EVX-form (evfscmpgt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EVFSCMPLT, 0xfc0007ff, 0x1000028d, 0x600000, // Vector Floating-Point Single-Precision Compare Less Than EVX-form (evfscmplt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EVFSCMPEQ, 0xfc0007ff, 0x1000028e, 0x600000, // Vector Floating-Point Single-Precision Compare Equal EVX-form (evfscmpeq BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EVFSTSTGT, 0xfc0007ff, 0x1000029c, 0x600000, // Vector Floating-Point Single-Precision Test Greater Than EVX-form (evfststgt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EVFSTSTLT, 0xfc0007ff, 0x1000029d, 0x600000, // Vector Floating-Point Single-Precision Test Less Than EVX-form (evfststlt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EVFSTSTEQ, 0xfc0007ff, 0x1000029e, 0x600000, // Vector Floating-Point Single-Precision Test Equal EVX-form (evfststeq BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EVFSCFSI, 0xfc0007ff, 0x10000291, 0x1f0000, // Vector Convert Floating-Point Single-Precision from Signed Integer EVX-form (evfscfsi RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EVFSCFSF, 0xfc0007ff, 0x10000293, 0x1f0000, // Vector Convert Floating-Point Single-Precision from Signed Fraction EVX-form (evfscfsf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EVFSCFUI, 0xfc0007ff, 0x10000290, 0x1f0000, // Vector Convert Floating-Point Single-Precision from Unsigned Integer EVX-form (evfscfui RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EVFSCFUF, 0xfc0007ff, 0x10000292, 0x1f0000, // Vector Convert Floating-Point Single-Precision from Unsigned Fraction EVX-form (evfscfuf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EVFSCTSI, 0xfc0007ff, 0x10000295, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Signed Integer EVX-form (evfsctsi RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EVFSCTUI, 0xfc0007ff, 0x10000294, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Unsigned Integer EVX-form (evfsctui RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EVFSCTSIZ, 0xfc0007ff, 0x1000029a, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Signed Integer with Round toward Zero EVX-form (evfsctsiz RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EVFSCTUIZ, 0xfc0007ff, 0x10000298, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Unsigned Integer with Round toward Zero EVX-form (evfsctuiz RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EVFSCTSF, 0xfc0007ff, 0x10000297, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Signed Fraction EVX-form (evfsctsf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EVFSCTUF, 0xfc0007ff, 0x10000296, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Unsigned Fraction EVX-form (evfsctuf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFSABS, 0xfc0007ff, 0x100002c4, 0xf800, // Floating-Point Single-Precision Absolute Value EVX-form (efsabs RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EFSNEG, 0xfc0007ff, 0x100002c6, 0xf800, // Floating-Point Single-Precision Negate EVX-form (efsneg RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EFSNABS, 0xfc0007ff, 0x100002c5, 0xf800, // Floating-Point Single-Precision Negative Absolute Value EVX-form (efsnabs RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EFSADD, 0xfc0007ff, 0x100002c0, 0x0, // Floating-Point Single-Precision Add EVX-form (efsadd RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EFSMUL, 0xfc0007ff, 0x100002c8, 0x0, // Floating-Point Single-Precision Multiply EVX-form (efsmul RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EFSSUB, 0xfc0007ff, 0x100002c1, 0x0, // Floating-Point Single-Precision Subtract EVX-form (efssub RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EFSDIV, 0xfc0007ff, 0x100002c9, 0x0, // Floating-Point Single-Precision Divide EVX-form (efsdiv RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EFSCMPGT, 0xfc0007ff, 0x100002cc, 0x600000, // Floating-Point Single-Precision Compare Greater Than EVX-form (efscmpgt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFSCMPLT, 0xfc0007ff, 0x100002cd, 0x600000, // Floating-Point Single-Precision Compare Less Than EVX-form (efscmplt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFSCMPEQ, 0xfc0007ff, 0x100002ce, 0x600000, // Floating-Point Single-Precision Compare Equal EVX-form (efscmpeq BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFSTSTGT, 0xfc0007ff, 0x100002dc, 0x600000, // Floating-Point Single-Precision Test Greater Than EVX-form (efststgt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFSTSTLT, 0xfc0007ff, 0x100002dd, 0x600000, // Floating-Point Single-Precision Test Less Than EVX-form (efststlt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFSTSTEQ, 0xfc0007ff, 0x100002de, 0x600000, // Floating-Point Single-Precision Test Equal EVX-form (efststeq BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFSCFSI, 0xfc0007ff, 0x100002d1, 0x1f0000, // Convert Floating-Point Single-Precision from Signed Integer EVX-form (efscfsi RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFSCFSF, 0xfc0007ff, 0x100002d3, 0x1f0000, // Convert Floating-Point Single-Precision from Signed Fraction EVX-form (efscfsf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFSCTSI, 0xfc0007ff, 0x100002d5, 0x1f0000, // Convert Floating-Point Single-Precision to Signed Integer EVX-form (efsctsi RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFSCFUI, 0xfc0007ff, 0x100002d0, 0x1f0000, // Convert Floating-Point Single-Precision from Unsigned Integer EVX-form (efscfui RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFSCFUF, 0xfc0007ff, 0x100002d2, 0x1f0000, // Convert Floating-Point Single-Precision from Unsigned Fraction EVX-form (efscfuf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFSCTUI, 0xfc0007ff, 0x100002d4, 0x1f0000, // Convert Floating-Point Single-Precision to Unsigned Integer EVX-form (efsctui RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFSCTSIZ, 0xfc0007ff, 0x100002da, 0x1f0000, // Convert Floating-Point Single-Precision to Signed Integer with Round toward Zero EVX-form (efsctsiz RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFSCTSF, 0xfc0007ff, 0x100002d7, 0x1f0000, // Convert Floating-Point Single-Precision to Signed Fraction EVX-form (efsctsf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFSCTUIZ, 0xfc0007ff, 0x100002d8, 0x1f0000, // Convert Floating-Point Single-Precision to Unsigned Integer with Round toward Zero EVX-form (efsctuiz RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFSCTUF, 0xfc0007ff, 0x100002d6, 0x1f0000, // Convert Floating-Point Single-Precision to Unsigned Fraction EVX-form (efsctuf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDABS, 0xfc0007ff, 0x100002e4, 0xf800, // Floating-Point Double-Precision Absolute Value EVX-form (efdabs RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EFDNEG, 0xfc0007ff, 0x100002e6, 0xf800, // Floating-Point Double-Precision Negate EVX-form (efdneg RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EFDNABS, 0xfc0007ff, 0x100002e5, 0xf800, // Floating-Point Double-Precision Negative Absolute Value EVX-form (efdnabs RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {EFDADD, 0xfc0007ff, 0x100002e0, 0x0, // Floating-Point Double-Precision Add EVX-form (efdadd RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EFDMUL, 0xfc0007ff, 0x100002e8, 0x0, // Floating-Point Double-Precision Multiply EVX-form (efdmul RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EFDSUB, 0xfc0007ff, 0x100002e1, 0x0, // Floating-Point Double-Precision Subtract EVX-form (efdsub RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EFDDIV, 0xfc0007ff, 0x100002e9, 0x0, // Floating-Point Double-Precision Divide EVX-form (efddiv RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EFDCMPGT, 0xfc0007ff, 0x100002ec, 0x600000, // Floating-Point Double-Precision Compare Greater Than EVX-form (efdcmpgt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFDCMPEQ, 0xfc0007ff, 0x100002ee, 0x600000, // Floating-Point Double-Precision Compare Equal EVX-form (efdcmpeq BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFDCMPLT, 0xfc0007ff, 0x100002ed, 0x600000, // Floating-Point Double-Precision Compare Less Than EVX-form (efdcmplt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFDTSTGT, 0xfc0007ff, 0x100002fc, 0x600000, // Floating-Point Double-Precision Test Greater Than EVX-form (efdtstgt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFDTSTLT, 0xfc0007ff, 0x100002fd, 0x600000, // Floating-Point Double-Precision Test Less Than EVX-form (efdtstlt BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFDCFSI, 0xfc0007ff, 0x100002f1, 0x1f0000, // Convert Floating-Point Double-Precision from Signed Integer EVX-form (efdcfsi RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDTSTEQ, 0xfc0007ff, 0x100002fe, 0x600000, // Floating-Point Double-Precision Test Equal EVX-form (efdtsteq BF,RA,RB) + [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, + {EFDCFUI, 0xfc0007ff, 0x100002f0, 0x1f0000, // Convert Floating-Point Double-Precision from Unsigned Integer EVX-form (efdcfui RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCFSID, 0xfc0007ff, 0x100002e3, 0x1f0000, // Convert Floating-Point Double-Precision from Signed Integer Doubleword EVX-form (efdcfsid RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCFSF, 0xfc0007ff, 0x100002f3, 0x1f0000, // Convert Floating-Point Double-Precision from Signed Fraction EVX-form (efdcfsf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCFUF, 0xfc0007ff, 0x100002f2, 0x1f0000, // Convert Floating-Point Double-Precision from Unsigned Fraction EVX-form (efdcfuf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCFUID, 0xfc0007ff, 0x100002e2, 0x1f0000, // Convert Floating-Point Double-Precision from Unsigned Integer Doubleword EVX-form (efdcfuid RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCTSI, 0xfc0007ff, 0x100002f5, 0x1f0000, // Convert Floating-Point Double-Precision to Signed Integer EVX-form (efdctsi RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCTUI, 0xfc0007ff, 0x100002f4, 0x1f0000, // Convert Floating-Point Double-Precision to Unsigned Integer EVX-form (efdctui RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCTSIDZ, 0xfc0007ff, 0x100002eb, 0x1f0000, // Convert Floating-Point Double-Precision to Signed Integer Doubleword with Round toward Zero EVX-form (efdctsidz RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCTUIDZ, 0xfc0007ff, 0x100002ea, 0x1f0000, // Convert Floating-Point Double-Precision to Unsigned Integer Doubleword with Round toward Zero EVX-form (efdctuidz RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCTSIZ, 0xfc0007ff, 0x100002fa, 0x1f0000, // Convert Floating-Point Double-Precision to Signed Integer with Round toward Zero EVX-form (efdctsiz RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCTSF, 0xfc0007ff, 0x100002f7, 0x1f0000, // Convert Floating-Point Double-Precision to Signed Fraction EVX-form (efdctsf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCTUF, 0xfc0007ff, 0x100002f6, 0x1f0000, // Convert Floating-Point Double-Precision to Unsigned Fraction EVX-form (efdctuf RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCTUIZ, 0xfc0007ff, 0x100002f8, 0x1f0000, // Convert Floating-Point Double-Precision to Unsigned Integer with Round toward Zero EVX-form (efdctuiz RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFDCFS, 0xfc0007ff, 0x100002ef, 0x1f0000, // Floating-Point Double-Precision Convert from Single-Precision EVX-form (efdcfs RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {EFSCFD, 0xfc0007ff, 0x100002cf, 0x1f0000, // Floating-Point Single-Precision Convert from Double-Precision EVX-form (efscfd RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {DLMZB, 0xfc0007ff, 0x7c00009c, 0x0, // Determine Leftmost Zero Byte X-form (dlmzb RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {DLMZB_, 0xfc0007ff, 0x7c00009d, 0x0, // Determine Leftmost Zero Byte X-form (dlmzb. RA,RS,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, + {MACCHW, 0xfc0007ff, 0x10000158, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHW_, 0xfc0007ff, 0x10000159, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWO, 0xfc0007ff, 0x10000558, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchwo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWO_, 0xfc0007ff, 0x10000559, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchwo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWS, 0xfc0007ff, 0x100001d8, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchws RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWS_, 0xfc0007ff, 0x100001d9, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchws. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWSO, 0xfc0007ff, 0x100005d8, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchwso RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWSO_, 0xfc0007ff, 0x100005d9, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchwso. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWU, 0xfc0007ff, 0x10000118, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWU_, 0xfc0007ff, 0x10000119, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWUO, 0xfc0007ff, 0x10000518, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwuo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWUO_, 0xfc0007ff, 0x10000519, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwuo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWSU, 0xfc0007ff, 0x10000198, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWSU_, 0xfc0007ff, 0x10000199, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWSUO, 0xfc0007ff, 0x10000598, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsuo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACCHWSUO_, 0xfc0007ff, 0x10000599, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsuo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHW, 0xfc0007ff, 0x10000058, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHW_, 0xfc0007ff, 0x10000059, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWO, 0xfc0007ff, 0x10000458, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhwo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWO_, 0xfc0007ff, 0x10000459, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhwo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWS, 0xfc0007ff, 0x100000d8, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhws RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWS_, 0xfc0007ff, 0x100000d9, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhws. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWSO, 0xfc0007ff, 0x100004d8, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhwso RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWSO_, 0xfc0007ff, 0x100004d9, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhwso. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWU, 0xfc0007ff, 0x10000018, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWU_, 0xfc0007ff, 0x10000019, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWUO, 0xfc0007ff, 0x10000418, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwuo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWUO_, 0xfc0007ff, 0x10000419, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwuo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWSU, 0xfc0007ff, 0x10000098, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWSU_, 0xfc0007ff, 0x10000099, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWSUO, 0xfc0007ff, 0x10000498, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsuo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACHHWSUO_, 0xfc0007ff, 0x10000499, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsuo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHW, 0xfc0007ff, 0x10000358, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHW_, 0xfc0007ff, 0x10000359, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWO, 0xfc0007ff, 0x10000758, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhwo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWO_, 0xfc0007ff, 0x10000759, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhwo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWS, 0xfc0007ff, 0x100003d8, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhws RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWS_, 0xfc0007ff, 0x100003d9, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhws. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWSO, 0xfc0007ff, 0x100007d8, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhwso RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWSO_, 0xfc0007ff, 0x100007d9, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhwso. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWU, 0xfc0007ff, 0x10000318, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWU_, 0xfc0007ff, 0x10000319, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWUO, 0xfc0007ff, 0x10000718, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwuo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWUO_, 0xfc0007ff, 0x10000719, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwuo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULCHW, 0xfc0007ff, 0x10000150, 0x0, // Multiply Cross Halfword to Word Signed X-form (mulchw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULCHW_, 0xfc0007ff, 0x10000151, 0x0, // Multiply Cross Halfword to Word Signed X-form (mulchw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWSU, 0xfc0007ff, 0x10000398, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWSU_, 0xfc0007ff, 0x10000399, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWSUO, 0xfc0007ff, 0x10000798, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsuo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MACLHWSUO_, 0xfc0007ff, 0x10000799, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsuo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULCHWU, 0xfc0007ff, 0x10000110, 0x0, // Multiply Cross Halfword to Word Unsigned X-form (mulchwu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULCHWU_, 0xfc0007ff, 0x10000111, 0x0, // Multiply Cross Halfword to Word Unsigned X-form (mulchwu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHHW, 0xfc0007ff, 0x10000050, 0x0, // Multiply High Halfword to Word Signed X-form (mulhhw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHHW_, 0xfc0007ff, 0x10000051, 0x0, // Multiply High Halfword to Word Signed X-form (mulhhw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULLHW, 0xfc0007ff, 0x10000350, 0x0, // Multiply Low Halfword to Word Signed X-form (mullhw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULLHW_, 0xfc0007ff, 0x10000351, 0x0, // Multiply Low Halfword to Word Signed X-form (mullhw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHHWU, 0xfc0007ff, 0x10000010, 0x0, // Multiply High Halfword to Word Unsigned X-form (mulhhwu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULHHWU_, 0xfc0007ff, 0x10000011, 0x0, // Multiply High Halfword to Word Unsigned X-form (mulhhwu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULLHWU, 0xfc0007ff, 0x10000310, 0x0, // Multiply Low Halfword to Word Unsigned X-form (mullhwu RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {MULLHWU_, 0xfc0007ff, 0x10000311, 0x0, // Multiply Low Halfword to Word Unsigned X-form (mullhwu. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACCHW, 0xfc0007ff, 0x1000015c, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACCHW_, 0xfc0007ff, 0x1000015d, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACCHWO, 0xfc0007ff, 0x1000055c, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchwo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACCHWO_, 0xfc0007ff, 0x1000055d, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchwo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACCHWS, 0xfc0007ff, 0x100001dc, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchws RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACCHWS_, 0xfc0007ff, 0x100001dd, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchws. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACCHWSO, 0xfc0007ff, 0x100005dc, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchwso RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACCHWSO_, 0xfc0007ff, 0x100005dd, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchwso. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACHHW, 0xfc0007ff, 0x1000005c, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACHHW_, 0xfc0007ff, 0x1000005d, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACHHWO, 0xfc0007ff, 0x1000045c, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhwo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACHHWO_, 0xfc0007ff, 0x1000045d, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhwo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACHHWS, 0xfc0007ff, 0x100000dc, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhws RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACHHWS_, 0xfc0007ff, 0x100000dd, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhws. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACHHWSO, 0xfc0007ff, 0x100004dc, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhwso RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACHHWSO_, 0xfc0007ff, 0x100004dd, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhwso. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACLHW, 0xfc0007ff, 0x1000035c, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhw RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACLHW_, 0xfc0007ff, 0x1000035d, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhw. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACLHWO, 0xfc0007ff, 0x1000075c, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhwo RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACLHWO_, 0xfc0007ff, 0x1000075d, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhwo. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACLHWS, 0xfc0007ff, 0x100003dc, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhws RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACLHWS_, 0xfc0007ff, 0x100003dd, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhws. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACLHWSO, 0xfc0007ff, 0x100007dc, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhwso RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {NMACLHWSO_, 0xfc0007ff, 0x100007dd, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhwso. RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ICBI, 0xfc0007fe, 0x7c0007ac, 0x3e00001, // Instruction Cache Block Invalidate X-form (icbi RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {ICBT, 0xfc0007fe, 0x7c00002c, 0x2000001, // Instruction Cache Block Touch X-form (icbt CT, RA, RB) + [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DCBA, 0xfc0007fe, 0x7c0005ec, 0x3e00001, // Data Cache Block Allocate X-form (dcba RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {DCBT, 0xfc0007fe, 0x7c00022c, 0x1, // Data Cache Block Touch X-form (dcbt RA,RB,TH) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_6_10}}, + {DCBT, 0xfc0007fe, 0x7c00022c, 0x1, // Data Cache Block Touch X-form (dcbt TH,RA,RB) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DCBTST, 0xfc0007fe, 0x7c0001ec, 0x1, // Data Cache Block Touch for Store X-form (dcbtst RA,RB,TH) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_6_10}}, + {DCBTST, 0xfc0007fe, 0x7c0001ec, 0x1, // Data Cache Block Touch for Store X-form (dcbtst TH,RA,RB) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DCBZ, 0xfc0007fe, 0x7c0007ec, 0x3e00001, // Data Cache Block set to Zero X-form (dcbz RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {DCBST, 0xfc0007fe, 0x7c00006c, 0x3e00001, // Data Cache Block Store X-form (dcbst RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {DCBF, 0xfc0007fe, 0x7c0000ac, 0x3800001, // Data Cache Block Flush X-form (dcbf RA,RB,L) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_9_10}}, + {ISYNC, 0xfc0007fe, 0x4c00012c, 0x3fff801, // Instruction Synchronize XL-form (isync) + [5]*argField{}}, + {LBARX, 0xfc0007ff, 0x7c000068, 0x0, // Load Byte And Reserve Indexed X-form [Category: Phased-In] (lbarx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LBARX, 0xfc0007fe, 0x7c000068, 0x0, // Load Byte And Reserve Indexed X-form [Category: Phased-In] (lbarx RT,RA,RB,EH) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}}, + {LHARX, 0xfc0007ff, 0x7c0000e8, 0x0, // Load Halfword And Reserve Indexed X-form [Category: Phased-In] (lharx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LHARX, 0xfc0007fe, 0x7c0000e8, 0x0, // Load Halfword And Reserve Indexed X-form [Category: Phased-In] (lharx RT,RA,RB,EH) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}}, + {LWARX, 0xfc0007ff, 0x7c000028, 0x0, // Load Word And Reserve Indexed X-form (lwarx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LWARX, 0xfc0007ff, 0x7c000028, 0x0, // Load Word And Reserve Indexed X-form (lwarx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LWARX, 0xfc0007fe, 0x7c000028, 0x0, // Load Word And Reserve Indexed X-form (lwarx RT,RA,RB,EH) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}}, + {STBCX_, 0xfc0007ff, 0x7c00056d, 0x0, // Store Byte Conditional Indexed X-form [Category: Phased-In] (stbcx. RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STHCX_, 0xfc0007ff, 0x7c0005ad, 0x0, // Store Halfword Conditional Indexed X-form [Category: Phased-In] (sthcx. RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STWCX_, 0xfc0007ff, 0x7c00012d, 0x0, // Store Word Conditional Indexed X-form (stwcx. RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LDARX, 0xfc0007ff, 0x7c0000a8, 0x0, // Load Doubleword And Reserve Indexed X-form (ldarx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LDARX, 0xfc0007fe, 0x7c0000a8, 0x0, // Load Doubleword And Reserve Indexed X-form (ldarx RT,RA,RB,EH) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}}, + {STDCX_, 0xfc0007ff, 0x7c0001ad, 0x0, // Store Doubleword Conditional Indexed X-form (stdcx. RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LQARX, 0xfc0007ff, 0x7c000228, 0x0, // Load Quadword And Reserve Indexed X-form (lqarx RTp,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LQARX, 0xfc0007fe, 0x7c000228, 0x0, // Load Quadword And Reserve Indexed X-form (lqarx RTp,RA,RB,EH) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}}, + {STQCX_, 0xfc0007ff, 0x7c00016d, 0x0, // Store Quadword Conditional Indexed X-form (stqcx. RSp,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SYNC, 0xfc0007fe, 0x7c0004ac, 0x390f801, // Synchronize X-form (sync L, E) + [5]*argField{ap_ImmUnsigned_9_10, ap_ImmUnsigned_12_15}}, + {EIEIO, 0xfc0007fe, 0x7c0006ac, 0x3fff801, // Enforce In-order Execution of I/O X-form (eieio) + [5]*argField{}}, + {MBAR, 0xfc0007fe, 0x7c0006ac, 0x1ff801, // Memory Barrier X-form (mbar MO) + [5]*argField{ap_ImmUnsigned_6_10}}, + {WAIT, 0xfc0007fe, 0x7c00007c, 0x39ff801, // Wait X-form (wait WC) + [5]*argField{ap_ImmUnsigned_9_10}}, + {TBEGIN_, 0xfc0007ff, 0x7c00051d, 0x1dff800, // Transaction Begin X-form (tbegin. R) + [5]*argField{ap_ImmUnsigned_10_10}}, + {TEND_, 0xfc0007ff, 0x7c00055d, 0x1fff800, // Transaction End X-form (tend. A) + [5]*argField{ap_ImmUnsigned_6_6}}, + {TABORT_, 0xfc0007ff, 0x7c00071d, 0x3e0f800, // Transaction Abort X-form (tabort. RA) + [5]*argField{ap_Reg_11_15}}, + {TABORTWC_, 0xfc0007ff, 0x7c00061d, 0x0, // Transaction Abort Word Conditional X-form (tabortwc. TO,RA,RB) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {TABORTWCI_, 0xfc0007ff, 0x7c00069d, 0x0, // Transaction Abort Word Conditional Immediate X-form (tabortwci. TO,RA,SI) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_20}}, + {TABORTDC_, 0xfc0007ff, 0x7c00065d, 0x0, // Transaction Abort Doubleword Conditional X-form (tabortdc. TO,RA,RB) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {TABORTDCI_, 0xfc0007ff, 0x7c0006dd, 0x0, // Transaction Abort Doubleword Conditional Immediate X-form (tabortdci. TO,RA, SI) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_20}}, + {TSR_, 0xfc0007ff, 0x7c0005dd, 0x3dff800, // Transaction Suspend or Resume X-form (tsr. L) + [5]*argField{ap_ImmUnsigned_10_10}}, + {TCHECK, 0xfc0007fe, 0x7c00059c, 0x7ff801, // Transaction Check X-form (tcheck BF) + [5]*argField{ap_CondRegField_6_8}}, + {MFTB, 0xfc0007fe, 0x7c0002e6, 0x1, // Move From Time Base XFX-form (mftb RT,TBR) + [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}}, + {RFEBB, 0xfc0007fe, 0x4c000124, 0x3fff001, // Return from Event-Based Branch XL-form (rfebb S) + [5]*argField{ap_ImmUnsigned_20_20}}, + {LBDX, 0xfc0007fe, 0x7c000406, 0x1, // Load Byte with Decoration Indexed X-form (lbdx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LHDX, 0xfc0007fe, 0x7c000446, 0x1, // Load Halfword with Decoration Indexed X-form (lhdx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LWDX, 0xfc0007fe, 0x7c000486, 0x1, // Load Word with Decoration Indexed X-form (lwdx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LDDX, 0xfc0007fe, 0x7c0004c6, 0x1, // Load Doubleword with Decoration Indexed X-form (lddx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LFDDX, 0xfc0007fe, 0x7c000646, 0x1, // Load Floating Doubleword with Decoration Indexed X-form (lfddx FRT,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STBDX, 0xfc0007fe, 0x7c000506, 0x1, // Store Byte with Decoration Indexed X-form (stbdx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STHDX, 0xfc0007fe, 0x7c000546, 0x1, // Store Halfword with Decoration Indexed X-form (sthdx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STWDX, 0xfc0007fe, 0x7c000586, 0x1, // Store Word with Decoration Indexed X-form (stwdx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STDDX, 0xfc0007fe, 0x7c0005c6, 0x1, // Store Doubleword with Decoration Indexed X-form (stddx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STFDDX, 0xfc0007fe, 0x7c000746, 0x1, // Store Floating Doubleword with Decoration Indexed X-form (stfddx FRS,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DSN, 0xfc0007fe, 0x7c0003c6, 0x3e00001, // Decorated Storage Notify X-form (dsn RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {ECIWX, 0xfc0007fe, 0x7c00026c, 0x1, // External Control In Word Indexed X-form (eciwx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ECOWX, 0xfc0007fe, 0x7c00036c, 0x1, // External Control Out Word Indexed X-form (ecowx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {SC, 0xfc000002, 0x44000002, 0x3fff01d, // System Call SC-form (sc LEV) + [5]*argField{ap_ImmUnsigned_20_26}}, + {RFID, 0xfc0007fe, 0x4c000024, 0x3fff801, // Return From Interrupt Doubleword XL-form (rfid) + [5]*argField{}}, + {HRFID, 0xfc0007fe, 0x4c000224, 0x3fff801, // Hypervisor Return From Interrupt Doubleword XL-form (hrfid) + [5]*argField{}}, + {DOZE, 0xfc0007fe, 0x4c000324, 0x3fff801, // Doze XL-form (doze) + [5]*argField{}}, + {NAP, 0xfc0007fe, 0x4c000364, 0x3fff801, // Nap XL-form (nap) + [5]*argField{}}, + {SLEEP, 0xfc0007fe, 0x4c0003a4, 0x3fff801, // Sleep XL-form (sleep) + [5]*argField{}}, + {RVWINKLE, 0xfc0007fe, 0x4c0003e4, 0x3fff801, // Rip Van Winkle XL-form (rvwinkle) + [5]*argField{}}, + {LBZCIX, 0xfc0007fe, 0x7c0006aa, 0x1, // Load Byte and Zero Caching Inhibited Indexed X-form (lbzcix RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LWZCIX, 0xfc0007fe, 0x7c00062a, 0x1, // Load Word and Zero Caching Inhibited Indexed X-form (lwzcix RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LHZCIX, 0xfc0007fe, 0x7c00066a, 0x1, // Load Halfword and Zero Caching Inhibited Indexed X-form (lhzcix RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LDCIX, 0xfc0007fe, 0x7c0006ea, 0x1, // Load Doubleword Caching Inhibited Indexed X-form (ldcix RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STBCIX, 0xfc0007fe, 0x7c0007aa, 0x1, // Store Byte Caching Inhibited Indexed X-form (stbcix RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STWCIX, 0xfc0007fe, 0x7c00072a, 0x1, // Store Word Caching Inhibited Indexed X-form (stwcix RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STHCIX, 0xfc0007fe, 0x7c00076a, 0x1, // Store Halfword Caching Inhibited Indexed X-form (sthcix RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STDCIX, 0xfc0007fe, 0x7c0007ea, 0x1, // Store Doubleword Caching Inhibited Indexed X-form (stdcix RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {TRECLAIM_, 0xfc0007ff, 0x7c00075d, 0x3e0f800, // Transaction Reclaim X-form (treclaim. RA) + [5]*argField{ap_Reg_11_15}}, + {TRECHKPT_, 0xfc0007ff, 0x7c0007dd, 0x3fff800, // Transaction Recheckpoint X-form (trechkpt.) + [5]*argField{}}, + {MTSPR, 0xfc0007fe, 0x7c0003a6, 0x1, // Move To Special Purpose Register XFX-form (mtspr SPR,RS) + [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}}, + {MFSPR, 0xfc0007fe, 0x7c0002a6, 0x1, // Move From Special Purpose Register XFX-form (mfspr RT,SPR) + [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}}, + {MTMSR, 0xfc0007fe, 0x7c000124, 0x1ef801, // Move To Machine State Register X-form (mtmsr RS,L) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_15_15}}, + {MTMSRD, 0xfc0007fe, 0x7c000164, 0x1ef801, // Move To Machine State Register Doubleword X-form (mtmsrd RS,L) + [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_15_15}}, + {MFMSR, 0xfc0007fe, 0x7c0000a6, 0x1ff801, // Move From Machine State Register X-form (mfmsr RT) + [5]*argField{ap_Reg_6_10}}, + {SLBIE, 0xfc0007fe, 0x7c000364, 0x3ff0001, // SLB Invalidate Entry X-form (slbie RB) + [5]*argField{ap_Reg_16_20}}, + {SLBIA, 0xfc0007fe, 0x7c0003e4, 0x31ff801, // SLB Invalidate All X-form (slbia IH) + [5]*argField{ap_ImmUnsigned_8_10}}, + {SLBMTE, 0xfc0007fe, 0x7c000324, 0x1f0001, // SLB Move To Entry X-form (slbmte RS,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {SLBMFEV, 0xfc0007fe, 0x7c0006a6, 0x1f0001, // SLB Move From Entry VSID X-form (slbmfev RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {SLBMFEE, 0xfc0007fe, 0x7c000726, 0x1f0001, // SLB Move From Entry ESID X-form (slbmfee RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {SLBFEE_, 0xfc0007ff, 0x7c0007a7, 0x1f0000, // SLB Find Entry ESID X-form (slbfee. RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {MTSR, 0xfc0007fe, 0x7c0001a4, 0x10f801, // Move To Segment Register X-form (mtsr SR,RS) + [5]*argField{ap_SpReg_12_15, ap_Reg_6_10}}, + {MTSRIN, 0xfc0007fe, 0x7c0001e4, 0x1f0001, // Move To Segment Register Indirect X-form (mtsrin RS,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {MFSR, 0xfc0007fe, 0x7c0004a6, 0x10f801, // Move From Segment Register X-form (mfsr RT,SR) + [5]*argField{ap_Reg_6_10, ap_SpReg_12_15}}, + {MFSRIN, 0xfc0007fe, 0x7c000526, 0x1f0001, // Move From Segment Register Indirect X-form (mfsrin RT,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, + {TLBIE, 0xfc0007fe, 0x7c000264, 0x1f0001, // TLB Invalidate Entry X-form (tlbie RB,RS) + [5]*argField{ap_Reg_16_20, ap_Reg_6_10}}, + {TLBIEL, 0xfc0007fe, 0x7c000224, 0x3ff0001, // TLB Invalidate Entry Local X-form (tlbiel RB) + [5]*argField{ap_Reg_16_20}}, + {TLBIA, 0xfc0007fe, 0x7c0002e4, 0x3fff801, // TLB Invalidate All X-form (tlbia) + [5]*argField{}}, + {TLBSYNC, 0xfc0007fe, 0x7c00046c, 0x3fff801, // TLB Synchronize X-form (tlbsync) + [5]*argField{}}, + {MSGSND, 0xfc0007fe, 0x7c00019c, 0x3ff0001, // Message Send X-form (msgsnd RB) + [5]*argField{ap_Reg_16_20}}, + {MSGCLR, 0xfc0007fe, 0x7c0001dc, 0x3ff0001, // Message Clear X-form (msgclr RB) + [5]*argField{ap_Reg_16_20}}, + {MSGSNDP, 0xfc0007fe, 0x7c00011c, 0x3ff0001, // Message Send Privileged X-form (msgsndp RB) + [5]*argField{ap_Reg_16_20}}, + {MSGCLRP, 0xfc0007fe, 0x7c00015c, 0x3ff0001, // Message Clear Privileged X-form (msgclrp RB) + [5]*argField{ap_Reg_16_20}}, + {MTTMR, 0xfc0007fe, 0x7c0003dc, 0x1, // Move To Thread Management Register XFX-form (mttmr TMR,RS) + [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}}, + {SC, 0xfc000002, 0x44000002, 0x3fffffd, // System Call SC-form (sc) + [5]*argField{}}, + {RFI, 0xfc0007fe, 0x4c000064, 0x3fff801, // Return From Interrupt XL-form (rfi) + [5]*argField{}}, + {RFCI, 0xfc0007fe, 0x4c000066, 0x3fff801, // Return From Critical Interrupt XL-form (rfci) + [5]*argField{}}, + {RFDI, 0xfc0007fe, 0x4c00004e, 0x3fff801, // Return From Debug Interrupt X-form (rfdi) + [5]*argField{}}, + {RFMCI, 0xfc0007fe, 0x4c00004c, 0x3fff801, // Return From Machine Check Interrupt XL-form (rfmci) + [5]*argField{}}, + {RFGI, 0xfc0007fe, 0x4c0000cc, 0x3fff801, // Return From Guest Interrupt XL-form (rfgi) + [5]*argField{}}, + {EHPRIV, 0xfc0007fe, 0x7c00021c, 0x1, // Embedded Hypervisor Privilege XL-form (ehpriv OC) + [5]*argField{ap_ImmUnsigned_6_20}}, + {MTSPR, 0xfc0007fe, 0x7c0003a6, 0x1, // Move To Special Purpose Register XFX-form (mtspr SPR,RS) + [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}}, + {MFSPR, 0xfc0007fe, 0x7c0002a6, 0x1, // Move From Special Purpose Register XFX-form (mfspr RT,SPR) + [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}}, + {MTDCR, 0xfc0007fe, 0x7c000386, 0x1, // Move To Device Control Register XFX-form (mtdcr DCRN,RS) + [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}}, + {MTDCRX, 0xfc0007fe, 0x7c000306, 0xf801, // Move To Device Control Register Indexed X-form (mtdcrx RA,RS) + [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, + {MFDCR, 0xfc0007fe, 0x7c000286, 0x1, // Move From Device Control Register XFX-form (mfdcr RT,DCRN) + [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}}, + {MFDCRX, 0xfc0007fe, 0x7c000206, 0xf801, // Move From Device Control Register Indexed X-form (mfdcrx RT,RA) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, + {MTMSR, 0xfc0007fe, 0x7c000124, 0x1ff801, // Move To Machine State Register X-form (mtmsr RS) + [5]*argField{ap_Reg_6_10}}, + {MFMSR, 0xfc0007fe, 0x7c0000a6, 0x1ff801, // Move From Machine State Register X-form (mfmsr RT) + [5]*argField{ap_Reg_6_10}}, + {WRTEE, 0xfc0007fe, 0x7c000106, 0x1ff801, // Write MSR External Enable X-form (wrtee RS) + [5]*argField{ap_Reg_6_10}}, + {WRTEEI, 0xfc0007fe, 0x7c000146, 0x3ff7801, // Write MSR External Enable Immediate X-form (wrteei E) + [5]*argField{ap_ImmUnsigned_16_16}}, + {LBEPX, 0xfc0007fe, 0x7c0000be, 0x1, // Load Byte by External Process ID Indexed X-form (lbepx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LHEPX, 0xfc0007fe, 0x7c00023e, 0x1, // Load Halfword by External Process ID Indexed X-form (lhepx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LWEPX, 0xfc0007fe, 0x7c00003e, 0x1, // Load Word by External Process ID Indexed X-form (lwepx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LDEPX, 0xfc0007fe, 0x7c00003a, 0x1, // Load Doubleword by External Process ID Indexed X-form (ldepx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STBEPX, 0xfc0007fe, 0x7c0001be, 0x1, // Store Byte by External Process ID Indexed X-form (stbepx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STHEPX, 0xfc0007fe, 0x7c00033e, 0x1, // Store Halfword by External Process ID Indexed X-form (sthepx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STWEPX, 0xfc0007fe, 0x7c00013e, 0x1, // Store Word by External Process ID Indexed X-form (stwepx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STDEPX, 0xfc0007fe, 0x7c00013a, 0x1, // Store Doubleword by External Process ID Indexed X-form (stdepx RS,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DCBSTEP, 0xfc0007fe, 0x7c00007e, 0x3e00001, // Data Cache Block Store by External PID X-form (dcbstep RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {DCBTEP, 0xfc0007fe, 0x7c00027e, 0x1, // Data Cache Block Touch by External PID X-form (dcbtep TH,RA,RB) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DCBFEP, 0xfc0007fe, 0x7c0000fe, 0x3800001, // Data Cache Block Flush by External PID X-form (dcbfep RA,RB,L) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_9_10}}, + {DCBTSTEP, 0xfc0007fe, 0x7c0001fe, 0x1, // Data Cache Block Touch for Store by External PID X-form (dcbtstep TH,RA,RB) + [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ICBIEP, 0xfc0007fe, 0x7c0007be, 0x3e00001, // Instruction Cache Block Invalidate by External PID X-form (icbiep RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {DCBZEP, 0xfc0007fe, 0x7c0007fe, 0x3e00001, // Data Cache Block set to Zero by External PID X-form (dcbzep RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {LFDEPX, 0xfc0007fe, 0x7c0004be, 0x1, // Load Floating-Point Double by External Process ID Indexed X-form (lfdepx FRT,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STFDEPX, 0xfc0007fe, 0x7c0005be, 0x1, // Store Floating-Point Double by External Process ID Indexed X-form (stfdepx FRS,RA,RB) + [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVLDDEPX, 0xfc0007fe, 0x7c00063e, 0x1, // Vector Load Doubleword into Doubleword by External Process ID Indexed EVX-form (evlddepx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {EVSTDDEPX, 0xfc0007fe, 0x7c00073e, 0x1, // Vector Store Doubleword into Doubleword by External Process ID Indexed EVX-form (evstddepx RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LVEPX, 0xfc0007fe, 0x7c00024e, 0x1, // Load Vector by External Process ID Indexed X-form (lvepx VRT,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LVEPXL, 0xfc0007fe, 0x7c00020e, 0x1, // Load Vector by External Process ID Indexed LRU X-form (lvepxl VRT,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STVEPX, 0xfc0007fe, 0x7c00064e, 0x1, // Store Vector by External Process ID Indexed X-form (stvepx VRS,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STVEPXL, 0xfc0007fe, 0x7c00060e, 0x1, // Store Vector by External Process ID Indexed LRU X-form (stvepxl VRS,RA,RB) + [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DCBI, 0xfc0007fe, 0x7c0003ac, 0x3e00001, // Data Cache Block Invalidate X-form (dcbi RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {DCBLQ_, 0xfc0007ff, 0x7c00034d, 0x2000000, // Data Cache Block Lock Query X-form (dcblq. CT,RA,RB) + [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ICBLQ_, 0xfc0007ff, 0x7c00018d, 0x2000000, // Instruction Cache Block Lock Query X-form (icblq. CT,RA,RB) + [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DCBTLS, 0xfc0007fe, 0x7c00014c, 0x2000001, // Data Cache Block Touch and Lock Set X-form (dcbtls CT,RA,RB) + [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DCBTSTLS, 0xfc0007fe, 0x7c00010c, 0x2000001, // Data Cache Block Touch for Store and Lock Set X-form (dcbtstls CT,RA,RB) + [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ICBTLS, 0xfc0007fe, 0x7c0003cc, 0x2000001, // Instruction Cache Block Touch and Lock Set X-form (icbtls CT,RA,RB) + [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ICBLC, 0xfc0007fe, 0x7c0001cc, 0x2000001, // Instruction Cache Block Lock Clear X-form (icblc CT,RA,RB) + [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, + {DCBLC, 0xfc0007fe, 0x7c00030c, 0x2000001, // Data Cache Block Lock Clear X-form (dcblc CT,RA,RB) + [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, + {TLBIVAX, 0xfc0007fe, 0x7c000624, 0x3e00001, // TLB Invalidate Virtual Address Indexed X-form (tlbivax RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {TLBILX, 0xfc0007fe, 0x7c000024, 0x3800001, // TLB Invalidate Local Indexed X-form (tlbilx RA,RB]) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {TLBSX, 0xfc0007fe, 0x7c000724, 0x3e00001, // TLB Search Indexed X-form (tlbsx RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {TLBSRX_, 0xfc0007ff, 0x7c0006a5, 0x3e00000, // TLB Search and Reserve Indexed X-form (tlbsrx. RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {TLBRE, 0xfc0007fe, 0x7c000764, 0x3fff801, // TLB Read Entry X-form (tlbre) + [5]*argField{}}, + {TLBSYNC, 0xfc0007fe, 0x7c00046c, 0x3fff801, // TLB Synchronize X-form (tlbsync) + [5]*argField{}}, + {TLBWE, 0xfc0007fe, 0x7c0007a4, 0x3fff801, // TLB Write Entry X-form (tlbwe) + [5]*argField{}}, + {DNH, 0xfc0007fe, 0x4c00018c, 0x1, // Debugger Notify Halt XFX-form (dnh DUI,DUIS) + [5]*argField{ap_ImmUnsigned_6_10, ap_ImmUnsigned_11_20}}, + {MSGSND, 0xfc0007fe, 0x7c00019c, 0x3ff0001, // Message Send X-form (msgsnd RB) + [5]*argField{ap_Reg_16_20}}, + {MSGCLR, 0xfc0007fe, 0x7c0001dc, 0x3ff0001, // Message Clear X-form (msgclr RB) + [5]*argField{ap_Reg_16_20}}, + {DCI, 0xfc0007fe, 0x7c00038c, 0x21ff801, // Data Cache Invalidate X-form (dci CT) + [5]*argField{ap_ImmUnsigned_7_10}}, + {ICI, 0xfc0007fe, 0x7c00078c, 0x21ff801, // Instruction Cache Invalidate X-form (ici CT) + [5]*argField{ap_ImmUnsigned_7_10}}, + {DCREAD, 0xfc0007fe, 0x7c0003cc, 0x1, // Data Cache Read X-form (dcread RT,RA,RB) + [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {ICREAD, 0xfc0007fe, 0x7c0007cc, 0x3e00001, // Instruction Cache Read X-form (icread RA,RB) + [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, + {MFPMR, 0xfc0007fe, 0x7c00029c, 0x1, // Move From Performance Monitor Register XFX-form (mfpmr RT,PMRN) + [5]*argField{ap_Reg_6_10, ap_SpReg_11_20}}, + {MTPMR, 0xfc0007fe, 0x7c00039c, 0x1, // Move To Performance Monitor Register XFX-form (mtpmr PMRN,RS) + [5]*argField{ap_SpReg_11_20, ap_Reg_6_10}}, +} diff --git a/vendor/golang.org/x/arch/x86/x86asm/LICENSE b/vendor/golang.org/x/arch/x86/x86asm/LICENSE new file mode 100644 index 00000000..d29b3726 --- /dev/null +++ b/vendor/golang.org/x/arch/x86/x86asm/LICENSE @@ -0,0 +1,27 @@ +Copyright (c) 2015 The Go Authors. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met: + + * Redistributions of source code must retain the above copyright +notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above +copyright notice, this list of conditions and the following disclaimer +in the documentation and/or other materials provided with the +distribution. + * Neither the name of Google Inc. nor the names of its +contributors may be used to endorse or promote products derived from +this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/vendor/golang.org/x/arch/x86/x86asm/decode.go b/vendor/golang.org/x/arch/x86/x86asm/decode.go new file mode 100644 index 00000000..148870b7 --- /dev/null +++ b/vendor/golang.org/x/arch/x86/x86asm/decode.go @@ -0,0 +1,1724 @@ +// Copyright 2014 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// Table-driven decoding of x86 instructions. + +package x86asm + +import ( + "encoding/binary" + "errors" + "fmt" + "runtime" +) + +// Set trace to true to cause the decoder to print the PC sequence +// of the executed instruction codes. This is typically only useful +// when you are running a test of a single input case. +const trace = false + +// A decodeOp is a single instruction in the decoder bytecode program. +// +// The decodeOps correspond to consuming and conditionally branching +// on input bytes, consuming additional fields, and then interpreting +// consumed data as instruction arguments. The names of the xRead and xArg +// operations are taken from the Intel manual conventions, for example +// Volume 2, Section 3.1.1, page 487 of +// http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf +// +// The actual decoding program is generated by ../x86map. +// +// TODO(rsc): We may be able to merge various of the memory operands +// since we don't care about, say, the distinction between m80dec and m80bcd. +// Similarly, mm and mm1 have identical meaning, as do xmm and xmm1. + +type decodeOp uint16 + +const ( + xFail decodeOp = iota // invalid instruction (return) + xMatch // completed match + xJump // jump to pc + + xCondByte // switch on instruction byte value + xCondSlashR // read and switch on instruction /r value + xCondPrefix // switch on presence of instruction prefix + xCondIs64 // switch on 64-bit processor mode + xCondDataSize // switch on operand size + xCondAddrSize // switch on address size + xCondIsMem // switch on memory vs register argument + + xSetOp // set instruction opcode + + xReadSlashR // read /r + xReadIb // read ib + xReadIw // read iw + xReadId // read id + xReadIo // read io + xReadCb // read cb + xReadCw // read cw + xReadCd // read cd + xReadCp // read cp + xReadCm // read cm + + xArg1 // arg 1 + xArg3 // arg 3 + xArgAL // arg AL + xArgAX // arg AX + xArgCL // arg CL + xArgCR0dashCR7 // arg CR0-CR7 + xArgCS // arg CS + xArgDR0dashDR7 // arg DR0-DR7 + xArgDS // arg DS + xArgDX // arg DX + xArgEAX // arg EAX + xArgEDX // arg EDX + xArgES // arg ES + xArgFS // arg FS + xArgGS // arg GS + xArgImm16 // arg imm16 + xArgImm32 // arg imm32 + xArgImm64 // arg imm64 + xArgImm8 // arg imm8 + xArgImm8u // arg imm8 but record as unsigned + xArgImm16u // arg imm8 but record as unsigned + xArgM // arg m + xArgM128 // arg m128 + xArgM256 // arg m256 + xArgM1428byte // arg m14/28byte + xArgM16 // arg m16 + xArgM16and16 // arg m16&16 + xArgM16and32 // arg m16&32 + xArgM16and64 // arg m16&64 + xArgM16colon16 // arg m16:16 + xArgM16colon32 // arg m16:32 + xArgM16colon64 // arg m16:64 + xArgM16int // arg m16int + xArgM2byte // arg m2byte + xArgM32 // arg m32 + xArgM32and32 // arg m32&32 + xArgM32fp // arg m32fp + xArgM32int // arg m32int + xArgM512byte // arg m512byte + xArgM64 // arg m64 + xArgM64fp // arg m64fp + xArgM64int // arg m64int + xArgM8 // arg m8 + xArgM80bcd // arg m80bcd + xArgM80dec // arg m80dec + xArgM80fp // arg m80fp + xArgM94108byte // arg m94/108byte + xArgMm // arg mm + xArgMm1 // arg mm1 + xArgMm2 // arg mm2 + xArgMm2M64 // arg mm2/m64 + xArgMmM32 // arg mm/m32 + xArgMmM64 // arg mm/m64 + xArgMem // arg mem + xArgMoffs16 // arg moffs16 + xArgMoffs32 // arg moffs32 + xArgMoffs64 // arg moffs64 + xArgMoffs8 // arg moffs8 + xArgPtr16colon16 // arg ptr16:16 + xArgPtr16colon32 // arg ptr16:32 + xArgR16 // arg r16 + xArgR16op // arg r16 with +rw in opcode + xArgR32 // arg r32 + xArgR32M16 // arg r32/m16 + xArgR32M8 // arg r32/m8 + xArgR32op // arg r32 with +rd in opcode + xArgR64 // arg r64 + xArgR64M16 // arg r64/m16 + xArgR64op // arg r64 with +rd in opcode + xArgR8 // arg r8 + xArgR8op // arg r8 with +rb in opcode + xArgRAX // arg RAX + xArgRDX // arg RDX + xArgRM // arg r/m + xArgRM16 // arg r/m16 + xArgRM32 // arg r/m32 + xArgRM64 // arg r/m64 + xArgRM8 // arg r/m8 + xArgReg // arg reg + xArgRegM16 // arg reg/m16 + xArgRegM32 // arg reg/m32 + xArgRegM8 // arg reg/m8 + xArgRel16 // arg rel16 + xArgRel32 // arg rel32 + xArgRel8 // arg rel8 + xArgSS // arg SS + xArgST // arg ST, aka ST(0) + xArgSTi // arg ST(i) with +i in opcode + xArgSreg // arg Sreg + xArgTR0dashTR7 // arg TR0-TR7 + xArgXmm // arg xmm + xArgXMM0 // arg <XMM0> + xArgXmm1 // arg xmm1 + xArgXmm2 // arg xmm2 + xArgXmm2M128 // arg xmm2/m128 + xArgYmm2M256 // arg ymm2/m256 + xArgXmm2M16 // arg xmm2/m16 + xArgXmm2M32 // arg xmm2/m32 + xArgXmm2M64 // arg xmm2/m64 + xArgXmmM128 // arg xmm/m128 + xArgXmmM32 // arg xmm/m32 + xArgXmmM64 // arg xmm/m64 + xArgYmm1 // arg ymm1 + xArgRmf16 // arg r/m16 but force mod=3 + xArgRmf32 // arg r/m32 but force mod=3 + xArgRmf64 // arg r/m64 but force mod=3 +) + +// instPrefix returns an Inst describing just one prefix byte. +// It is only used if there is a prefix followed by an unintelligible +// or invalid instruction byte sequence. +func instPrefix(b byte, mode int) (Inst, error) { + // When tracing it is useful to see what called instPrefix to report an error. + if trace { + _, file, line, _ := runtime.Caller(1) + fmt.Printf("%s:%d\n", file, line) + } + p := Prefix(b) + switch p { + case PrefixDataSize: + if mode == 16 { + p = PrefixData32 + } else { + p = PrefixData16 + } + case PrefixAddrSize: + if mode == 32 { + p = PrefixAddr16 + } else { + p = PrefixAddr32 + } + } + // Note: using composite literal with Prefix key confuses 'bundle' tool. + inst := Inst{Len: 1} + inst.Prefix = Prefixes{p} + return inst, nil +} + +// truncated reports a truncated instruction. +// For now we use instPrefix but perhaps later we will return +// a specific error here. +func truncated(src []byte, mode int) (Inst, error) { + // return Inst{}, len(src), ErrTruncated + return instPrefix(src[0], mode) // too long +} + +// These are the errors returned by Decode. +var ( + ErrInvalidMode = errors.New("invalid x86 mode in Decode") + ErrTruncated = errors.New("truncated instruction") + ErrUnrecognized = errors.New("unrecognized instruction") +) + +// decoderCover records coverage information for which parts +// of the byte code have been executed. +// TODO(rsc): This is for testing. Only use this if a flag is given. +var decoderCover []bool + +// Decode decodes the leading bytes in src as a single instruction. +// The mode arguments specifies the assumed processor mode: +// 16, 32, or 64 for 16-, 32-, and 64-bit execution modes. +func Decode(src []byte, mode int) (inst Inst, err error) { + return decode1(src, mode, false) +} + +// decode1 is the implementation of Decode but takes an extra +// gnuCompat flag to cause it to change its behavior to mimic +// bugs (or at least unique features) of GNU libopcodes as used +// by objdump. We don't believe that logic is the right thing to do +// in general, but when testing against libopcodes it simplifies the +// comparison if we adjust a few small pieces of logic. +// The affected logic is in the conditional branch for "mandatory" prefixes, +// case xCondPrefix. +func decode1(src []byte, mode int, gnuCompat bool) (Inst, error) { + switch mode { + case 16, 32, 64: + // ok + // TODO(rsc): 64-bit mode not tested, probably not working. + default: + return Inst{}, ErrInvalidMode + } + + // Maximum instruction size is 15 bytes. + // If we need to read more, return 'truncated instruction. + if len(src) > 15 { + src = src[:15] + } + + var ( + // prefix decoding information + pos = 0 // position reading src + nprefix = 0 // number of prefixes + lockIndex = -1 // index of LOCK prefix in src and inst.Prefix + repIndex = -1 // index of REP/REPN prefix in src and inst.Prefix + segIndex = -1 // index of Group 2 prefix in src and inst.Prefix + dataSizeIndex = -1 // index of Group 3 prefix in src and inst.Prefix + addrSizeIndex = -1 // index of Group 4 prefix in src and inst.Prefix + rex Prefix // rex byte if present (or 0) + rexUsed Prefix // bits used in rex byte + rexIndex = -1 // index of rex byte + vex Prefix // use vex encoding + vexIndex = -1 // index of vex prefix + + addrMode = mode // address mode (width in bits) + dataMode = mode // operand mode (width in bits) + + // decoded ModR/M fields + haveModrm bool + modrm int + mod int + regop int + rm int + + // if ModR/M is memory reference, Mem form + mem Mem + haveMem bool + + // decoded SIB fields + haveSIB bool + sib int + scale int + index int + base int + displen int + dispoff int + + // decoded immediate values + imm int64 + imm8 int8 + immc int64 + immcpos int + + // output + opshift int + inst Inst + narg int // number of arguments written to inst + ) + + if mode == 64 { + dataMode = 32 + } + + // Prefixes are certainly the most complex and underspecified part of + // decoding x86 instructions. Although the manuals say things like + // up to four prefixes, one from each group, nearly everyone seems to + // agree that in practice as many prefixes as possible, including multiple + // from a particular group or repetitions of a given prefix, can be used on + // an instruction, provided the total instruction length including prefixes + // does not exceed the agreed-upon maximum of 15 bytes. + // Everyone also agrees that if one of these prefixes is the LOCK prefix + // and the instruction is not one of the instructions that can be used with + // the LOCK prefix or if the destination is not a memory operand, + // then the instruction is invalid and produces the #UD exception. + // However, that is the end of any semblance of agreement. + // + // What happens if prefixes are given that conflict with other prefixes? + // For example, the memory segment overrides CS, DS, ES, FS, GS, SS + // conflict with each other: only one segment can be in effect. + // Disassemblers seem to agree that later prefixes take priority over + // earlier ones. I have not taken the time to write assembly programs + // to check to see if the hardware agrees. + // + // What happens if prefixes are given that have no meaning for the + // specific instruction to which they are attached? It depends. + // If they really have no meaning, they are ignored. However, a future + // processor may assign a different meaning. As a disassembler, we + // don't really know whether we're seeing a meaningless prefix or one + // whose meaning we simply haven't been told yet. + // + // Combining the two questions, what happens when conflicting + // extension prefixes are given? No one seems to know for sure. + // For example, MOVQ is 66 0F D6 /r, MOVDQ2Q is F2 0F D6 /r, + // and MOVQ2DQ is F3 0F D6 /r. What is '66 F2 F3 0F D6 /r'? + // Which prefix wins? See the xCondPrefix prefix for more. + // + // Writing assembly test cases to divine which interpretation the + // CPU uses might clarify the situation, but more likely it would + // make the situation even less clear. + + // Read non-REX prefixes. +ReadPrefixes: + for ; pos < len(src); pos++ { + p := Prefix(src[pos]) + switch p { + default: + nprefix = pos + break ReadPrefixes + + // Group 1 - lock and repeat prefixes + // According to Intel, there should only be one from this set, + // but according to AMD both can be present. + case 0xF0: + if lockIndex >= 0 { + inst.Prefix[lockIndex] |= PrefixIgnored + } + lockIndex = pos + case 0xF2, 0xF3: + if repIndex >= 0 { + inst.Prefix[repIndex] |= PrefixIgnored + } + repIndex = pos + + // Group 2 - segment override / branch hints + case 0x26, 0x2E, 0x36, 0x3E: + if mode == 64 { + p |= PrefixIgnored + break + } + fallthrough + case 0x64, 0x65: + if segIndex >= 0 { + inst.Prefix[segIndex] |= PrefixIgnored + } + segIndex = pos + + // Group 3 - operand size override + case 0x66: + if mode == 16 { + dataMode = 32 + p = PrefixData32 + } else { + dataMode = 16 + p = PrefixData16 + } + if dataSizeIndex >= 0 { + inst.Prefix[dataSizeIndex] |= PrefixIgnored + } + dataSizeIndex = pos + + // Group 4 - address size override + case 0x67: + if mode == 32 { + addrMode = 16 + p = PrefixAddr16 + } else { + addrMode = 32 + p = PrefixAddr32 + } + if addrSizeIndex >= 0 { + inst.Prefix[addrSizeIndex] |= PrefixIgnored + } + addrSizeIndex = pos + + //Group 5 - Vex encoding + case 0xC5: + if pos == 0 && (mode == 64 || (mode == 32 && pos+1 < len(src) && src[pos+1]&0xc0 == 0xc0)) { + vex = p + vexIndex = pos + inst.Prefix[pos] = p + inst.Prefix[pos+1] = Prefix(src[pos+1]) + pos += 1 + continue + } else { + nprefix = pos + break ReadPrefixes + } + case 0xC4: + if pos == 0 && (mode == 64 || (mode == 32 && pos+2 < len(src) && src[pos+1]&0xc0 == 0xc0)) { + vex = p + vexIndex = pos + inst.Prefix[pos] = p + inst.Prefix[pos+1] = Prefix(src[pos+1]) + inst.Prefix[pos+2] = Prefix(src[pos+2]) + pos += 2 + continue + } else { + nprefix = pos + break ReadPrefixes + } + } + + if pos >= len(inst.Prefix) { + return instPrefix(src[0], mode) // too long + } + + inst.Prefix[pos] = p + } + + // Read REX prefix. + if pos < len(src) && mode == 64 && Prefix(src[pos]).IsREX() && vex == 0 { + rex = Prefix(src[pos]) + rexIndex = pos + if pos >= len(inst.Prefix) { + return instPrefix(src[0], mode) // too long + } + inst.Prefix[pos] = rex + pos++ + if rex&PrefixREXW != 0 { + dataMode = 64 + if dataSizeIndex >= 0 { + inst.Prefix[dataSizeIndex] |= PrefixIgnored + } + } + } + + // Decode instruction stream, interpreting decoding instructions. + // opshift gives the shift to use when saving the next + // opcode byte into inst.Opcode. + opshift = 24 + if decoderCover == nil { + decoderCover = make([]bool, len(decoder)) + } + + // Decode loop, executing decoder program. + var oldPC, prevPC int +Decode: + for pc := 1; ; { // TODO uint + oldPC = prevPC + prevPC = pc + if trace { + println("run", pc) + } + x := decoder[pc] + decoderCover[pc] = true + pc++ + + // Read and decode ModR/M if needed by opcode. + switch decodeOp(x) { + case xCondSlashR, xReadSlashR: + if haveModrm { + return Inst{Len: pos}, errInternal + } + haveModrm = true + if pos >= len(src) { + return truncated(src, mode) + } + modrm = int(src[pos]) + pos++ + if opshift >= 0 { + inst.Opcode |= uint32(modrm) << uint(opshift) + opshift -= 8 + } + mod = modrm >> 6 + regop = (modrm >> 3) & 07 + rm = modrm & 07 + if rex&PrefixREXR != 0 { + rexUsed |= PrefixREXR + regop |= 8 + } + if addrMode == 16 { + // 16-bit modrm form + if mod != 3 { + haveMem = true + mem = addr16[rm] + if rm == 6 && mod == 0 { + mem.Base = 0 + } + + // Consume disp16 if present. + if mod == 0 && rm == 6 || mod == 2 { + if pos+2 > len(src) { + return truncated(src, mode) + } + mem.Disp = int64(binary.LittleEndian.Uint16(src[pos:])) + pos += 2 + } + + // Consume disp8 if present. + if mod == 1 { + if pos >= len(src) { + return truncated(src, mode) + } + mem.Disp = int64(int8(src[pos])) + pos++ + } + } + } else { + haveMem = mod != 3 + + // 32-bit or 64-bit form + // Consume SIB encoding if present. + if rm == 4 && mod != 3 { + haveSIB = true + if pos >= len(src) { + return truncated(src, mode) + } + sib = int(src[pos]) + pos++ + if opshift >= 0 { + inst.Opcode |= uint32(sib) << uint(opshift) + opshift -= 8 + } + scale = sib >> 6 + index = (sib >> 3) & 07 + base = sib & 07 + if rex&PrefixREXB != 0 || vex == 0xC4 && inst.Prefix[vexIndex+1]&0x20 == 0 { + rexUsed |= PrefixREXB + base |= 8 + } + if rex&PrefixREXX != 0 || vex == 0xC4 && inst.Prefix[vexIndex+1]&0x40 == 0 { + rexUsed |= PrefixREXX + index |= 8 + } + + mem.Scale = 1 << uint(scale) + if index == 4 { + // no mem.Index + } else { + mem.Index = baseRegForBits(addrMode) + Reg(index) + } + if base&7 == 5 && mod == 0 { + // no mem.Base + } else { + mem.Base = baseRegForBits(addrMode) + Reg(base) + } + } else { + if rex&PrefixREXB != 0 { + rexUsed |= PrefixREXB + rm |= 8 + } + if mod == 0 && rm&7 == 5 || rm&7 == 4 { + // base omitted + } else if mod != 3 { + mem.Base = baseRegForBits(addrMode) + Reg(rm) + } + } + + // Consume disp32 if present. + if mod == 0 && (rm&7 == 5 || haveSIB && base&7 == 5) || mod == 2 { + if pos+4 > len(src) { + return truncated(src, mode) + } + dispoff = pos + displen = 4 + mem.Disp = int64(binary.LittleEndian.Uint32(src[pos:])) + pos += 4 + } + + // Consume disp8 if present. + if mod == 1 { + if pos >= len(src) { + return truncated(src, mode) + } + dispoff = pos + displen = 1 + mem.Disp = int64(int8(src[pos])) + pos++ + } + + // In 64-bit, mod=0 rm=5 is PC-relative instead of just disp. + // See Vol 2A. Table 2-7. + if mode == 64 && mod == 0 && rm&7 == 5 { + if addrMode == 32 { + mem.Base = EIP + } else { + mem.Base = RIP + } + } + } + + if segIndex >= 0 { + mem.Segment = prefixToSegment(inst.Prefix[segIndex]) + } + } + + // Execute single opcode. + switch decodeOp(x) { + default: + println("bad op", x, "at", pc-1, "from", oldPC) + return Inst{Len: pos}, errInternal + + case xFail: + inst.Op = 0 + break Decode + + case xMatch: + break Decode + + case xJump: + pc = int(decoder[pc]) + + // Conditional branches. + + case xCondByte: + if pos >= len(src) { + return truncated(src, mode) + } + b := src[pos] + n := int(decoder[pc]) + pc++ + for i := 0; i < n; i++ { + xb, xpc := decoder[pc], int(decoder[pc+1]) + pc += 2 + if b == byte(xb) { + pc = xpc + pos++ + if opshift >= 0 { + inst.Opcode |= uint32(b) << uint(opshift) + opshift -= 8 + } + continue Decode + } + } + // xCondByte is the only conditional with a fall through, + // so that it can be used to pick off special cases before + // an xCondSlash. If the fallthrough instruction is xFail, + // advance the position so that the decoded instruction + // size includes the byte we just compared against. + if decodeOp(decoder[pc]) == xJump { + pc = int(decoder[pc+1]) + } + if decodeOp(decoder[pc]) == xFail { + pos++ + } + + case xCondIs64: + if mode == 64 { + pc = int(decoder[pc+1]) + } else { + pc = int(decoder[pc]) + } + + case xCondIsMem: + mem := haveMem + if !haveModrm { + if pos >= len(src) { + return instPrefix(src[0], mode) // too long + } + mem = src[pos]>>6 != 3 + } + if mem { + pc = int(decoder[pc+1]) + } else { + pc = int(decoder[pc]) + } + + case xCondDataSize: + switch dataMode { + case 16: + if dataSizeIndex >= 0 { + inst.Prefix[dataSizeIndex] |= PrefixImplicit + } + pc = int(decoder[pc]) + case 32: + if dataSizeIndex >= 0 { + inst.Prefix[dataSizeIndex] |= PrefixImplicit + } + pc = int(decoder[pc+1]) + case 64: + rexUsed |= PrefixREXW + pc = int(decoder[pc+2]) + } + + case xCondAddrSize: + switch addrMode { + case 16: + if addrSizeIndex >= 0 { + inst.Prefix[addrSizeIndex] |= PrefixImplicit + } + pc = int(decoder[pc]) + case 32: + if addrSizeIndex >= 0 { + inst.Prefix[addrSizeIndex] |= PrefixImplicit + } + pc = int(decoder[pc+1]) + case 64: + pc = int(decoder[pc+2]) + } + + case xCondPrefix: + // Conditional branch based on presence or absence of prefixes. + // The conflict cases here are completely undocumented and + // differ significantly between GNU libopcodes and Intel xed. + // I have not written assembly code to divine what various CPUs + // do, but it wouldn't surprise me if they are not consistent either. + // + // The basic idea is to switch on the presence of a prefix, so that + // for example: + // + // xCondPrefix, 4 + // 0xF3, 123, + // 0xF2, 234, + // 0x66, 345, + // 0, 456 + // + // branch to 123 if the F3 prefix is present, 234 if the F2 prefix + // is present, 66 if the 345 prefix is present, and 456 otherwise. + // The prefixes are given in descending order so that the 0 will be last. + // + // It is unclear what should happen if multiple conditions are + // satisfied: what if F2 and F3 are both present, or if 66 and F2 + // are present, or if all three are present? The one chosen becomes + // part of the opcode and the others do not. Perhaps the answer + // depends on the specific opcodes in question. + // + // The only clear example is that CRC32 is F2 0F 38 F1 /r, and + // it comes in 16-bit and 32-bit forms based on the 66 prefix, + // so 66 F2 0F 38 F1 /r should be treated as F2 taking priority, + // with the 66 being only an operand size override, and probably + // F2 66 0F 38 F1 /r should be treated the same. + // Perhaps that rule is specific to the case of CRC32, since no + // 66 0F 38 F1 instruction is defined (today) (that we know of). + // However, both libopcodes and xed seem to generalize this + // example and choose F2/F3 in preference to 66, and we + // do the same. + // + // Next, what if both F2 and F3 are present? Which wins? + // The Intel xed rule, and ours, is that the one that occurs last wins. + // The GNU libopcodes rule, which we implement only in gnuCompat mode, + // is that F3 beats F2 unless F3 has no special meaning, in which + // case F3 can be a modified on an F2 special meaning. + // + // Concretely, + // 66 0F D6 /r is MOVQ + // F2 0F D6 /r is MOVDQ2Q + // F3 0F D6 /r is MOVQ2DQ. + // + // F2 66 0F D6 /r is 66 + MOVDQ2Q always. + // 66 F2 0F D6 /r is 66 + MOVDQ2Q always. + // F3 66 0F D6 /r is 66 + MOVQ2DQ always. + // 66 F3 0F D6 /r is 66 + MOVQ2DQ always. + // F2 F3 0F D6 /r is F2 + MOVQ2DQ always. + // F3 F2 0F D6 /r is F3 + MOVQ2DQ in Intel xed, but F2 + MOVQ2DQ in GNU libopcodes. + // Adding 66 anywhere in the prefix section of the + // last two cases does not change the outcome. + // + // Finally, what if there is a variant in which 66 is a mandatory + // prefix rather than an operand size override, but we know of + // no corresponding F2/F3 form, and we see both F2/F3 and 66. + // Does F2/F3 still take priority, so that the result is an unknown + // instruction, or does the 66 take priority, so that the extended + // 66 instruction should be interpreted as having a REP/REPN prefix? + // Intel xed does the former and GNU libopcodes does the latter. + // We side with Intel xed, unless we are trying to match libopcodes + // more closely during the comparison-based test suite. + // + // In 64-bit mode REX.W is another valid prefix to test for, but + // there is less ambiguity about that. When present, REX.W is + // always the first entry in the table. + n := int(decoder[pc]) + pc++ + sawF3 := false + for j := 0; j < n; j++ { + prefix := Prefix(decoder[pc+2*j]) + if prefix.IsREX() { + rexUsed |= prefix + if rex&prefix == prefix { + pc = int(decoder[pc+2*j+1]) + continue Decode + } + continue + } + ok := false + if prefix == 0 { + ok = true + } else if prefix.IsREX() { + rexUsed |= prefix + if rex&prefix == prefix { + ok = true + } + } else if prefix == 0xC5 || prefix == 0xC4 { + if vex == prefix { + ok = true + } + } else if vex != 0 && (prefix == 0x0F || prefix == 0x0F38 || prefix == 0x0F3A || + prefix == 0x66 || prefix == 0xF2 || prefix == 0xF3) { + var vexM, vexP Prefix + if vex == 0xC5 { + vexM = 1 // 2 byte vex always implies 0F + vexP = inst.Prefix[vexIndex+1] + } else { + vexM = inst.Prefix[vexIndex+1] + vexP = inst.Prefix[vexIndex+2] + } + switch prefix { + case 0x66: + ok = vexP&3 == 1 + case 0xF3: + ok = vexP&3 == 2 + case 0xF2: + ok = vexP&3 == 3 + case 0x0F: + ok = vexM&3 == 1 + case 0x0F38: + ok = vexM&3 == 2 + case 0x0F3A: + ok = vexM&3 == 3 + } + } else { + if prefix == 0xF3 { + sawF3 = true + } + switch prefix { + case PrefixLOCK: + if lockIndex >= 0 { + inst.Prefix[lockIndex] |= PrefixImplicit + ok = true + } + case PrefixREP, PrefixREPN: + if repIndex >= 0 && inst.Prefix[repIndex]&0xFF == prefix { + inst.Prefix[repIndex] |= PrefixImplicit + ok = true + } + if gnuCompat && !ok && prefix == 0xF3 && repIndex >= 0 && (j+1 >= n || decoder[pc+2*(j+1)] != 0xF2) { + // Check to see if earlier prefix F3 is present. + for i := repIndex - 1; i >= 0; i-- { + if inst.Prefix[i]&0xFF == prefix { + inst.Prefix[i] |= PrefixImplicit + ok = true + } + } + } + if gnuCompat && !ok && prefix == 0xF2 && repIndex >= 0 && !sawF3 && inst.Prefix[repIndex]&0xFF == 0xF3 { + // Check to see if earlier prefix F2 is present. + for i := repIndex - 1; i >= 0; i-- { + if inst.Prefix[i]&0xFF == prefix { + inst.Prefix[i] |= PrefixImplicit + ok = true + } + } + } + case PrefixCS, PrefixDS, PrefixES, PrefixFS, PrefixGS, PrefixSS: + if segIndex >= 0 && inst.Prefix[segIndex]&0xFF == prefix { + inst.Prefix[segIndex] |= PrefixImplicit + ok = true + } + case PrefixDataSize: + // Looking for 66 mandatory prefix. + // The F2/F3 mandatory prefixes take priority when both are present. + // If we got this far in the xCondPrefix table and an F2/F3 is present, + // it means the table didn't have any entry for that prefix. But if 66 has + // special meaning, perhaps F2/F3 have special meaning that we don't know. + // Intel xed works this way, treating the F2/F3 as inhibiting the 66. + // GNU libopcodes allows the 66 to match. We do what Intel xed does + // except in gnuCompat mode. + if repIndex >= 0 && !gnuCompat { + inst.Op = 0 + break Decode + } + if dataSizeIndex >= 0 { + inst.Prefix[dataSizeIndex] |= PrefixImplicit + ok = true + } + case PrefixAddrSize: + if addrSizeIndex >= 0 { + inst.Prefix[addrSizeIndex] |= PrefixImplicit + ok = true + } + } + } + if ok { + pc = int(decoder[pc+2*j+1]) + continue Decode + } + } + inst.Op = 0 + break Decode + + case xCondSlashR: + pc = int(decoder[pc+regop&7]) + + // Input. + + case xReadSlashR: + // done above + + case xReadIb: + if pos >= len(src) { + return truncated(src, mode) + } + imm8 = int8(src[pos]) + pos++ + + case xReadIw: + if pos+2 > len(src) { + return truncated(src, mode) + } + imm = int64(binary.LittleEndian.Uint16(src[pos:])) + pos += 2 + + case xReadId: + if pos+4 > len(src) { + return truncated(src, mode) + } + imm = int64(binary.LittleEndian.Uint32(src[pos:])) + pos += 4 + + case xReadIo: + if pos+8 > len(src) { + return truncated(src, mode) + } + imm = int64(binary.LittleEndian.Uint64(src[pos:])) + pos += 8 + + case xReadCb: + if pos >= len(src) { + return truncated(src, mode) + } + immcpos = pos + immc = int64(src[pos]) + pos++ + + case xReadCw: + if pos+2 > len(src) { + return truncated(src, mode) + } + immcpos = pos + immc = int64(binary.LittleEndian.Uint16(src[pos:])) + pos += 2 + + case xReadCm: + immcpos = pos + if addrMode == 16 { + if pos+2 > len(src) { + return truncated(src, mode) + } + immc = int64(binary.LittleEndian.Uint16(src[pos:])) + pos += 2 + } else if addrMode == 32 { + if pos+4 > len(src) { + return truncated(src, mode) + } + immc = int64(binary.LittleEndian.Uint32(src[pos:])) + pos += 4 + } else { + if pos+8 > len(src) { + return truncated(src, mode) + } + immc = int64(binary.LittleEndian.Uint64(src[pos:])) + pos += 8 + } + case xReadCd: + immcpos = pos + if pos+4 > len(src) { + return truncated(src, mode) + } + immc = int64(binary.LittleEndian.Uint32(src[pos:])) + pos += 4 + + case xReadCp: + immcpos = pos + if pos+6 > len(src) { + return truncated(src, mode) + } + w := binary.LittleEndian.Uint32(src[pos:]) + w2 := binary.LittleEndian.Uint16(src[pos+4:]) + immc = int64(w2)<<32 | int64(w) + pos += 6 + + // Output. + + case xSetOp: + inst.Op = Op(decoder[pc]) + pc++ + + case xArg1, + xArg3, + xArgAL, + xArgAX, + xArgCL, + xArgCS, + xArgDS, + xArgDX, + xArgEAX, + xArgEDX, + xArgES, + xArgFS, + xArgGS, + xArgRAX, + xArgRDX, + xArgSS, + xArgST, + xArgXMM0: + inst.Args[narg] = fixedArg[x] + narg++ + + case xArgImm8: + inst.Args[narg] = Imm(imm8) + narg++ + + case xArgImm8u: + inst.Args[narg] = Imm(uint8(imm8)) + narg++ + + case xArgImm16: + inst.Args[narg] = Imm(int16(imm)) + narg++ + + case xArgImm16u: + inst.Args[narg] = Imm(uint16(imm)) + narg++ + + case xArgImm32: + inst.Args[narg] = Imm(int32(imm)) + narg++ + + case xArgImm64: + inst.Args[narg] = Imm(imm) + narg++ + + case xArgM, + xArgM128, + xArgM256, + xArgM1428byte, + xArgM16, + xArgM16and16, + xArgM16and32, + xArgM16and64, + xArgM16colon16, + xArgM16colon32, + xArgM16colon64, + xArgM16int, + xArgM2byte, + xArgM32, + xArgM32and32, + xArgM32fp, + xArgM32int, + xArgM512byte, + xArgM64, + xArgM64fp, + xArgM64int, + xArgM8, + xArgM80bcd, + xArgM80dec, + xArgM80fp, + xArgM94108byte, + xArgMem: + if !haveMem { + inst.Op = 0 + break Decode + } + inst.Args[narg] = mem + inst.MemBytes = int(memBytes[decodeOp(x)]) + if mem.Base == RIP { + inst.PCRel = displen + inst.PCRelOff = dispoff + } + narg++ + + case xArgPtr16colon16: + inst.Args[narg] = Imm(immc >> 16) + inst.Args[narg+1] = Imm(immc & (1<<16 - 1)) + narg += 2 + + case xArgPtr16colon32: + inst.Args[narg] = Imm(immc >> 32) + inst.Args[narg+1] = Imm(immc & (1<<32 - 1)) + narg += 2 + + case xArgMoffs8, xArgMoffs16, xArgMoffs32, xArgMoffs64: + // TODO(rsc): Can address be 64 bits? + mem = Mem{Disp: int64(immc)} + if segIndex >= 0 { + mem.Segment = prefixToSegment(inst.Prefix[segIndex]) + inst.Prefix[segIndex] |= PrefixImplicit + } + inst.Args[narg] = mem + inst.MemBytes = int(memBytes[decodeOp(x)]) + if mem.Base == RIP { + inst.PCRel = displen + inst.PCRelOff = dispoff + } + narg++ + + case xArgYmm1: + base := baseReg[x] + index := Reg(regop) + if inst.Prefix[vexIndex+1]&0x80 == 0 { + index += 8 + } + inst.Args[narg] = base + index + narg++ + + case xArgR8, xArgR16, xArgR32, xArgR64, xArgXmm, xArgXmm1, xArgDR0dashDR7: + base := baseReg[x] + index := Reg(regop) + if rex != 0 && base == AL && index >= 4 { + rexUsed |= PrefixREX + index -= 4 + base = SPB + } + inst.Args[narg] = base + index + narg++ + + case xArgMm, xArgMm1, xArgTR0dashTR7: + inst.Args[narg] = baseReg[x] + Reg(regop&7) + narg++ + + case xArgCR0dashCR7: + // AMD documents an extension that the LOCK prefix + // can be used in place of a REX prefix in order to access + // CR8 from 32-bit mode. The LOCK prefix is allowed in + // all modes, provided the corresponding CPUID bit is set. + if lockIndex >= 0 { + inst.Prefix[lockIndex] |= PrefixImplicit + regop += 8 + } + inst.Args[narg] = CR0 + Reg(regop) + narg++ + + case xArgSreg: + regop &= 7 + if regop >= 6 { + inst.Op = 0 + break Decode + } + inst.Args[narg] = ES + Reg(regop) + narg++ + + case xArgRmf16, xArgRmf32, xArgRmf64: + base := baseReg[x] + index := Reg(modrm & 07) + if rex&PrefixREXB != 0 { + rexUsed |= PrefixREXB + index += 8 + } + inst.Args[narg] = base + index + narg++ + + case xArgR8op, xArgR16op, xArgR32op, xArgR64op, xArgSTi: + n := inst.Opcode >> uint(opshift+8) & 07 + base := baseReg[x] + index := Reg(n) + if rex&PrefixREXB != 0 && decodeOp(x) != xArgSTi { + rexUsed |= PrefixREXB + index += 8 + } + if rex != 0 && base == AL && index >= 4 { + rexUsed |= PrefixREX + index -= 4 + base = SPB + } + inst.Args[narg] = base + index + narg++ + case xArgRM8, xArgRM16, xArgRM32, xArgRM64, xArgR32M16, xArgR32M8, xArgR64M16, + xArgMmM32, xArgMmM64, xArgMm2M64, + xArgXmm2M16, xArgXmm2M32, xArgXmm2M64, xArgXmmM64, xArgXmmM128, xArgXmmM32, xArgXmm2M128, + xArgYmm2M256: + if haveMem { + inst.Args[narg] = mem + inst.MemBytes = int(memBytes[decodeOp(x)]) + if mem.Base == RIP { + inst.PCRel = displen + inst.PCRelOff = dispoff + } + } else { + base := baseReg[x] + index := Reg(rm) + switch decodeOp(x) { + case xArgMmM32, xArgMmM64, xArgMm2M64: + // There are only 8 MMX registers, so these ignore the REX.X bit. + index &= 7 + case xArgRM8: + if rex != 0 && index >= 4 { + rexUsed |= PrefixREX + index -= 4 + base = SPB + } + case xArgYmm2M256: + if vex == 0xC4 && inst.Prefix[vexIndex+1]&0x40 == 0x40 { + index += 8 + } + } + inst.Args[narg] = base + index + } + narg++ + + case xArgMm2: // register only; TODO(rsc): Handle with tag modrm_regonly tag + if haveMem { + inst.Op = 0 + break Decode + } + inst.Args[narg] = baseReg[x] + Reg(rm&7) + narg++ + + case xArgXmm2: // register only; TODO(rsc): Handle with tag modrm_regonly tag + if haveMem { + inst.Op = 0 + break Decode + } + inst.Args[narg] = baseReg[x] + Reg(rm) + narg++ + + case xArgRel8: + inst.PCRelOff = immcpos + inst.PCRel = 1 + inst.Args[narg] = Rel(int8(immc)) + narg++ + + case xArgRel16: + inst.PCRelOff = immcpos + inst.PCRel = 2 + inst.Args[narg] = Rel(int16(immc)) + narg++ + + case xArgRel32: + inst.PCRelOff = immcpos + inst.PCRel = 4 + inst.Args[narg] = Rel(int32(immc)) + narg++ + } + } + + if inst.Op == 0 { + // Invalid instruction. + if nprefix > 0 { + return instPrefix(src[0], mode) // invalid instruction + } + return Inst{Len: pos}, ErrUnrecognized + } + + // Matched! Hooray! + + // 90 decodes as XCHG EAX, EAX but is NOP. + // 66 90 decodes as XCHG AX, AX and is NOP too. + // 48 90 decodes as XCHG RAX, RAX and is NOP too. + // 43 90 decodes as XCHG R8D, EAX and is *not* NOP. + // F3 90 decodes as REP XCHG EAX, EAX but is PAUSE. + // It's all too special to handle in the decoding tables, at least for now. + if inst.Op == XCHG && inst.Opcode>>24 == 0x90 { + if inst.Args[0] == RAX || inst.Args[0] == EAX || inst.Args[0] == AX { + inst.Op = NOP + if dataSizeIndex >= 0 { + inst.Prefix[dataSizeIndex] &^= PrefixImplicit + } + inst.Args[0] = nil + inst.Args[1] = nil + } + if repIndex >= 0 && inst.Prefix[repIndex] == 0xF3 { + inst.Prefix[repIndex] |= PrefixImplicit + inst.Op = PAUSE + inst.Args[0] = nil + inst.Args[1] = nil + } else if gnuCompat { + for i := nprefix - 1; i >= 0; i-- { + if inst.Prefix[i]&0xFF == 0xF3 { + inst.Prefix[i] |= PrefixImplicit + inst.Op = PAUSE + inst.Args[0] = nil + inst.Args[1] = nil + break + } + } + } + } + + // defaultSeg returns the default segment for an implicit + // memory reference: the final override if present, or else DS. + defaultSeg := func() Reg { + if segIndex >= 0 { + inst.Prefix[segIndex] |= PrefixImplicit + return prefixToSegment(inst.Prefix[segIndex]) + } + return DS + } + + // Add implicit arguments not present in the tables. + // Normally we shy away from making implicit arguments explicit, + // following the Intel manuals, but adding the arguments seems + // the best way to express the effect of the segment override prefixes. + // TODO(rsc): Perhaps add these to the tables and + // create bytecode instructions for them. + usedAddrSize := false + switch inst.Op { + case INSB, INSW, INSD: + inst.Args[0] = Mem{Segment: ES, Base: baseRegForBits(addrMode) + DI - AX} + inst.Args[1] = DX + usedAddrSize = true + + case OUTSB, OUTSW, OUTSD: + inst.Args[0] = DX + inst.Args[1] = Mem{Segment: defaultSeg(), Base: baseRegForBits(addrMode) + SI - AX} + usedAddrSize = true + + case MOVSB, MOVSW, MOVSD, MOVSQ: + inst.Args[0] = Mem{Segment: ES, Base: baseRegForBits(addrMode) + DI - AX} + inst.Args[1] = Mem{Segment: defaultSeg(), Base: baseRegForBits(addrMode) + SI - AX} + usedAddrSize = true + + case CMPSB, CMPSW, CMPSD, CMPSQ: + inst.Args[0] = Mem{Segment: defaultSeg(), Base: baseRegForBits(addrMode) + SI - AX} + inst.Args[1] = Mem{Segment: ES, Base: baseRegForBits(addrMode) + DI - AX} + usedAddrSize = true + + case LODSB, LODSW, LODSD, LODSQ: + switch inst.Op { + case LODSB: + inst.Args[0] = AL + case LODSW: + inst.Args[0] = AX + case LODSD: + inst.Args[0] = EAX + case LODSQ: + inst.Args[0] = RAX + } + inst.Args[1] = Mem{Segment: defaultSeg(), Base: baseRegForBits(addrMode) + SI - AX} + usedAddrSize = true + + case STOSB, STOSW, STOSD, STOSQ: + inst.Args[0] = Mem{Segment: ES, Base: baseRegForBits(addrMode) + DI - AX} + switch inst.Op { + case STOSB: + inst.Args[1] = AL + case STOSW: + inst.Args[1] = AX + case STOSD: + inst.Args[1] = EAX + case STOSQ: + inst.Args[1] = RAX + } + usedAddrSize = true + + case SCASB, SCASW, SCASD, SCASQ: + inst.Args[1] = Mem{Segment: ES, Base: baseRegForBits(addrMode) + DI - AX} + switch inst.Op { + case SCASB: + inst.Args[0] = AL + case SCASW: + inst.Args[0] = AX + case SCASD: + inst.Args[0] = EAX + case SCASQ: + inst.Args[0] = RAX + } + usedAddrSize = true + + case XLATB: + inst.Args[0] = Mem{Segment: defaultSeg(), Base: baseRegForBits(addrMode) + BX - AX} + usedAddrSize = true + } + + // If we used the address size annotation to construct the + // argument list, mark that prefix as implicit: it doesn't need + // to be shown when printing the instruction. + if haveMem || usedAddrSize { + if addrSizeIndex >= 0 { + inst.Prefix[addrSizeIndex] |= PrefixImplicit + } + } + + // Similarly, if there's some memory operand, the segment + // will be shown there and doesn't need to be shown as an + // explicit prefix. + if haveMem { + if segIndex >= 0 { + inst.Prefix[segIndex] |= PrefixImplicit + } + } + + // Branch predict prefixes are overloaded segment prefixes, + // since segment prefixes don't make sense on conditional jumps. + // Rewrite final instance to prediction prefix. + // The set of instructions to which the prefixes apply (other then the + // Jcc conditional jumps) is not 100% clear from the manuals, but + // the disassemblers seem to agree about the LOOP and JCXZ instructions, + // so we'll follow along. + // TODO(rsc): Perhaps this instruction class should be derived from the CSV. + if isCondJmp[inst.Op] || isLoop[inst.Op] || inst.Op == JCXZ || inst.Op == JECXZ || inst.Op == JRCXZ { + PredictLoop: + for i := nprefix - 1; i >= 0; i-- { + p := inst.Prefix[i] + switch p & 0xFF { + case PrefixCS: + inst.Prefix[i] = PrefixPN + break PredictLoop + case PrefixDS: + inst.Prefix[i] = PrefixPT + break PredictLoop + } + } + } + + // The BND prefix is part of the Intel Memory Protection Extensions (MPX). + // A REPN applied to certain control transfers is a BND prefix to bound + // the range of possible destinations. There's surprisingly little documentation + // about this, so we just do what libopcodes and xed agree on. + // In particular, it's unclear why a REPN applied to LOOP or JCXZ instructions + // does not turn into a BND. + // TODO(rsc): Perhaps this instruction class should be derived from the CSV. + if isCondJmp[inst.Op] || inst.Op == JMP || inst.Op == CALL || inst.Op == RET { + for i := nprefix - 1; i >= 0; i-- { + p := inst.Prefix[i] + if p&^PrefixIgnored == PrefixREPN { + inst.Prefix[i] = PrefixBND + break + } + } + } + + // The LOCK prefix only applies to certain instructions, and then only + // to instances of the instruction with a memory destination. + // Other uses of LOCK are invalid and cause a processor exception, + // in contrast to the "just ignore it" spirit applied to all other prefixes. + // Mark invalid lock prefixes. + hasLock := false + if lockIndex >= 0 && inst.Prefix[lockIndex]&PrefixImplicit == 0 { + switch inst.Op { + // TODO(rsc): Perhaps this instruction class should be derived from the CSV. + case ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCHG8B, CMPXCHG16B, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD, XCHG: + if isMem(inst.Args[0]) { + hasLock = true + break + } + fallthrough + default: + inst.Prefix[lockIndex] |= PrefixInvalid + } + } + + // In certain cases, all of which require a memory destination, + // the REPN and REP prefixes are interpreted as XACQUIRE and XRELEASE + // from the Intel Transactional Synchroniation Extensions (TSX). + // + // The specific rules are: + // (1) Any instruction with a valid LOCK prefix can have XACQUIRE or XRELEASE. + // (2) Any XCHG, which always has an implicit LOCK, can have XACQUIRE or XRELEASE. + // (3) Any 0x88-, 0x89-, 0xC6-, or 0xC7-opcode MOV can have XRELEASE. + if isMem(inst.Args[0]) { + if inst.Op == XCHG { + hasLock = true + } + + for i := len(inst.Prefix) - 1; i >= 0; i-- { + p := inst.Prefix[i] &^ PrefixIgnored + switch p { + case PrefixREPN: + if hasLock { + inst.Prefix[i] = inst.Prefix[i]&PrefixIgnored | PrefixXACQUIRE + } + + case PrefixREP: + if hasLock { + inst.Prefix[i] = inst.Prefix[i]&PrefixIgnored | PrefixXRELEASE + } + + if inst.Op == MOV { + op := (inst.Opcode >> 24) &^ 1 + if op == 0x88 || op == 0xC6 { + inst.Prefix[i] = inst.Prefix[i]&PrefixIgnored | PrefixXRELEASE + } + } + } + } + } + + // If REP is used on a non-REP-able instruction, mark the prefix as ignored. + if repIndex >= 0 { + switch inst.Prefix[repIndex] { + case PrefixREP, PrefixREPN: + switch inst.Op { + // According to the manuals, the REP/REPE prefix applies to all of these, + // while the REPN applies only to some of them. However, both libopcodes + // and xed show both prefixes explicitly for all instructions, so we do the same. + // TODO(rsc): Perhaps this instruction class should be derived from the CSV. + case INSB, INSW, INSD, + MOVSB, MOVSW, MOVSD, MOVSQ, + OUTSB, OUTSW, OUTSD, + LODSB, LODSW, LODSD, LODSQ, + CMPSB, CMPSW, CMPSD, CMPSQ, + SCASB, SCASW, SCASD, SCASQ, + STOSB, STOSW, STOSD, STOSQ: + // ok + default: + inst.Prefix[repIndex] |= PrefixIgnored + } + } + } + + // If REX was present, mark implicit if all the 1 bits were consumed. + if rexIndex >= 0 { + if rexUsed != 0 { + rexUsed |= PrefixREX + } + if rex&^rexUsed == 0 { + inst.Prefix[rexIndex] |= PrefixImplicit + } + } + + inst.DataSize = dataMode + inst.AddrSize = addrMode + inst.Mode = mode + inst.Len = pos + return inst, nil +} + +var errInternal = errors.New("internal error") + +// addr16 records the eight 16-bit addressing modes. +var addr16 = [8]Mem{ + {Base: BX, Scale: 1, Index: SI}, + {Base: BX, Scale: 1, Index: DI}, + {Base: BP, Scale: 1, Index: SI}, + {Base: BP, Scale: 1, Index: DI}, + {Base: SI}, + {Base: DI}, + {Base: BP}, + {Base: BX}, +} + +// baseReg returns the base register for a given register size in bits. +func baseRegForBits(bits int) Reg { + switch bits { + case 8: + return AL + case 16: + return AX + case 32: + return EAX + case 64: + return RAX + } + return 0 +} + +// baseReg records the base register for argument types that specify +// a range of registers indexed by op, regop, or rm. +var baseReg = [...]Reg{ + xArgDR0dashDR7: DR0, + xArgMm1: M0, + xArgMm2: M0, + xArgMm2M64: M0, + xArgMm: M0, + xArgMmM32: M0, + xArgMmM64: M0, + xArgR16: AX, + xArgR16op: AX, + xArgR32: EAX, + xArgR32M16: EAX, + xArgR32M8: EAX, + xArgR32op: EAX, + xArgR64: RAX, + xArgR64M16: RAX, + xArgR64op: RAX, + xArgR8: AL, + xArgR8op: AL, + xArgRM16: AX, + xArgRM32: EAX, + xArgRM64: RAX, + xArgRM8: AL, + xArgRmf16: AX, + xArgRmf32: EAX, + xArgRmf64: RAX, + xArgSTi: F0, + xArgTR0dashTR7: TR0, + xArgXmm1: X0, + xArgYmm1: X0, + xArgXmm2: X0, + xArgXmm2M128: X0, + xArgYmm2M256: X0, + xArgXmm2M16: X0, + xArgXmm2M32: X0, + xArgXmm2M64: X0, + xArgXmm: X0, + xArgXmmM128: X0, + xArgXmmM32: X0, + xArgXmmM64: X0, +} + +// prefixToSegment returns the segment register +// corresponding to a particular segment prefix. +func prefixToSegment(p Prefix) Reg { + switch p &^ PrefixImplicit { + case PrefixCS: + return CS + case PrefixDS: + return DS + case PrefixES: + return ES + case PrefixFS: + return FS + case PrefixGS: + return GS + case PrefixSS: + return SS + } + return 0 +} + +// fixedArg records the fixed arguments corresponding to the given bytecodes. +var fixedArg = [...]Arg{ + xArg1: Imm(1), + xArg3: Imm(3), + xArgAL: AL, + xArgAX: AX, + xArgDX: DX, + xArgEAX: EAX, + xArgEDX: EDX, + xArgRAX: RAX, + xArgRDX: RDX, + xArgCL: CL, + xArgCS: CS, + xArgDS: DS, + xArgES: ES, + xArgFS: FS, + xArgGS: GS, + xArgSS: SS, + xArgST: F0, + xArgXMM0: X0, +} + +// memBytes records the size of the memory pointed at +// by a memory argument of the given form. +var memBytes = [...]int8{ + xArgM128: 128 / 8, + xArgM256: 256 / 8, + xArgM16: 16 / 8, + xArgM16and16: (16 + 16) / 8, + xArgM16colon16: (16 + 16) / 8, + xArgM16colon32: (16 + 32) / 8, + xArgM16int: 16 / 8, + xArgM2byte: 2, + xArgM32: 32 / 8, + xArgM32and32: (32 + 32) / 8, + xArgM32fp: 32 / 8, + xArgM32int: 32 / 8, + xArgM64: 64 / 8, + xArgM64fp: 64 / 8, + xArgM64int: 64 / 8, + xArgMm2M64: 64 / 8, + xArgMmM32: 32 / 8, + xArgMmM64: 64 / 8, + xArgMoffs16: 16 / 8, + xArgMoffs32: 32 / 8, + xArgMoffs64: 64 / 8, + xArgMoffs8: 8 / 8, + xArgR32M16: 16 / 8, + xArgR32M8: 8 / 8, + xArgR64M16: 16 / 8, + xArgRM16: 16 / 8, + xArgRM32: 32 / 8, + xArgRM64: 64 / 8, + xArgRM8: 8 / 8, + xArgXmm2M128: 128 / 8, + xArgYmm2M256: 256 / 8, + xArgXmm2M16: 16 / 8, + xArgXmm2M32: 32 / 8, + xArgXmm2M64: 64 / 8, + xArgXmm: 128 / 8, + xArgXmmM128: 128 / 8, + xArgXmmM32: 32 / 8, + xArgXmmM64: 64 / 8, +} + +// isCondJmp records the conditional jumps. +var isCondJmp = [maxOp + 1]bool{ + JA: true, + JAE: true, + JB: true, + JBE: true, + JE: true, + JG: true, + JGE: true, + JL: true, + JLE: true, + JNE: true, + JNO: true, + JNP: true, + JNS: true, + JO: true, + JP: true, + JS: true, +} + +// isLoop records the loop operators. +var isLoop = [maxOp + 1]bool{ + LOOP: true, + LOOPE: true, + LOOPNE: true, + JECXZ: true, + JRCXZ: true, +} diff --git a/vendor/golang.org/x/arch/x86/x86asm/gnu.go b/vendor/golang.org/x/arch/x86/x86asm/gnu.go new file mode 100644 index 00000000..728e5d18 --- /dev/null +++ b/vendor/golang.org/x/arch/x86/x86asm/gnu.go @@ -0,0 +1,928 @@ +// Copyright 2014 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package x86asm + +import ( + "fmt" + "strings" +) + +// GNUSyntax returns the GNU assembler syntax for the instruction, as defined by GNU binutils. +// This general form is often called ``AT&T syntax'' as a reference to AT&T System V Unix. +func GNUSyntax(inst Inst) string { + // Rewrite instruction to mimic GNU peculiarities. + // Note that inst has been passed by value and contains + // no pointers, so any changes we make here are local + // and will not propagate back out to the caller. + + // Adjust opcode [sic]. + switch inst.Op { + case FDIV, FDIVR, FSUB, FSUBR, FDIVP, FDIVRP, FSUBP, FSUBRP: + // DC E0, DC F0: libopcodes swaps FSUBR/FSUB and FDIVR/FDIV, at least + // if you believe the Intel manual is correct (the encoding is irregular as given; + // libopcodes uses the more regular expected encoding). + // TODO(rsc): Test to ensure Intel manuals are correct and report to libopcodes maintainers? + // NOTE: iant thinks this is deliberate, but we can't find the history. + _, reg1 := inst.Args[0].(Reg) + _, reg2 := inst.Args[1].(Reg) + if reg1 && reg2 && (inst.Opcode>>24 == 0xDC || inst.Opcode>>24 == 0xDE) { + switch inst.Op { + case FDIV: + inst.Op = FDIVR + case FDIVR: + inst.Op = FDIV + case FSUB: + inst.Op = FSUBR + case FSUBR: + inst.Op = FSUB + case FDIVP: + inst.Op = FDIVRP + case FDIVRP: + inst.Op = FDIVP + case FSUBP: + inst.Op = FSUBRP + case FSUBRP: + inst.Op = FSUBP + } + } + + case MOVNTSD: + // MOVNTSD is F2 0F 2B /r. + // MOVNTSS is F3 0F 2B /r (supposedly; not in manuals). + // Usually inner prefixes win for display, + // so that F3 F2 0F 2B 11 is REP MOVNTSD + // and F2 F3 0F 2B 11 is REPN MOVNTSS. + // Libopcodes always prefers MOVNTSS regardless of prefix order. + if countPrefix(&inst, 0xF3) > 0 { + found := false + for i := len(inst.Prefix) - 1; i >= 0; i-- { + switch inst.Prefix[i] & 0xFF { + case 0xF3: + if !found { + found = true + inst.Prefix[i] |= PrefixImplicit + } + case 0xF2: + inst.Prefix[i] &^= PrefixImplicit + } + } + inst.Op = MOVNTSS + } + } + + // Add implicit arguments. + switch inst.Op { + case MONITOR: + inst.Args[0] = EDX + inst.Args[1] = ECX + inst.Args[2] = EAX + if inst.AddrSize == 16 { + inst.Args[2] = AX + } + + case MWAIT: + if inst.Mode == 64 { + inst.Args[0] = RCX + inst.Args[1] = RAX + } else { + inst.Args[0] = ECX + inst.Args[1] = EAX + } + } + + // Adjust which prefixes will be displayed. + // The rule is to display all the prefixes not implied by + // the usual instruction display, that is, all the prefixes + // except the ones with PrefixImplicit set. + // However, of course, there are exceptions to the rule. + switch inst.Op { + case CRC32: + // CRC32 has a mandatory F2 prefix. + // If there are multiple F2s and no F3s, the extra F2s do not print. + // (And Decode has already marked them implicit.) + // However, if there is an F3 anywhere, then the extra F2s do print. + // If there are multiple F2 prefixes *and* an (ignored) F3, + // then libopcodes prints the extra F2s as REPNs. + if countPrefix(&inst, 0xF2) > 1 { + unmarkImplicit(&inst, 0xF2) + markLastImplicit(&inst, 0xF2) + } + + // An unused data size override should probably be shown, + // to distinguish DATA16 CRC32B from plain CRC32B, + // but libopcodes always treats the final override as implicit + // and the others as explicit. + unmarkImplicit(&inst, PrefixDataSize) + markLastImplicit(&inst, PrefixDataSize) + + case CVTSI2SD, CVTSI2SS: + if !isMem(inst.Args[1]) { + markLastImplicit(&inst, PrefixDataSize) + } + + case CVTSD2SI, CVTSS2SI, CVTTSD2SI, CVTTSS2SI, + ENTER, FLDENV, FNSAVE, FNSTENV, FRSTOR, LGDT, LIDT, LRET, + POP, PUSH, RET, SGDT, SIDT, SYSRET, XBEGIN: + markLastImplicit(&inst, PrefixDataSize) + + case LOOP, LOOPE, LOOPNE, MONITOR: + markLastImplicit(&inst, PrefixAddrSize) + + case MOV: + // The 16-bit and 32-bit forms of MOV Sreg, dst and MOV src, Sreg + // cannot be distinguished when src or dst refers to memory, because + // Sreg is always a 16-bit value, even when we're doing a 32-bit + // instruction. Because the instruction tables distinguished these two, + // any operand size prefix has been marked as used (to decide which + // branch to take). Unmark it, so that it will show up in disassembly, + // so that the reader can tell the size of memory operand. + // up with the same arguments + dst, _ := inst.Args[0].(Reg) + src, _ := inst.Args[1].(Reg) + if ES <= src && src <= GS && isMem(inst.Args[0]) || ES <= dst && dst <= GS && isMem(inst.Args[1]) { + unmarkImplicit(&inst, PrefixDataSize) + } + + case MOVDQU: + if countPrefix(&inst, 0xF3) > 1 { + unmarkImplicit(&inst, 0xF3) + markLastImplicit(&inst, 0xF3) + } + + case MOVQ2DQ: + markLastImplicit(&inst, PrefixDataSize) + + case SLDT, SMSW, STR, FXRSTOR, XRSTOR, XSAVE, XSAVEOPT, CMPXCHG8B: + if isMem(inst.Args[0]) { + unmarkImplicit(&inst, PrefixDataSize) + } + + case SYSEXIT: + unmarkImplicit(&inst, PrefixDataSize) + } + + if isCondJmp[inst.Op] || isLoop[inst.Op] || inst.Op == JCXZ || inst.Op == JECXZ || inst.Op == JRCXZ { + if countPrefix(&inst, PrefixCS) > 0 && countPrefix(&inst, PrefixDS) > 0 { + for i, p := range inst.Prefix { + switch p & 0xFFF { + case PrefixPN, PrefixPT: + inst.Prefix[i] &= 0xF0FF // cut interpretation bits, producing original segment prefix + } + } + } + } + + // XACQUIRE/XRELEASE adjustment. + if inst.Op == MOV { + // MOV into memory is a candidate for turning REP into XRELEASE. + // However, if the REP is followed by a REPN, that REPN blocks the + // conversion. + haveREPN := false + for i := len(inst.Prefix) - 1; i >= 0; i-- { + switch inst.Prefix[i] &^ PrefixIgnored { + case PrefixREPN: + haveREPN = true + case PrefixXRELEASE: + if haveREPN { + inst.Prefix[i] = PrefixREP + } + } + } + } + + // We only format the final F2/F3 as XRELEASE/XACQUIRE. + haveXA := false + haveXR := false + for i := len(inst.Prefix) - 1; i >= 0; i-- { + switch inst.Prefix[i] &^ PrefixIgnored { + case PrefixXRELEASE: + if !haveXR { + haveXR = true + } else { + inst.Prefix[i] = PrefixREP + } + + case PrefixXACQUIRE: + if !haveXA { + haveXA = true + } else { + inst.Prefix[i] = PrefixREPN + } + } + } + + // Determine opcode. + op := strings.ToLower(inst.Op.String()) + if alt := gnuOp[inst.Op]; alt != "" { + op = alt + } + + // Determine opcode suffix. + // Libopcodes omits the suffix if the width of the operation + // can be inferred from a register arguments. For example, + // add $1, %ebx has no suffix because you can tell from the + // 32-bit register destination that it is a 32-bit add, + // but in addl $1, (%ebx), the destination is memory, so the + // size is not evident without the l suffix. + needSuffix := true +SuffixLoop: + for i, a := range inst.Args { + if a == nil { + break + } + switch a := a.(type) { + case Reg: + switch inst.Op { + case MOVSX, MOVZX: + continue + + case SHL, SHR, RCL, RCR, ROL, ROR, SAR: + if i == 1 { + // shift count does not tell us operand size + continue + } + + case CRC32: + // The source argument does tell us operand size, + // but libopcodes still always puts a suffix on crc32. + continue + + case PUSH, POP: + // Even though segment registers are 16-bit, push and pop + // can save/restore them from 32-bit slots, so they + // do not imply operand size. + if ES <= a && a <= GS { + continue + } + + case CVTSI2SD, CVTSI2SS: + // The integer register argument takes priority. + if X0 <= a && a <= X15 { + continue + } + } + + if AL <= a && a <= R15 || ES <= a && a <= GS || X0 <= a && a <= X15 || M0 <= a && a <= M7 { + needSuffix = false + break SuffixLoop + } + } + } + + if needSuffix { + switch inst.Op { + case CMPXCHG8B, FLDCW, FNSTCW, FNSTSW, LDMXCSR, LLDT, LMSW, LTR, PCLMULQDQ, + SETA, SETAE, SETB, SETBE, SETE, SETG, SETGE, SETL, SETLE, SETNE, SETNO, SETNP, SETNS, SETO, SETP, SETS, + SLDT, SMSW, STMXCSR, STR, VERR, VERW: + // For various reasons, libopcodes emits no suffix for these instructions. + + case CRC32: + op += byteSizeSuffix(argBytes(&inst, inst.Args[1])) + + case LGDT, LIDT, SGDT, SIDT: + op += byteSizeSuffix(inst.DataSize / 8) + + case MOVZX, MOVSX: + // Integer size conversions get two suffixes. + op = op[:4] + byteSizeSuffix(argBytes(&inst, inst.Args[1])) + byteSizeSuffix(argBytes(&inst, inst.Args[0])) + + case LOOP, LOOPE, LOOPNE: + // Add w suffix to indicate use of CX register instead of ECX. + if inst.AddrSize == 16 { + op += "w" + } + + case CALL, ENTER, JMP, LCALL, LEAVE, LJMP, LRET, RET, SYSRET, XBEGIN: + // Add w suffix to indicate use of 16-bit target. + // Exclude JMP rel8. + if inst.Opcode>>24 == 0xEB { + break + } + if inst.DataSize == 16 && inst.Mode != 16 { + markLastImplicit(&inst, PrefixDataSize) + op += "w" + } else if inst.Mode == 64 { + op += "q" + } + + case FRSTOR, FNSAVE, FNSTENV, FLDENV: + // Add s suffix to indicate shortened FPU state (I guess). + if inst.DataSize == 16 { + op += "s" + } + + case PUSH, POP: + if markLastImplicit(&inst, PrefixDataSize) { + op += byteSizeSuffix(inst.DataSize / 8) + } else if inst.Mode == 64 { + op += "q" + } else { + op += byteSizeSuffix(inst.MemBytes) + } + + default: + if isFloat(inst.Op) { + // I can't explain any of this, but it's what libopcodes does. + switch inst.MemBytes { + default: + if (inst.Op == FLD || inst.Op == FSTP) && isMem(inst.Args[0]) { + op += "t" + } + case 4: + if isFloatInt(inst.Op) { + op += "l" + } else { + op += "s" + } + case 8: + if isFloatInt(inst.Op) { + op += "ll" + } else { + op += "l" + } + } + break + } + + op += byteSizeSuffix(inst.MemBytes) + } + } + + // Adjust special case opcodes. + switch inst.Op { + case 0: + if inst.Prefix[0] != 0 { + return strings.ToLower(inst.Prefix[0].String()) + } + + case INT: + if inst.Opcode>>24 == 0xCC { + inst.Args[0] = nil + op = "int3" + } + + case CMPPS, CMPPD, CMPSD_XMM, CMPSS: + imm, ok := inst.Args[2].(Imm) + if ok && 0 <= imm && imm < 8 { + inst.Args[2] = nil + op = cmppsOps[imm] + op[3:] + } + + case PCLMULQDQ: + imm, ok := inst.Args[2].(Imm) + if ok && imm&^0x11 == 0 { + inst.Args[2] = nil + op = pclmulqOps[(imm&0x10)>>3|(imm&1)] + } + + case XLATB: + if markLastImplicit(&inst, PrefixAddrSize) { + op = "xlat" // not xlatb + } + } + + // Build list of argument strings. + var ( + usedPrefixes bool // segment prefixes consumed by Mem formatting + args []string // formatted arguments + ) + for i, a := range inst.Args { + if a == nil { + break + } + switch inst.Op { + case MOVSB, MOVSW, MOVSD, MOVSQ, OUTSB, OUTSW, OUTSD: + if i == 0 { + usedPrefixes = true // disable use of prefixes for first argument + } else { + usedPrefixes = false + } + } + if a == Imm(1) && (inst.Opcode>>24)&^1 == 0xD0 { + continue + } + args = append(args, gnuArg(&inst, a, &usedPrefixes)) + } + + // The default is to print the arguments in reverse Intel order. + // A few instructions inhibit this behavior. + switch inst.Op { + case BOUND, LCALL, ENTER, LJMP: + // no reverse + default: + // reverse args + for i, j := 0, len(args)-1; i < j; i, j = i+1, j-1 { + args[i], args[j] = args[j], args[i] + } + } + + // Build prefix string. + // Must be after argument formatting, which can turn off segment prefixes. + var ( + prefix = "" // output string + numAddr = 0 + numData = 0 + implicitData = false + ) + for _, p := range inst.Prefix { + if p&0xFF == PrefixDataSize && p&PrefixImplicit != 0 { + implicitData = true + } + } + for _, p := range inst.Prefix { + if p == 0 || p.IsVEX() { + break + } + if p&PrefixImplicit != 0 { + continue + } + switch p &^ (PrefixIgnored | PrefixInvalid) { + default: + if p.IsREX() { + if p&0xFF == PrefixREX { + prefix += "rex " + } else { + prefix += "rex." + p.String()[4:] + " " + } + break + } + prefix += strings.ToLower(p.String()) + " " + + case PrefixPN: + op += ",pn" + continue + + case PrefixPT: + op += ",pt" + continue + + case PrefixAddrSize, PrefixAddr16, PrefixAddr32: + // For unknown reasons, if the addr16 prefix is repeated, + // libopcodes displays all but the last as addr32, even though + // the addressing form used in a memory reference is clearly + // still 16-bit. + n := 32 + if inst.Mode == 32 { + n = 16 + } + numAddr++ + if countPrefix(&inst, PrefixAddrSize) > numAddr { + n = inst.Mode + } + prefix += fmt.Sprintf("addr%d ", n) + continue + + case PrefixData16, PrefixData32: + if implicitData && countPrefix(&inst, PrefixDataSize) > 1 { + // Similar to the addr32 logic above, but it only kicks in + // when something used the data size prefix (one is implicit). + n := 16 + if inst.Mode == 16 { + n = 32 + } + numData++ + if countPrefix(&inst, PrefixDataSize) > numData { + if inst.Mode == 16 { + n = 16 + } else { + n = 32 + } + } + prefix += fmt.Sprintf("data%d ", n) + continue + } + prefix += strings.ToLower(p.String()) + " " + } + } + + // Finally! Put it all together. + text := prefix + op + if args != nil { + text += " " + // Indirect call/jmp gets a star to distinguish from direct jump address. + if (inst.Op == CALL || inst.Op == JMP || inst.Op == LJMP || inst.Op == LCALL) && (isMem(inst.Args[0]) || isReg(inst.Args[0])) { + text += "*" + } + text += strings.Join(args, ",") + } + return text +} + +// gnuArg returns the GNU syntax for the argument x from the instruction inst. +// If *usedPrefixes is false and x is a Mem, then the formatting +// includes any segment prefixes and sets *usedPrefixes to true. +func gnuArg(inst *Inst, x Arg, usedPrefixes *bool) string { + if x == nil { + return "<nil>" + } + switch x := x.(type) { + case Reg: + switch inst.Op { + case CVTSI2SS, CVTSI2SD, CVTSS2SI, CVTSD2SI, CVTTSD2SI, CVTTSS2SI: + if inst.DataSize == 16 && EAX <= x && x <= R15L { + x -= EAX - AX + } + + case IN, INSB, INSW, INSD, OUT, OUTSB, OUTSW, OUTSD: + // DX is the port, but libopcodes prints it as if it were a memory reference. + if x == DX { + return "(%dx)" + } + case VMOVDQA, VMOVDQU, VMOVNTDQA, VMOVNTDQ: + return strings.Replace(gccRegName[x], "xmm", "ymm", -1) + } + return gccRegName[x] + case Mem: + seg := "" + var haveCS, haveDS, haveES, haveFS, haveGS, haveSS bool + switch x.Segment { + case CS: + haveCS = true + case DS: + haveDS = true + case ES: + haveES = true + case FS: + haveFS = true + case GS: + haveGS = true + case SS: + haveSS = true + } + switch inst.Op { + case INSB, INSW, INSD, STOSB, STOSW, STOSD, STOSQ, SCASB, SCASW, SCASD, SCASQ: + // These do not accept segment prefixes, at least in the GNU rendering. + default: + if *usedPrefixes { + break + } + for i := len(inst.Prefix) - 1; i >= 0; i-- { + p := inst.Prefix[i] &^ PrefixIgnored + if p == 0 { + continue + } + switch p { + case PrefixCS: + if !haveCS { + haveCS = true + inst.Prefix[i] |= PrefixImplicit + } + case PrefixDS: + if !haveDS { + haveDS = true + inst.Prefix[i] |= PrefixImplicit + } + case PrefixES: + if !haveES { + haveES = true + inst.Prefix[i] |= PrefixImplicit + } + case PrefixFS: + if !haveFS { + haveFS = true + inst.Prefix[i] |= PrefixImplicit + } + case PrefixGS: + if !haveGS { + haveGS = true + inst.Prefix[i] |= PrefixImplicit + } + case PrefixSS: + if !haveSS { + haveSS = true + inst.Prefix[i] |= PrefixImplicit + } + } + } + *usedPrefixes = true + } + if haveCS { + seg += "%cs:" + } + if haveDS { + seg += "%ds:" + } + if haveSS { + seg += "%ss:" + } + if haveES { + seg += "%es:" + } + if haveFS { + seg += "%fs:" + } + if haveGS { + seg += "%gs:" + } + disp := "" + if x.Disp != 0 { + disp = fmt.Sprintf("%#x", x.Disp) + } + if x.Scale == 0 || x.Index == 0 && x.Scale == 1 && (x.Base == ESP || x.Base == RSP || x.Base == 0 && inst.Mode == 64) { + if x.Base == 0 { + return seg + disp + } + return fmt.Sprintf("%s%s(%s)", seg, disp, gccRegName[x.Base]) + } + base := gccRegName[x.Base] + if x.Base == 0 { + base = "" + } + index := gccRegName[x.Index] + if x.Index == 0 { + if inst.AddrSize == 64 { + index = "%riz" + } else { + index = "%eiz" + } + } + if AX <= x.Base && x.Base <= DI { + // 16-bit addressing - no scale + return fmt.Sprintf("%s%s(%s,%s)", seg, disp, base, index) + } + return fmt.Sprintf("%s%s(%s,%s,%d)", seg, disp, base, index, x.Scale) + case Rel: + return fmt.Sprintf(".%+#x", int32(x)) + case Imm: + if inst.Mode == 32 { + return fmt.Sprintf("$%#x", uint32(x)) + } + return fmt.Sprintf("$%#x", int64(x)) + } + return x.String() +} + +var gccRegName = [...]string{ + 0: "REG0", + AL: "%al", + CL: "%cl", + BL: "%bl", + DL: "%dl", + AH: "%ah", + CH: "%ch", + BH: "%bh", + DH: "%dh", + SPB: "%spl", + BPB: "%bpl", + SIB: "%sil", + DIB: "%dil", + R8B: "%r8b", + R9B: "%r9b", + R10B: "%r10b", + R11B: "%r11b", + R12B: "%r12b", + R13B: "%r13b", + R14B: "%r14b", + R15B: "%r15b", + AX: "%ax", + CX: "%cx", + BX: "%bx", + DX: "%dx", + SP: "%sp", + BP: "%bp", + SI: "%si", + DI: "%di", + R8W: "%r8w", + R9W: "%r9w", + R10W: "%r10w", + R11W: "%r11w", + R12W: "%r12w", + R13W: "%r13w", + R14W: "%r14w", + R15W: "%r15w", + EAX: "%eax", + ECX: "%ecx", + EDX: "%edx", + EBX: "%ebx", + ESP: "%esp", + EBP: "%ebp", + ESI: "%esi", + EDI: "%edi", + R8L: "%r8d", + R9L: "%r9d", + R10L: "%r10d", + R11L: "%r11d", + R12L: "%r12d", + R13L: "%r13d", + R14L: "%r14d", + R15L: "%r15d", + RAX: "%rax", + RCX: "%rcx", + RDX: "%rdx", + RBX: "%rbx", + RSP: "%rsp", + RBP: "%rbp", + RSI: "%rsi", + RDI: "%rdi", + R8: "%r8", + R9: "%r9", + R10: "%r10", + R11: "%r11", + R12: "%r12", + R13: "%r13", + R14: "%r14", + R15: "%r15", + IP: "%ip", + EIP: "%eip", + RIP: "%rip", + F0: "%st", + F1: "%st(1)", + F2: "%st(2)", + F3: "%st(3)", + F4: "%st(4)", + F5: "%st(5)", + F6: "%st(6)", + F7: "%st(7)", + M0: "%mm0", + M1: "%mm1", + M2: "%mm2", + M3: "%mm3", + M4: "%mm4", + M5: "%mm5", + M6: "%mm6", + M7: "%mm7", + X0: "%xmm0", + X1: "%xmm1", + X2: "%xmm2", + X3: "%xmm3", + X4: "%xmm4", + X5: "%xmm5", + X6: "%xmm6", + X7: "%xmm7", + X8: "%xmm8", + X9: "%xmm9", + X10: "%xmm10", + X11: "%xmm11", + X12: "%xmm12", + X13: "%xmm13", + X14: "%xmm14", + X15: "%xmm15", + CS: "%cs", + SS: "%ss", + DS: "%ds", + ES: "%es", + FS: "%fs", + GS: "%gs", + GDTR: "%gdtr", + IDTR: "%idtr", + LDTR: "%ldtr", + MSW: "%msw", + TASK: "%task", + CR0: "%cr0", + CR1: "%cr1", + CR2: "%cr2", + CR3: "%cr3", + CR4: "%cr4", + CR5: "%cr5", + CR6: "%cr6", + CR7: "%cr7", + CR8: "%cr8", + CR9: "%cr9", + CR10: "%cr10", + CR11: "%cr11", + CR12: "%cr12", + CR13: "%cr13", + CR14: "%cr14", + CR15: "%cr15", + DR0: "%db0", + DR1: "%db1", + DR2: "%db2", + DR3: "%db3", + DR4: "%db4", + DR5: "%db5", + DR6: "%db6", + DR7: "%db7", + TR0: "%tr0", + TR1: "%tr1", + TR2: "%tr2", + TR3: "%tr3", + TR4: "%tr4", + TR5: "%tr5", + TR6: "%tr6", + TR7: "%tr7", +} + +var gnuOp = map[Op]string{ + CBW: "cbtw", + CDQ: "cltd", + CMPSD: "cmpsl", + CMPSD_XMM: "cmpsd", + CWD: "cwtd", + CWDE: "cwtl", + CQO: "cqto", + INSD: "insl", + IRET: "iretw", + IRETD: "iret", + IRETQ: "iretq", + LODSB: "lods", + LODSD: "lods", + LODSQ: "lods", + LODSW: "lods", + MOVSD: "movsl", + MOVSD_XMM: "movsd", + OUTSD: "outsl", + POPA: "popaw", + POPAD: "popa", + POPF: "popfw", + POPFD: "popf", + PUSHA: "pushaw", + PUSHAD: "pusha", + PUSHF: "pushfw", + PUSHFD: "pushf", + SCASB: "scas", + SCASD: "scas", + SCASQ: "scas", + SCASW: "scas", + STOSB: "stos", + STOSD: "stos", + STOSQ: "stos", + STOSW: "stos", + XLATB: "xlat", +} + +var cmppsOps = []string{ + "cmpeq", + "cmplt", + "cmple", + "cmpunord", + "cmpneq", + "cmpnlt", + "cmpnle", + "cmpord", +} + +var pclmulqOps = []string{ + "pclmullqlqdq", + "pclmulhqlqdq", + "pclmullqhqdq", + "pclmulhqhqdq", +} + +func countPrefix(inst *Inst, target Prefix) int { + n := 0 + for _, p := range inst.Prefix { + if p&0xFF == target&0xFF { + n++ + } + } + return n +} + +func markLastImplicit(inst *Inst, prefix Prefix) bool { + for i := len(inst.Prefix) - 1; i >= 0; i-- { + p := inst.Prefix[i] + if p&0xFF == prefix { + inst.Prefix[i] |= PrefixImplicit + return true + } + } + return false +} + +func unmarkImplicit(inst *Inst, prefix Prefix) { + for i := len(inst.Prefix) - 1; i >= 0; i-- { + p := inst.Prefix[i] + if p&0xFF == prefix { + inst.Prefix[i] &^= PrefixImplicit + } + } +} + +func byteSizeSuffix(b int) string { + switch b { + case 1: + return "b" + case 2: + return "w" + case 4: + return "l" + case 8: + return "q" + } + return "" +} + +func argBytes(inst *Inst, arg Arg) int { + if isMem(arg) { + return inst.MemBytes + } + return regBytes(arg) +} + +func isFloat(op Op) bool { + switch op { + case FADD, FCOM, FCOMP, FDIV, FDIVR, FIADD, FICOM, FICOMP, FIDIV, FIDIVR, FILD, FIMUL, FIST, FISTP, FISTTP, FISUB, FISUBR, FLD, FMUL, FST, FSTP, FSUB, FSUBR: + return true + } + return false +} + +func isFloatInt(op Op) bool { + switch op { + case FIADD, FICOM, FICOMP, FIDIV, FIDIVR, FILD, FIMUL, FIST, FISTP, FISTTP, FISUB, FISUBR: + return true + } + return false +} diff --git a/vendor/golang.org/x/arch/x86/x86asm/inst.go b/vendor/golang.org/x/arch/x86/x86asm/inst.go new file mode 100644 index 00000000..4632b506 --- /dev/null +++ b/vendor/golang.org/x/arch/x86/x86asm/inst.go @@ -0,0 +1,649 @@ +// Copyright 2014 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// Package x86asm implements decoding of x86 machine code. +package x86asm + +import ( + "bytes" + "fmt" +) + +// An Inst is a single instruction. +type Inst struct { + Prefix Prefixes // Prefixes applied to the instruction. + Op Op // Opcode mnemonic + Opcode uint32 // Encoded opcode bits, left aligned (first byte is Opcode>>24, etc) + Args Args // Instruction arguments, in Intel order + Mode int // processor mode in bits: 16, 32, or 64 + AddrSize int // address size in bits: 16, 32, or 64 + DataSize int // operand size in bits: 16, 32, or 64 + MemBytes int // size of memory argument in bytes: 1, 2, 4, 8, 16, and so on. + Len int // length of encoded instruction in bytes + PCRel int // length of PC-relative address in instruction encoding + PCRelOff int // index of start of PC-relative address in instruction encoding +} + +// Prefixes is an array of prefixes associated with a single instruction. +// The prefixes are listed in the same order as found in the instruction: +// each prefix byte corresponds to one slot in the array. The first zero +// in the array marks the end of the prefixes. +type Prefixes [14]Prefix + +// A Prefix represents an Intel instruction prefix. +// The low 8 bits are the actual prefix byte encoding, +// and the top 8 bits contain distinguishing bits and metadata. +type Prefix uint16 + +const ( + // Metadata about the role of a prefix in an instruction. + PrefixImplicit Prefix = 0x8000 // prefix is implied by instruction text + PrefixIgnored Prefix = 0x4000 // prefix is ignored: either irrelevant or overridden by a later prefix + PrefixInvalid Prefix = 0x2000 // prefix makes entire instruction invalid (bad LOCK) + + // Memory segment overrides. + PrefixES Prefix = 0x26 // ES segment override + PrefixCS Prefix = 0x2E // CS segment override + PrefixSS Prefix = 0x36 // SS segment override + PrefixDS Prefix = 0x3E // DS segment override + PrefixFS Prefix = 0x64 // FS segment override + PrefixGS Prefix = 0x65 // GS segment override + + // Branch prediction. + PrefixPN Prefix = 0x12E // predict not taken (conditional branch only) + PrefixPT Prefix = 0x13E // predict taken (conditional branch only) + + // Size attributes. + PrefixDataSize Prefix = 0x66 // operand size override + PrefixData16 Prefix = 0x166 + PrefixData32 Prefix = 0x266 + PrefixAddrSize Prefix = 0x67 // address size override + PrefixAddr16 Prefix = 0x167 + PrefixAddr32 Prefix = 0x267 + + // One of a kind. + PrefixLOCK Prefix = 0xF0 // lock + PrefixREPN Prefix = 0xF2 // repeat not zero + PrefixXACQUIRE Prefix = 0x1F2 + PrefixBND Prefix = 0x2F2 + PrefixREP Prefix = 0xF3 // repeat + PrefixXRELEASE Prefix = 0x1F3 + + // The REX prefixes must be in the range [PrefixREX, PrefixREX+0x10). + // the other bits are set or not according to the intended use. + PrefixREX Prefix = 0x40 // REX 64-bit extension prefix + PrefixREXW Prefix = 0x08 // extension bit W (64-bit instruction width) + PrefixREXR Prefix = 0x04 // extension bit R (r field in modrm) + PrefixREXX Prefix = 0x02 // extension bit X (index field in sib) + PrefixREXB Prefix = 0x01 // extension bit B (r/m field in modrm or base field in sib) + PrefixVEX2Bytes Prefix = 0xC5 // Short form of vex prefix + PrefixVEX3Bytes Prefix = 0xC4 // Long form of vex prefix +) + +// IsREX reports whether p is a REX prefix byte. +func (p Prefix) IsREX() bool { + return p&0xF0 == PrefixREX +} + +func (p Prefix) IsVEX() bool { + return p&0xFF == PrefixVEX2Bytes || p&0xFF == PrefixVEX3Bytes +} + +func (p Prefix) String() string { + p &^= PrefixImplicit | PrefixIgnored | PrefixInvalid + if s := prefixNames[p]; s != "" { + return s + } + + if p.IsREX() { + s := "REX." + if p&PrefixREXW != 0 { + s += "W" + } + if p&PrefixREXR != 0 { + s += "R" + } + if p&PrefixREXX != 0 { + s += "X" + } + if p&PrefixREXB != 0 { + s += "B" + } + return s + } + + return fmt.Sprintf("Prefix(%#x)", int(p)) +} + +// An Op is an x86 opcode. +type Op uint32 + +func (op Op) String() string { + i := int(op) + if i < 0 || i >= len(opNames) || opNames[i] == "" { + return fmt.Sprintf("Op(%d)", i) + } + return opNames[i] +} + +// An Args holds the instruction arguments. +// If an instruction has fewer than 4 arguments, +// the final elements in the array are nil. +type Args [4]Arg + +// An Arg is a single instruction argument, +// one of these types: Reg, Mem, Imm, Rel. +type Arg interface { + String() string + isArg() +} + +// Note that the implements of Arg that follow are all sized +// so that on a 64-bit machine the data can be inlined in +// the interface value instead of requiring an allocation. + +// A Reg is a single register. +// The zero Reg value has no name but indicates ``no register.'' +type Reg uint8 + +const ( + _ Reg = iota + + // 8-bit + AL + CL + DL + BL + AH + CH + DH + BH + SPB + BPB + SIB + DIB + R8B + R9B + R10B + R11B + R12B + R13B + R14B + R15B + + // 16-bit + AX + CX + DX + BX + SP + BP + SI + DI + R8W + R9W + R10W + R11W + R12W + R13W + R14W + R15W + + // 32-bit + EAX + ECX + EDX + EBX + ESP + EBP + ESI + EDI + R8L + R9L + R10L + R11L + R12L + R13L + R14L + R15L + + // 64-bit + RAX + RCX + RDX + RBX + RSP + RBP + RSI + RDI + R8 + R9 + R10 + R11 + R12 + R13 + R14 + R15 + + // Instruction pointer. + IP // 16-bit + EIP // 32-bit + RIP // 64-bit + + // 387 floating point registers. + F0 + F1 + F2 + F3 + F4 + F5 + F6 + F7 + + // MMX registers. + M0 + M1 + M2 + M3 + M4 + M5 + M6 + M7 + + // XMM registers. + X0 + X1 + X2 + X3 + X4 + X5 + X6 + X7 + X8 + X9 + X10 + X11 + X12 + X13 + X14 + X15 + + // Segment registers. + ES + CS + SS + DS + FS + GS + + // System registers. + GDTR + IDTR + LDTR + MSW + TASK + + // Control registers. + CR0 + CR1 + CR2 + CR3 + CR4 + CR5 + CR6 + CR7 + CR8 + CR9 + CR10 + CR11 + CR12 + CR13 + CR14 + CR15 + + // Debug registers. + DR0 + DR1 + DR2 + DR3 + DR4 + DR5 + DR6 + DR7 + DR8 + DR9 + DR10 + DR11 + DR12 + DR13 + DR14 + DR15 + + // Task registers. + TR0 + TR1 + TR2 + TR3 + TR4 + TR5 + TR6 + TR7 +) + +const regMax = TR7 + +func (Reg) isArg() {} + +func (r Reg) String() string { + i := int(r) + if i < 0 || i >= len(regNames) || regNames[i] == "" { + return fmt.Sprintf("Reg(%d)", i) + } + return regNames[i] +} + +// A Mem is a memory reference. +// The general form is Segment:[Base+Scale*Index+Disp]. +type Mem struct { + Segment Reg + Base Reg + Scale uint8 + Index Reg + Disp int64 +} + +func (Mem) isArg() {} + +func (m Mem) String() string { + var base, plus, scale, index, disp string + + if m.Base != 0 { + base = m.Base.String() + } + if m.Scale != 0 { + if m.Base != 0 { + plus = "+" + } + if m.Scale > 1 { + scale = fmt.Sprintf("%d*", m.Scale) + } + index = m.Index.String() + } + if m.Disp != 0 || m.Base == 0 && m.Scale == 0 { + disp = fmt.Sprintf("%+#x", m.Disp) + } + return "[" + base + plus + scale + index + disp + "]" +} + +// A Rel is an offset relative to the current instruction pointer. +type Rel int32 + +func (Rel) isArg() {} + +func (r Rel) String() string { + return fmt.Sprintf(".%+d", r) +} + +// An Imm is an integer constant. +type Imm int64 + +func (Imm) isArg() {} + +func (i Imm) String() string { + return fmt.Sprintf("%#x", int64(i)) +} + +func (i Inst) String() string { + var buf bytes.Buffer + for _, p := range i.Prefix { + if p == 0 { + break + } + if p&PrefixImplicit != 0 { + continue + } + fmt.Fprintf(&buf, "%v ", p) + } + fmt.Fprintf(&buf, "%v", i.Op) + sep := " " + for _, v := range i.Args { + if v == nil { + break + } + fmt.Fprintf(&buf, "%s%v", sep, v) + sep = ", " + } + return buf.String() +} + +func isReg(a Arg) bool { + _, ok := a.(Reg) + return ok +} + +func isSegReg(a Arg) bool { + r, ok := a.(Reg) + return ok && ES <= r && r <= GS +} + +func isMem(a Arg) bool { + _, ok := a.(Mem) + return ok +} + +func isImm(a Arg) bool { + _, ok := a.(Imm) + return ok +} + +func regBytes(a Arg) int { + r, ok := a.(Reg) + if !ok { + return 0 + } + if AL <= r && r <= R15B { + return 1 + } + if AX <= r && r <= R15W { + return 2 + } + if EAX <= r && r <= R15L { + return 4 + } + if RAX <= r && r <= R15 { + return 8 + } + return 0 +} + +func isSegment(p Prefix) bool { + switch p { + case PrefixCS, PrefixDS, PrefixES, PrefixFS, PrefixGS, PrefixSS: + return true + } + return false +} + +// The Op definitions and string list are in tables.go. + +var prefixNames = map[Prefix]string{ + PrefixCS: "CS", + PrefixDS: "DS", + PrefixES: "ES", + PrefixFS: "FS", + PrefixGS: "GS", + PrefixSS: "SS", + PrefixLOCK: "LOCK", + PrefixREP: "REP", + PrefixREPN: "REPN", + PrefixAddrSize: "ADDRSIZE", + PrefixDataSize: "DATASIZE", + PrefixAddr16: "ADDR16", + PrefixData16: "DATA16", + PrefixAddr32: "ADDR32", + PrefixData32: "DATA32", + PrefixBND: "BND", + PrefixXACQUIRE: "XACQUIRE", + PrefixXRELEASE: "XRELEASE", + PrefixREX: "REX", + PrefixPT: "PT", + PrefixPN: "PN", +} + +var regNames = [...]string{ + AL: "AL", + CL: "CL", + BL: "BL", + DL: "DL", + AH: "AH", + CH: "CH", + BH: "BH", + DH: "DH", + SPB: "SPB", + BPB: "BPB", + SIB: "SIB", + DIB: "DIB", + R8B: "R8B", + R9B: "R9B", + R10B: "R10B", + R11B: "R11B", + R12B: "R12B", + R13B: "R13B", + R14B: "R14B", + R15B: "R15B", + AX: "AX", + CX: "CX", + BX: "BX", + DX: "DX", + SP: "SP", + BP: "BP", + SI: "SI", + DI: "DI", + R8W: "R8W", + R9W: "R9W", + R10W: "R10W", + R11W: "R11W", + R12W: "R12W", + R13W: "R13W", + R14W: "R14W", + R15W: "R15W", + EAX: "EAX", + ECX: "ECX", + EDX: "EDX", + EBX: "EBX", + ESP: "ESP", + EBP: "EBP", + ESI: "ESI", + EDI: "EDI", + R8L: "R8L", + R9L: "R9L", + R10L: "R10L", + R11L: "R11L", + R12L: "R12L", + R13L: "R13L", + R14L: "R14L", + R15L: "R15L", + RAX: "RAX", + RCX: "RCX", + RDX: "RDX", + RBX: "RBX", + RSP: "RSP", + RBP: "RBP", + RSI: "RSI", + RDI: "RDI", + R8: "R8", + R9: "R9", + R10: "R10", + R11: "R11", + R12: "R12", + R13: "R13", + R14: "R14", + R15: "R15", + IP: "IP", + EIP: "EIP", + RIP: "RIP", + F0: "F0", + F1: "F1", + F2: "F2", + F3: "F3", + F4: "F4", + F5: "F5", + F6: "F6", + F7: "F7", + M0: "M0", + M1: "M1", + M2: "M2", + M3: "M3", + M4: "M4", + M5: "M5", + M6: "M6", + M7: "M7", + X0: "X0", + X1: "X1", + X2: "X2", + X3: "X3", + X4: "X4", + X5: "X5", + X6: "X6", + X7: "X7", + X8: "X8", + X9: "X9", + X10: "X10", + X11: "X11", + X12: "X12", + X13: "X13", + X14: "X14", + X15: "X15", + CS: "CS", + SS: "SS", + DS: "DS", + ES: "ES", + FS: "FS", + GS: "GS", + GDTR: "GDTR", + IDTR: "IDTR", + LDTR: "LDTR", + MSW: "MSW", + TASK: "TASK", + CR0: "CR0", + CR1: "CR1", + CR2: "CR2", + CR3: "CR3", + CR4: "CR4", + CR5: "CR5", + CR6: "CR6", + CR7: "CR7", + CR8: "CR8", + CR9: "CR9", + CR10: "CR10", + CR11: "CR11", + CR12: "CR12", + CR13: "CR13", + CR14: "CR14", + CR15: "CR15", + DR0: "DR0", + DR1: "DR1", + DR2: "DR2", + DR3: "DR3", + DR4: "DR4", + DR5: "DR5", + DR6: "DR6", + DR7: "DR7", + DR8: "DR8", + DR9: "DR9", + DR10: "DR10", + DR11: "DR11", + DR12: "DR12", + DR13: "DR13", + DR14: "DR14", + DR15: "DR15", + TR0: "TR0", + TR1: "TR1", + TR2: "TR2", + TR3: "TR3", + TR4: "TR4", + TR5: "TR5", + TR6: "TR6", + TR7: "TR7", +} diff --git a/vendor/golang.org/x/arch/x86/x86asm/intel.go b/vendor/golang.org/x/arch/x86/x86asm/intel.go new file mode 100644 index 00000000..63fa2cfc --- /dev/null +++ b/vendor/golang.org/x/arch/x86/x86asm/intel.go @@ -0,0 +1,532 @@ +// Copyright 2014 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package x86asm + +import ( + "fmt" + "strings" +) + +// IntelSyntax returns the Intel assembler syntax for the instruction, as defined by Intel's XED tool. +func IntelSyntax(inst Inst) string { + var iargs []Arg + for _, a := range inst.Args { + if a == nil { + break + } + iargs = append(iargs, a) + } + + switch inst.Op { + case INSB, INSD, INSW, OUTSB, OUTSD, OUTSW, LOOPNE, JCXZ, JECXZ, JRCXZ, LOOP, LOOPE, MOV, XLATB: + if inst.Op == MOV && (inst.Opcode>>16)&0xFFFC != 0x0F20 { + break + } + for i, p := range inst.Prefix { + if p&0xFF == PrefixAddrSize { + inst.Prefix[i] &^= PrefixImplicit + } + } + } + + switch inst.Op { + case MOV: + dst, _ := inst.Args[0].(Reg) + src, _ := inst.Args[1].(Reg) + if ES <= dst && dst <= GS && EAX <= src && src <= R15L { + src -= EAX - AX + iargs[1] = src + } + if ES <= dst && dst <= GS && RAX <= src && src <= R15 { + src -= RAX - AX + iargs[1] = src + } + + if inst.Opcode>>24&^3 == 0xA0 { + for i, p := range inst.Prefix { + if p&0xFF == PrefixAddrSize { + inst.Prefix[i] |= PrefixImplicit + } + } + } + } + + switch inst.Op { + case AAM, AAD: + if imm, ok := iargs[0].(Imm); ok { + if inst.DataSize == 32 { + iargs[0] = Imm(uint32(int8(imm))) + } else if inst.DataSize == 16 { + iargs[0] = Imm(uint16(int8(imm))) + } + } + + case PUSH: + if imm, ok := iargs[0].(Imm); ok { + iargs[0] = Imm(uint32(imm)) + } + } + + for _, p := range inst.Prefix { + if p&PrefixImplicit != 0 { + for j, pj := range inst.Prefix { + if pj&0xFF == p&0xFF { + inst.Prefix[j] |= PrefixImplicit + } + } + } + } + + if inst.Op != 0 { + for i, p := range inst.Prefix { + switch p &^ PrefixIgnored { + case PrefixData16, PrefixData32, PrefixCS, PrefixDS, PrefixES, PrefixSS: + inst.Prefix[i] |= PrefixImplicit + } + if p.IsREX() { + inst.Prefix[i] |= PrefixImplicit + } + if p.IsVEX() { + if p == PrefixVEX3Bytes { + inst.Prefix[i+2] |= PrefixImplicit + } + inst.Prefix[i] |= PrefixImplicit + inst.Prefix[i+1] |= PrefixImplicit + } + } + } + + if isLoop[inst.Op] || inst.Op == JCXZ || inst.Op == JECXZ || inst.Op == JRCXZ { + for i, p := range inst.Prefix { + if p == PrefixPT || p == PrefixPN { + inst.Prefix[i] |= PrefixImplicit + } + } + } + + switch inst.Op { + case AAA, AAS, CBW, CDQE, CLC, CLD, CLI, CLTS, CMC, CPUID, CQO, CWD, DAA, DAS, + FDECSTP, FINCSTP, FNCLEX, FNINIT, FNOP, FWAIT, HLT, + ICEBP, INSB, INSD, INSW, INT, INTO, INVD, IRET, IRETQ, + LAHF, LEAVE, LRET, MONITOR, MWAIT, NOP, OUTSB, OUTSD, OUTSW, + PAUSE, POPA, POPF, POPFQ, PUSHA, PUSHF, PUSHFQ, + RDMSR, RDPMC, RDTSC, RDTSCP, RET, RSM, + SAHF, STC, STD, STI, SYSENTER, SYSEXIT, SYSRET, + UD2, WBINVD, WRMSR, XEND, XLATB, XTEST: + + if inst.Op == NOP && inst.Opcode>>24 != 0x90 { + break + } + if inst.Op == RET && inst.Opcode>>24 != 0xC3 { + break + } + if inst.Op == INT && inst.Opcode>>24 != 0xCC { + break + } + if inst.Op == LRET && inst.Opcode>>24 != 0xcb { + break + } + for i, p := range inst.Prefix { + if p&0xFF == PrefixDataSize { + inst.Prefix[i] &^= PrefixImplicit | PrefixIgnored + } + } + + case 0: + // ok + } + + switch inst.Op { + case INSB, INSD, INSW, OUTSB, OUTSD, OUTSW, MONITOR, MWAIT, XLATB: + iargs = nil + + case STOSB, STOSW, STOSD, STOSQ: + iargs = iargs[:1] + + case LODSB, LODSW, LODSD, LODSQ, SCASB, SCASW, SCASD, SCASQ: + iargs = iargs[1:] + } + + const ( + haveData16 = 1 << iota + haveData32 + haveAddr16 + haveAddr32 + haveXacquire + haveXrelease + haveLock + haveHintTaken + haveHintNotTaken + haveBnd + ) + var prefixBits uint32 + prefix := "" + for _, p := range inst.Prefix { + if p == 0 { + break + } + if p&0xFF == 0xF3 { + prefixBits &^= haveBnd + } + if p&(PrefixImplicit|PrefixIgnored) != 0 { + continue + } + switch p { + default: + prefix += strings.ToLower(p.String()) + " " + case PrefixCS, PrefixDS, PrefixES, PrefixFS, PrefixGS, PrefixSS: + if inst.Op == 0 { + prefix += strings.ToLower(p.String()) + " " + } + case PrefixREPN: + prefix += "repne " + case PrefixLOCK: + prefixBits |= haveLock + case PrefixData16, PrefixDataSize: + prefixBits |= haveData16 + case PrefixData32: + prefixBits |= haveData32 + case PrefixAddrSize, PrefixAddr16: + prefixBits |= haveAddr16 + case PrefixAddr32: + prefixBits |= haveAddr32 + case PrefixXACQUIRE: + prefixBits |= haveXacquire + case PrefixXRELEASE: + prefixBits |= haveXrelease + case PrefixPT: + prefixBits |= haveHintTaken + case PrefixPN: + prefixBits |= haveHintNotTaken + case PrefixBND: + prefixBits |= haveBnd + } + } + switch inst.Op { + case JMP: + if inst.Opcode>>24 == 0xEB { + prefixBits &^= haveBnd + } + case RET, LRET: + prefixBits &^= haveData16 | haveData32 + } + + if prefixBits&haveXacquire != 0 { + prefix += "xacquire " + } + if prefixBits&haveXrelease != 0 { + prefix += "xrelease " + } + if prefixBits&haveLock != 0 { + prefix += "lock " + } + if prefixBits&haveBnd != 0 { + prefix += "bnd " + } + if prefixBits&haveHintTaken != 0 { + prefix += "hint-taken " + } + if prefixBits&haveHintNotTaken != 0 { + prefix += "hint-not-taken " + } + if prefixBits&haveAddr16 != 0 { + prefix += "addr16 " + } + if prefixBits&haveAddr32 != 0 { + prefix += "addr32 " + } + if prefixBits&haveData16 != 0 { + prefix += "data16 " + } + if prefixBits&haveData32 != 0 { + prefix += "data32 " + } + + if inst.Op == 0 { + if prefix == "" { + return "<no instruction>" + } + return prefix[:len(prefix)-1] + } + + var args []string + for _, a := range iargs { + if a == nil { + break + } + args = append(args, intelArg(&inst, a)) + } + + var op string + switch inst.Op { + case NOP: + if inst.Opcode>>24 == 0x0F { + if inst.DataSize == 16 { + args = append(args, "ax") + } else { + args = append(args, "eax") + } + } + + case BLENDVPD, BLENDVPS, PBLENDVB: + args = args[:2] + + case INT: + if inst.Opcode>>24 == 0xCC { + args = nil + op = "int3" + } + + case LCALL, LJMP: + if len(args) == 2 { + args[0], args[1] = args[1], args[0] + } + + case FCHS, FABS, FTST, FLDPI, FLDL2E, FLDLG2, F2XM1, FXAM, FLD1, FLDL2T, FSQRT, FRNDINT, FCOS, FSIN: + if len(args) == 0 { + args = append(args, "st0") + } + + case FPTAN, FSINCOS, FUCOMPP, FCOMPP, FYL2X, FPATAN, FXTRACT, FPREM1, FPREM, FYL2XP1, FSCALE: + if len(args) == 0 { + args = []string{"st0", "st1"} + } + + case FST, FSTP, FISTTP, FIST, FISTP, FBSTP: + if len(args) == 1 { + args = append(args, "st0") + } + + case FLD, FXCH, FCOM, FCOMP, FIADD, FIMUL, FICOM, FICOMP, FISUBR, FIDIV, FUCOM, FUCOMP, FILD, FBLD, FADD, FMUL, FSUB, FSUBR, FISUB, FDIV, FDIVR, FIDIVR: + if len(args) == 1 { + args = []string{"st0", args[0]} + } + + case MASKMOVDQU, MASKMOVQ, XLATB, OUTSB, OUTSW, OUTSD: + FixSegment: + for i := len(inst.Prefix) - 1; i >= 0; i-- { + p := inst.Prefix[i] & 0xFF + switch p { + case PrefixCS, PrefixES, PrefixFS, PrefixGS, PrefixSS: + if inst.Mode != 64 || p == PrefixFS || p == PrefixGS { + args = append(args, strings.ToLower((inst.Prefix[i] & 0xFF).String())) + break FixSegment + } + case PrefixDS: + if inst.Mode != 64 { + break FixSegment + } + } + } + } + + if op == "" { + op = intelOp[inst.Op] + } + if op == "" { + op = strings.ToLower(inst.Op.String()) + } + if args != nil { + op += " " + strings.Join(args, ", ") + } + return prefix + op +} + +func intelArg(inst *Inst, arg Arg) string { + switch a := arg.(type) { + case Imm: + if inst.Mode == 32 { + return fmt.Sprintf("%#x", uint32(a)) + } + if Imm(int32(a)) == a { + return fmt.Sprintf("%#x", int64(a)) + } + return fmt.Sprintf("%#x", uint64(a)) + case Mem: + if a.Base == EIP { + a.Base = RIP + } + prefix := "" + switch inst.MemBytes { + case 1: + prefix = "byte " + case 2: + prefix = "word " + case 4: + prefix = "dword " + case 8: + prefix = "qword " + case 16: + prefix = "xmmword " + case 32: + prefix = "ymmword " + } + switch inst.Op { + case INVLPG: + prefix = "byte " + case STOSB, MOVSB, CMPSB, LODSB, SCASB: + prefix = "byte " + case STOSW, MOVSW, CMPSW, LODSW, SCASW: + prefix = "word " + case STOSD, MOVSD, CMPSD, LODSD, SCASD: + prefix = "dword " + case STOSQ, MOVSQ, CMPSQ, LODSQ, SCASQ: + prefix = "qword " + case LAR: + prefix = "word " + case BOUND: + if inst.Mode == 32 { + prefix = "qword " + } else { + prefix = "dword " + } + case PREFETCHW, PREFETCHNTA, PREFETCHT0, PREFETCHT1, PREFETCHT2, CLFLUSH: + prefix = "zmmword " + } + switch inst.Op { + case MOVSB, MOVSW, MOVSD, MOVSQ, CMPSB, CMPSW, CMPSD, CMPSQ, STOSB, STOSW, STOSD, STOSQ, SCASB, SCASW, SCASD, SCASQ, LODSB, LODSW, LODSD, LODSQ: + switch a.Base { + case DI, EDI, RDI: + if a.Segment == ES { + a.Segment = 0 + } + case SI, ESI, RSI: + if a.Segment == DS { + a.Segment = 0 + } + } + case LEA: + a.Segment = 0 + default: + switch a.Base { + case SP, ESP, RSP, BP, EBP, RBP: + if a.Segment == SS { + a.Segment = 0 + } + default: + if a.Segment == DS { + a.Segment = 0 + } + } + } + + if inst.Mode == 64 && a.Segment != FS && a.Segment != GS { + a.Segment = 0 + } + + prefix += "ptr " + if a.Segment != 0 { + prefix += strings.ToLower(a.Segment.String()) + ":" + } + prefix += "[" + if a.Base != 0 { + prefix += intelArg(inst, a.Base) + } + if a.Scale != 0 && a.Index != 0 { + if a.Base != 0 { + prefix += "+" + } + prefix += fmt.Sprintf("%s*%d", intelArg(inst, a.Index), a.Scale) + } + if a.Disp != 0 { + if prefix[len(prefix)-1] == '[' && (a.Disp >= 0 || int64(int32(a.Disp)) != a.Disp) { + prefix += fmt.Sprintf("%#x", uint64(a.Disp)) + } else { + prefix += fmt.Sprintf("%+#x", a.Disp) + } + } + prefix += "]" + return prefix + case Rel: + return fmt.Sprintf(".%+#x", int64(a)) + case Reg: + if int(a) < len(intelReg) && intelReg[a] != "" { + switch inst.Op { + case VMOVDQA, VMOVDQU, VMOVNTDQA, VMOVNTDQ: + return strings.Replace(intelReg[a], "xmm", "ymm", -1) + default: + return intelReg[a] + } + } + } + return strings.ToLower(arg.String()) +} + +var intelOp = map[Op]string{ + JAE: "jnb", + JA: "jnbe", + JGE: "jnl", + JNE: "jnz", + JG: "jnle", + JE: "jz", + SETAE: "setnb", + SETA: "setnbe", + SETGE: "setnl", + SETNE: "setnz", + SETG: "setnle", + SETE: "setz", + CMOVAE: "cmovnb", + CMOVA: "cmovnbe", + CMOVGE: "cmovnl", + CMOVNE: "cmovnz", + CMOVG: "cmovnle", + CMOVE: "cmovz", + LCALL: "call far", + LJMP: "jmp far", + LRET: "ret far", + ICEBP: "int1", + MOVSD_XMM: "movsd", + XLATB: "xlat", +} + +var intelReg = [...]string{ + F0: "st0", + F1: "st1", + F2: "st2", + F3: "st3", + F4: "st4", + F5: "st5", + F6: "st6", + F7: "st7", + M0: "mmx0", + M1: "mmx1", + M2: "mmx2", + M3: "mmx3", + M4: "mmx4", + M5: "mmx5", + M6: "mmx6", + M7: "mmx7", + X0: "xmm0", + X1: "xmm1", + X2: "xmm2", + X3: "xmm3", + X4: "xmm4", + X5: "xmm5", + X6: "xmm6", + X7: "xmm7", + X8: "xmm8", + X9: "xmm9", + X10: "xmm10", + X11: "xmm11", + X12: "xmm12", + X13: "xmm13", + X14: "xmm14", + X15: "xmm15", + + // TODO: Maybe the constants are named wrong. + SPB: "spl", + BPB: "bpl", + SIB: "sil", + DIB: "dil", + + R8L: "r8d", + R9L: "r9d", + R10L: "r10d", + R11L: "r11d", + R12L: "r12d", + R13L: "r13d", + R14L: "r14d", + R15L: "r15d", +} diff --git a/vendor/golang.org/x/arch/x86/x86asm/plan9x.go b/vendor/golang.org/x/arch/x86/x86asm/plan9x.go new file mode 100644 index 00000000..41cfc08f --- /dev/null +++ b/vendor/golang.org/x/arch/x86/x86asm/plan9x.go @@ -0,0 +1,362 @@ +// Copyright 2014 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package x86asm + +import ( + "fmt" + "strings" +) + +// GoSyntax returns the Go assembler syntax for the instruction. +// The syntax was originally defined by Plan 9. +// The pc is the program counter of the instruction, used for expanding +// PC-relative addresses into absolute ones. +// The symname function queries the symbol table for the program +// being disassembled. Given a target address it returns the name and base +// address of the symbol containing the target, if any; otherwise it returns "", 0. +func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64)) string { + if symname == nil { + symname = func(uint64) (string, uint64) { return "", 0 } + } + var args []string + for i := len(inst.Args) - 1; i >= 0; i-- { + a := inst.Args[i] + if a == nil { + continue + } + args = append(args, plan9Arg(&inst, pc, symname, a)) + } + + var rep string + var last Prefix + for _, p := range inst.Prefix { + if p == 0 || p.IsREX() || p.IsVEX() { + break + } + + switch { + // Don't show prefixes implied by the instruction text. + case p&0xFF00 == PrefixImplicit: + continue + // Only REP and REPN are recognized repeaters. Plan 9 syntax + // treats them as separate opcodes. + case p&0xFF == PrefixREP: + rep = "REP; " + case p&0xFF == PrefixREPN: + rep = "REPNE; " + default: + last = p + } + } + + prefix := "" + switch last & 0xFF { + case 0, 0x66, 0x67: + // ignore + default: + prefix += last.String() + " " + } + + op := inst.Op.String() + if plan9Suffix[inst.Op] { + s := inst.DataSize + if inst.MemBytes != 0 { + s = inst.MemBytes * 8 + } + switch s { + case 8: + op += "B" + case 16: + op += "W" + case 32: + op += "L" + case 64: + op += "Q" + } + } + + if args != nil { + op += " " + strings.Join(args, ", ") + } + + return rep + prefix + op +} + +func plan9Arg(inst *Inst, pc uint64, symname func(uint64) (string, uint64), arg Arg) string { + switch a := arg.(type) { + case Reg: + return plan9Reg[a] + case Rel: + if pc == 0 { + break + } + // If the absolute address is the start of a symbol, use the name. + // Otherwise use the raw address, so that things like relative + // jumps show up as JMP 0x123 instead of JMP f+10(SB). + // It is usually easier to search for 0x123 than to do the mental + // arithmetic to find f+10. + addr := pc + uint64(inst.Len) + uint64(a) + if s, base := symname(addr); s != "" && addr == base { + return fmt.Sprintf("%s(SB)", s) + } + return fmt.Sprintf("%#x", addr) + + case Imm: + if s, base := symname(uint64(a)); s != "" { + suffix := "" + if uint64(a) != base { + suffix = fmt.Sprintf("%+d", uint64(a)-base) + } + return fmt.Sprintf("$%s%s(SB)", s, suffix) + } + if inst.Mode == 32 { + return fmt.Sprintf("$%#x", uint32(a)) + } + if Imm(int32(a)) == a { + return fmt.Sprintf("$%#x", int64(a)) + } + return fmt.Sprintf("$%#x", uint64(a)) + case Mem: + if a.Segment == 0 && a.Disp != 0 && a.Base == 0 && (a.Index == 0 || a.Scale == 0) { + if s, base := symname(uint64(a.Disp)); s != "" { + suffix := "" + if uint64(a.Disp) != base { + suffix = fmt.Sprintf("%+d", uint64(a.Disp)-base) + } + return fmt.Sprintf("%s%s(SB)", s, suffix) + } + } + s := "" + if a.Segment != 0 { + s += fmt.Sprintf("%s:", plan9Reg[a.Segment]) + } + if a.Disp != 0 { + s += fmt.Sprintf("%#x", a.Disp) + } else { + s += "0" + } + if a.Base != 0 { + s += fmt.Sprintf("(%s)", plan9Reg[a.Base]) + } + if a.Index != 0 && a.Scale != 0 { + s += fmt.Sprintf("(%s*%d)", plan9Reg[a.Index], a.Scale) + } + return s + } + return arg.String() +} + +var plan9Suffix = [maxOp + 1]bool{ + ADC: true, + ADD: true, + AND: true, + BSF: true, + BSR: true, + BT: true, + BTC: true, + BTR: true, + BTS: true, + CMP: true, + CMPXCHG: true, + CVTSI2SD: true, + CVTSI2SS: true, + CVTSD2SI: true, + CVTSS2SI: true, + CVTTSD2SI: true, + CVTTSS2SI: true, + DEC: true, + DIV: true, + FLDENV: true, + FRSTOR: true, + IDIV: true, + IMUL: true, + IN: true, + INC: true, + LEA: true, + MOV: true, + MOVNTI: true, + MUL: true, + NEG: true, + NOP: true, + NOT: true, + OR: true, + OUT: true, + POP: true, + POPA: true, + PUSH: true, + PUSHA: true, + RCL: true, + RCR: true, + ROL: true, + ROR: true, + SAR: true, + SBB: true, + SHL: true, + SHLD: true, + SHR: true, + SHRD: true, + SUB: true, + TEST: true, + XADD: true, + XCHG: true, + XOR: true, +} + +var plan9Reg = [...]string{ + AL: "AL", + CL: "CL", + BL: "BL", + DL: "DL", + AH: "AH", + CH: "CH", + BH: "BH", + DH: "DH", + SPB: "SP", + BPB: "BP", + SIB: "SI", + DIB: "DI", + R8B: "R8", + R9B: "R9", + R10B: "R10", + R11B: "R11", + R12B: "R12", + R13B: "R13", + R14B: "R14", + R15B: "R15", + AX: "AX", + CX: "CX", + BX: "BX", + DX: "DX", + SP: "SP", + BP: "BP", + SI: "SI", + DI: "DI", + R8W: "R8", + R9W: "R9", + R10W: "R10", + R11W: "R11", + R12W: "R12", + R13W: "R13", + R14W: "R14", + R15W: "R15", + EAX: "AX", + ECX: "CX", + EDX: "DX", + EBX: "BX", + ESP: "SP", + EBP: "BP", + ESI: "SI", + EDI: "DI", + R8L: "R8", + R9L: "R9", + R10L: "R10", + R11L: "R11", + R12L: "R12", + R13L: "R13", + R14L: "R14", + R15L: "R15", + RAX: "AX", + RCX: "CX", + RDX: "DX", + RBX: "BX", + RSP: "SP", + RBP: "BP", + RSI: "SI", + RDI: "DI", + R8: "R8", + R9: "R9", + R10: "R10", + R11: "R11", + R12: "R12", + R13: "R13", + R14: "R14", + R15: "R15", + IP: "IP", + EIP: "IP", + RIP: "IP", + F0: "F0", + F1: "F1", + F2: "F2", + F3: "F3", + F4: "F4", + F5: "F5", + F6: "F6", + F7: "F7", + M0: "M0", + M1: "M1", + M2: "M2", + M3: "M3", + M4: "M4", + M5: "M5", + M6: "M6", + M7: "M7", + X0: "X0", + X1: "X1", + X2: "X2", + X3: "X3", + X4: "X4", + X5: "X5", + X6: "X6", + X7: "X7", + X8: "X8", + X9: "X9", + X10: "X10", + X11: "X11", + X12: "X12", + X13: "X13", + X14: "X14", + X15: "X15", + CS: "CS", + SS: "SS", + DS: "DS", + ES: "ES", + FS: "FS", + GS: "GS", + GDTR: "GDTR", + IDTR: "IDTR", + LDTR: "LDTR", + MSW: "MSW", + TASK: "TASK", + CR0: "CR0", + CR1: "CR1", + CR2: "CR2", + CR3: "CR3", + CR4: "CR4", + CR5: "CR5", + CR6: "CR6", + CR7: "CR7", + CR8: "CR8", + CR9: "CR9", + CR10: "CR10", + CR11: "CR11", + CR12: "CR12", + CR13: "CR13", + CR14: "CR14", + CR15: "CR15", + DR0: "DR0", + DR1: "DR1", + DR2: "DR2", + DR3: "DR3", + DR4: "DR4", + DR5: "DR5", + DR6: "DR6", + DR7: "DR7", + DR8: "DR8", + DR9: "DR9", + DR10: "DR10", + DR11: "DR11", + DR12: "DR12", + DR13: "DR13", + DR14: "DR14", + DR15: "DR15", + TR0: "TR0", + TR1: "TR1", + TR2: "TR2", + TR3: "TR3", + TR4: "TR4", + TR5: "TR5", + TR6: "TR6", + TR7: "TR7", +} diff --git a/vendor/golang.org/x/arch/x86/x86asm/tables.go b/vendor/golang.org/x/arch/x86/x86asm/tables.go new file mode 100644 index 00000000..5b39b744 --- /dev/null +++ b/vendor/golang.org/x/arch/x86/x86asm/tables.go @@ -0,0 +1,9902 @@ +// DO NOT EDIT +// generated by: x86map -fmt=decoder ../x86.csv + +package x86asm + +var decoder = [...]uint16{ + uint16(xFail), + /*1*/ uint16(xCondByte), 243, + 0x00, 490, + 0x01, 496, + 0x02, 525, + 0x03, 531, + 0x04, 560, + 0x05, 566, + 0x06, 595, + 0x07, 602, + 0x08, 609, + 0x09, 615, + 0x0A, 644, + 0x0B, 650, + 0x0C, 679, + 0x0D, 685, + 0x0E, 714, + 0x0F, 721, + 0x10, 8026, + 0x11, 8032, + 0x12, 8061, + 0x13, 8067, + 0x14, 8096, + 0x15, 8102, + 0x16, 8131, + 0x17, 8138, + 0x18, 8145, + 0x19, 8151, + 0x1A, 8180, + 0x1B, 8186, + 0x1C, 8215, + 0x1D, 8221, + 0x1E, 8250, + 0x1F, 8257, + 0x20, 8264, + 0x21, 8270, + 0x22, 8299, + 0x23, 8305, + 0x24, 8334, + 0x25, 8340, + 0x27, 8369, + 0x28, 8375, + 0x29, 8381, + 0x2A, 8410, + 0x2B, 8452, + 0x2C, 8481, + 0x2D, 8487, + 0x2F, 8516, + 0x30, 8522, + 0x31, 8528, + 0x32, 8557, + 0x33, 8563, + 0x34, 8592, + 0x35, 8598, + 0x37, 8627, + 0x38, 8633, + 0x39, 8639, + 0x3A, 8668, + 0x3B, 8674, + 0x3C, 8703, + 0x3D, 8709, + 0x3F, 8738, + 0x40, 8744, + 0x41, 8744, + 0x42, 8744, + 0x43, 8744, + 0x44, 8744, + 0x45, 8744, + 0x46, 8744, + 0x47, 8744, + 0x48, 8759, + 0x49, 8759, + 0x4a, 8759, + 0x4b, 8759, + 0x4c, 8759, + 0x4d, 8759, + 0x4e, 8759, + 0x4f, 8759, + 0x50, 8774, + 0x51, 8774, + 0x52, 8774, + 0x53, 8774, + 0x54, 8774, + 0x55, 8774, + 0x56, 8774, + 0x57, 8774, + 0x58, 8801, + 0x59, 8801, + 0x5a, 8801, + 0x5b, 8801, + 0x5c, 8801, + 0x5d, 8801, + 0x5e, 8801, + 0x5f, 8801, + 0x60, 8828, + 0x61, 8841, + 0x62, 8854, + 0x63, 8873, + 0x68, 8904, + 0x69, 8923, + 0x6A, 8958, + 0x6B, 8963, + 0x6C, 8998, + 0x6D, 9001, + 0x6E, 9014, + 0x6F, 9017, + 0x70, 9090, + 0x71, 9095, + 0x72, 9100, + 0x73, 9105, + 0x74, 9110, + 0x75, 9115, + 0x76, 9120, + 0x77, 9125, + 0x78, 9152, + 0x79, 9157, + 0x7A, 9162, + 0x7B, 9167, + 0x7C, 9172, + 0x7D, 9177, + 0x7E, 9182, + 0x7F, 9187, + 0x80, 9252, + 0x81, 9309, + 0x83, 9550, + 0x84, 9791, + 0x85, 9797, + 0x86, 9826, + 0x87, 9832, + 0x88, 9861, + 0x89, 9867, + 0x8A, 9889, + 0x8B, 9895, + 0x8C, 9917, + 0x8D, 9946, + 0x8E, 9975, + 0x8F, 10004, + 0x90, 10040, + 0x91, 10040, + 0x92, 10040, + 0x93, 10040, + 0x94, 10040, + 0x95, 10040, + 0x96, 10040, + 0x97, 10040, + 0x98, 10066, + 0x99, 10086, + 0x9A, 10106, + 0x9B, 10123, + 0x9C, 10126, + 0x9D, 10149, + 0x9E, 10172, + 0x9F, 10175, + 0xA0, 10178, + 0xA1, 10197, + 0xA2, 10219, + 0xA3, 10238, + 0xA4, 10260, + 0xA5, 10263, + 0xA6, 10283, + 0xA7, 10286, + 0xA8, 10306, + 0xA9, 10312, + 0xAA, 10341, + 0xAB, 10344, + 0xAC, 10364, + 0xAD, 10367, + 0xAE, 10387, + 0xAF, 10390, + 0xb0, 10410, + 0xb1, 10410, + 0xb2, 10410, + 0xb3, 10410, + 0xb4, 10410, + 0xb5, 10410, + 0xb6, 10410, + 0xb7, 10410, + 0xb8, 10416, + 0xb9, 10416, + 0xba, 10416, + 0xbb, 10416, + 0xbc, 10416, + 0xbd, 10416, + 0xbe, 10416, + 0xbf, 10416, + 0xC0, 10445, + 0xC1, 10496, + 0xC2, 10694, + 0xC3, 10699, + 0xC4, 10702, + 0xC5, 10721, + 0xC6, 10740, + 0xC7, 10764, + 0xC8, 10825, + 0xC9, 10832, + 0xCA, 10855, + 0xCB, 10860, + 0xCC, 10863, + 0xCD, 10867, + 0xCE, 10872, + 0xCF, 10878, + 0xD0, 10898, + 0xD1, 10942, + 0xD2, 11133, + 0xD3, 11177, + 0xD4, 11368, + 0xD5, 11376, + 0xD7, 11384, + 0xD8, 11397, + 0xD9, 11606, + 0xDA, 11815, + 0xDB, 11947, + 0xDC, 12118, + 0xDD, 12287, + 0xDE, 12426, + 0xDF, 12600, + 0xE0, 12711, + 0xE1, 12716, + 0xE2, 12721, + 0xE3, 12726, + 0xE4, 12752, + 0xE5, 12758, + 0xE6, 12780, + 0xE7, 12786, + 0xE8, 12844, + 0xE9, 12875, + 0xEA, 12906, + 0xEB, 12923, + 0xEC, 12928, + 0xED, 12933, + 0xEE, 12952, + 0xEF, 12957, + 0xF1, 12976, + 0xF4, 12979, + 0xF5, 12982, + 0xF6, 12985, + 0xF7, 13024, + 0xF8, 13200, + 0xF9, 13203, + 0xFA, 13206, + 0xFB, 13209, + 0xFC, 13212, + 0xFD, 13215, + 0xFE, 13218, + 0xFF, 13235, + uint16(xFail), + /*490*/ uint16(xSetOp), uint16(ADD), + /*492*/ uint16(xReadSlashR), + /*493*/ uint16(xArgRM8), + /*494*/ uint16(xArgR8), + /*495*/ uint16(xMatch), + /*496*/ uint16(xCondIs64), 499, 515, + /*499*/ uint16(xCondDataSize), 503, 509, 0, + /*503*/ uint16(xSetOp), uint16(ADD), + /*505*/ uint16(xReadSlashR), + /*506*/ uint16(xArgRM16), + /*507*/ uint16(xArgR16), + /*508*/ uint16(xMatch), + /*509*/ uint16(xSetOp), uint16(ADD), + /*511*/ uint16(xReadSlashR), + /*512*/ uint16(xArgRM32), + /*513*/ uint16(xArgR32), + /*514*/ uint16(xMatch), + /*515*/ uint16(xCondDataSize), 503, 509, 519, + /*519*/ uint16(xSetOp), uint16(ADD), + /*521*/ uint16(xReadSlashR), + /*522*/ uint16(xArgRM64), + /*523*/ uint16(xArgR64), + /*524*/ uint16(xMatch), + /*525*/ uint16(xSetOp), uint16(ADD), + /*527*/ uint16(xReadSlashR), + /*528*/ uint16(xArgR8), + /*529*/ uint16(xArgRM8), + /*530*/ uint16(xMatch), + /*531*/ uint16(xCondIs64), 534, 550, + /*534*/ uint16(xCondDataSize), 538, 544, 0, + /*538*/ uint16(xSetOp), uint16(ADD), + /*540*/ uint16(xReadSlashR), + /*541*/ uint16(xArgR16), + /*542*/ uint16(xArgRM16), + /*543*/ uint16(xMatch), + /*544*/ uint16(xSetOp), uint16(ADD), + /*546*/ uint16(xReadSlashR), + /*547*/ uint16(xArgR32), + /*548*/ uint16(xArgRM32), + /*549*/ uint16(xMatch), + /*550*/ uint16(xCondDataSize), 538, 544, 554, + /*554*/ uint16(xSetOp), uint16(ADD), + /*556*/ uint16(xReadSlashR), + /*557*/ uint16(xArgR64), + /*558*/ uint16(xArgRM64), + /*559*/ uint16(xMatch), + /*560*/ uint16(xSetOp), uint16(ADD), + /*562*/ uint16(xReadIb), + /*563*/ uint16(xArgAL), + /*564*/ uint16(xArgImm8u), + /*565*/ uint16(xMatch), + /*566*/ uint16(xCondIs64), 569, 585, + /*569*/ uint16(xCondDataSize), 573, 579, 0, + /*573*/ uint16(xSetOp), uint16(ADD), + /*575*/ uint16(xReadIw), + /*576*/ uint16(xArgAX), + /*577*/ uint16(xArgImm16), + /*578*/ uint16(xMatch), + /*579*/ uint16(xSetOp), uint16(ADD), + /*581*/ uint16(xReadId), + /*582*/ uint16(xArgEAX), + /*583*/ uint16(xArgImm32), + /*584*/ uint16(xMatch), + /*585*/ uint16(xCondDataSize), 573, 579, 589, + /*589*/ uint16(xSetOp), uint16(ADD), + /*591*/ uint16(xReadId), + /*592*/ uint16(xArgRAX), + /*593*/ uint16(xArgImm32), + /*594*/ uint16(xMatch), + /*595*/ uint16(xCondIs64), 598, 0, + /*598*/ uint16(xSetOp), uint16(PUSH), + /*600*/ uint16(xArgES), + /*601*/ uint16(xMatch), + /*602*/ uint16(xCondIs64), 605, 0, + /*605*/ uint16(xSetOp), uint16(POP), + /*607*/ uint16(xArgES), + /*608*/ uint16(xMatch), + /*609*/ uint16(xSetOp), uint16(OR), + /*611*/ uint16(xReadSlashR), + /*612*/ uint16(xArgRM8), + /*613*/ uint16(xArgR8), + /*614*/ uint16(xMatch), + /*615*/ uint16(xCondIs64), 618, 634, + /*618*/ uint16(xCondDataSize), 622, 628, 0, + /*622*/ uint16(xSetOp), uint16(OR), + /*624*/ uint16(xReadSlashR), + /*625*/ uint16(xArgRM16), + /*626*/ uint16(xArgR16), + /*627*/ uint16(xMatch), + /*628*/ uint16(xSetOp), uint16(OR), + /*630*/ uint16(xReadSlashR), + /*631*/ uint16(xArgRM32), + /*632*/ uint16(xArgR32), + /*633*/ uint16(xMatch), + /*634*/ uint16(xCondDataSize), 622, 628, 638, + /*638*/ uint16(xSetOp), uint16(OR), + /*640*/ uint16(xReadSlashR), + /*641*/ uint16(xArgRM64), + /*642*/ uint16(xArgR64), + /*643*/ uint16(xMatch), + /*644*/ uint16(xSetOp), uint16(OR), + /*646*/ uint16(xReadSlashR), + /*647*/ uint16(xArgR8), + /*648*/ uint16(xArgRM8), + /*649*/ uint16(xMatch), + /*650*/ uint16(xCondIs64), 653, 669, + /*653*/ uint16(xCondDataSize), 657, 663, 0, + /*657*/ uint16(xSetOp), uint16(OR), + /*659*/ uint16(xReadSlashR), + /*660*/ uint16(xArgR16), + /*661*/ uint16(xArgRM16), + /*662*/ uint16(xMatch), + /*663*/ uint16(xSetOp), uint16(OR), + /*665*/ uint16(xReadSlashR), + /*666*/ uint16(xArgR32), + /*667*/ uint16(xArgRM32), + /*668*/ uint16(xMatch), + /*669*/ uint16(xCondDataSize), 657, 663, 673, + /*673*/ uint16(xSetOp), uint16(OR), + /*675*/ uint16(xReadSlashR), + /*676*/ uint16(xArgR64), + /*677*/ uint16(xArgRM64), + /*678*/ uint16(xMatch), + /*679*/ uint16(xSetOp), uint16(OR), + /*681*/ uint16(xReadIb), + /*682*/ uint16(xArgAL), + /*683*/ uint16(xArgImm8u), + /*684*/ uint16(xMatch), + /*685*/ uint16(xCondIs64), 688, 704, + /*688*/ uint16(xCondDataSize), 692, 698, 0, + /*692*/ uint16(xSetOp), uint16(OR), + /*694*/ uint16(xReadIw), + /*695*/ uint16(xArgAX), + /*696*/ uint16(xArgImm16), + /*697*/ uint16(xMatch), + /*698*/ uint16(xSetOp), uint16(OR), + /*700*/ uint16(xReadId), + /*701*/ uint16(xArgEAX), + /*702*/ uint16(xArgImm32), + /*703*/ uint16(xMatch), + /*704*/ uint16(xCondDataSize), 692, 698, 708, + /*708*/ uint16(xSetOp), uint16(OR), + /*710*/ uint16(xReadId), + /*711*/ uint16(xArgRAX), + /*712*/ uint16(xArgImm32), + /*713*/ uint16(xMatch), + /*714*/ uint16(xCondIs64), 717, 0, + /*717*/ uint16(xSetOp), uint16(PUSH), + /*719*/ uint16(xArgCS), + /*720*/ uint16(xMatch), + /*721*/ uint16(xCondByte), 228, + 0x00, 1180, + 0x01, 1237, + 0x02, 1345, + 0x03, 1367, + 0x05, 1389, + 0x06, 1395, + 0x07, 1398, + 0x08, 1404, + 0x09, 1407, + 0x0B, 1410, + 0x0D, 1413, + 0x10, 1426, + 0x11, 1460, + 0x12, 1494, + 0x13, 1537, + 0x14, 1555, + 0x15, 1573, + 0x16, 1591, + 0x17, 1626, + 0x18, 1644, + 0x1F, 1669, + 0x20, 1690, + 0x21, 1705, + 0x22, 1720, + 0x23, 1735, + 0x24, 1750, + 0x26, 1765, + 0x28, 1780, + 0x29, 1798, + 0x2A, 1816, + 0x2B, 1903, + 0x2C, 1937, + 0x2D, 2024, + 0x2E, 2111, + 0x2F, 2129, + 0x30, 2147, + 0x31, 2150, + 0x32, 2153, + 0x33, 2156, + 0x34, 2159, + 0x35, 2162, + 0x38, 2172, + 0x3A, 3073, + 0x40, 3484, + 0x41, 3513, + 0x42, 3542, + 0x43, 3571, + 0x44, 3600, + 0x45, 3629, + 0x46, 3658, + 0x47, 3687, + 0x48, 3716, + 0x49, 3745, + 0x4A, 3774, + 0x4B, 3803, + 0x4C, 3832, + 0x4D, 3861, + 0x4E, 3890, + 0x4F, 3919, + 0x50, 3948, + 0x51, 3966, + 0x52, 4000, + 0x53, 4018, + 0x54, 4036, + 0x55, 4054, + 0x56, 4072, + 0x57, 4090, + 0x58, 4108, + 0x59, 4142, + 0x5A, 4176, + 0x5B, 4210, + 0x5C, 4236, + 0x5D, 4270, + 0x5E, 4304, + 0x5F, 4338, + 0x60, 4372, + 0x61, 4390, + 0x62, 4408, + 0x63, 4426, + 0x64, 4444, + 0x65, 4462, + 0x66, 4480, + 0x67, 4498, + 0x68, 4516, + 0x69, 4534, + 0x6A, 4552, + 0x6B, 4570, + 0x6C, 4588, + 0x6D, 4598, + 0x6E, 4608, + 0x6F, 4675, + 0x70, 4701, + 0x71, 4743, + 0x72, 4806, + 0x73, 4869, + 0x74, 4934, + 0x75, 4952, + 0x76, 4970, + 0x77, 4988, + 0x7C, 4991, + 0x7D, 5009, + 0x7E, 5027, + 0x7F, 5104, + 0x80, 5130, + 0x81, 5161, + 0x82, 5192, + 0x83, 5223, + 0x84, 5254, + 0x85, 5285, + 0x86, 5316, + 0x87, 5347, + 0x88, 5378, + 0x89, 5409, + 0x8A, 5440, + 0x8B, 5471, + 0x8C, 5502, + 0x8D, 5533, + 0x8E, 5564, + 0x8F, 5595, + 0x90, 5626, + 0x91, 5631, + 0x92, 5636, + 0x93, 5641, + 0x94, 5646, + 0x95, 5651, + 0x96, 5656, + 0x97, 5661, + 0x98, 5666, + 0x99, 5671, + 0x9A, 5676, + 0x9B, 5681, + 0x9C, 5686, + 0x9D, 5691, + 0x9E, 5696, + 0x9F, 5701, + 0xA0, 5706, + 0xA1, 5710, + 0xA2, 5737, + 0xA3, 5740, + 0xA4, 5769, + 0xA5, 5804, + 0xA8, 5836, + 0xA9, 5840, + 0xAA, 5867, + 0xAB, 5870, + 0xAC, 5899, + 0xAD, 5934, + 0xAE, 5966, + 0xAF, 6224, + 0xB0, 6253, + 0xB1, 6259, + 0xB2, 6288, + 0xB3, 6317, + 0xB4, 6346, + 0xB5, 6375, + 0xB6, 6404, + 0xB7, 6433, + 0xB8, 6462, + 0xB9, 6499, + 0xBA, 6502, + 0xBB, 6627, + 0xBC, 6656, + 0xBD, 6723, + 0xBE, 6790, + 0xBF, 6819, + 0xC0, 6848, + 0xC1, 6854, + 0xC2, 6883, + 0xC3, 6925, + 0xC4, 6954, + 0xC5, 6976, + 0xC6, 6998, + 0xC7, 7020, + 0xc8, 7149, + 0xc9, 7149, + 0xca, 7149, + 0xcb, 7149, + 0xcc, 7149, + 0xcd, 7149, + 0xce, 7149, + 0xcf, 7149, + 0xD0, 7172, + 0xD1, 7190, + 0xD2, 7208, + 0xD3, 7226, + 0xD4, 7244, + 0xD5, 7262, + 0xD6, 7280, + 0xD7, 7306, + 0xD8, 7324, + 0xD9, 7342, + 0xDA, 7360, + 0xDB, 7378, + 0xDC, 7396, + 0xDD, 7414, + 0xDE, 7432, + 0xDF, 7450, + 0xE0, 7468, + 0xE1, 7486, + 0xE2, 7504, + 0xE3, 7522, + 0xE4, 7540, + 0xE5, 7558, + 0xE6, 7576, + 0xE7, 7602, + 0xE8, 7620, + 0xE9, 7638, + 0xEA, 7656, + 0xEB, 7674, + 0xEC, 7692, + 0xED, 7710, + 0xEE, 7728, + 0xEF, 7746, + 0xF0, 7764, + 0xF1, 7774, + 0xF2, 7792, + 0xF3, 7810, + 0xF4, 7828, + 0xF5, 7846, + 0xF6, 7864, + 0xF7, 7882, + 0xF8, 7900, + 0xF9, 7918, + 0xFA, 7936, + 0xFB, 7954, + 0xFC, 7972, + 0xFD, 7990, + 0xFE, 8008, + uint16(xFail), + /*1180*/ uint16(xCondSlashR), + 1189, // 0 + 1205, // 1 + 1221, // 2 + 1225, // 3 + 1229, // 4 + 1233, // 5 + 0, // 6 + 0, // 7 + /*1189*/ uint16(xCondDataSize), 1193, 1197, 1201, + /*1193*/ uint16(xSetOp), uint16(SLDT), + /*1195*/ uint16(xArgRM16), + /*1196*/ uint16(xMatch), + /*1197*/ uint16(xSetOp), uint16(SLDT), + /*1199*/ uint16(xArgR32M16), + /*1200*/ uint16(xMatch), + /*1201*/ uint16(xSetOp), uint16(SLDT), + /*1203*/ uint16(xArgR64M16), + /*1204*/ uint16(xMatch), + /*1205*/ uint16(xCondDataSize), 1209, 1213, 1217, + /*1209*/ uint16(xSetOp), uint16(STR), + /*1211*/ uint16(xArgRM16), + /*1212*/ uint16(xMatch), + /*1213*/ uint16(xSetOp), uint16(STR), + /*1215*/ uint16(xArgR32M16), + /*1216*/ uint16(xMatch), + /*1217*/ uint16(xSetOp), uint16(STR), + /*1219*/ uint16(xArgR64M16), + /*1220*/ uint16(xMatch), + /*1221*/ uint16(xSetOp), uint16(LLDT), + /*1223*/ uint16(xArgRM16), + /*1224*/ uint16(xMatch), + /*1225*/ uint16(xSetOp), uint16(LTR), + /*1227*/ uint16(xArgRM16), + /*1228*/ uint16(xMatch), + /*1229*/ uint16(xSetOp), uint16(VERR), + /*1231*/ uint16(xArgRM16), + /*1232*/ uint16(xMatch), + /*1233*/ uint16(xSetOp), uint16(VERW), + /*1235*/ uint16(xArgRM16), + /*1236*/ uint16(xMatch), + /*1237*/ uint16(xCondByte), 8, + 0xC8, 1318, + 0xC9, 1321, + 0xD0, 1324, + 0xD1, 1327, + 0xD5, 1330, + 0xD6, 1333, + 0xF8, 1336, + 0xF9, 1342, + /*1255*/ uint16(xCondSlashR), + 1264, // 0 + 1268, // 1 + 1272, // 2 + 1283, // 3 + 1294, // 4 + 0, // 5 + 1310, // 6 + 1314, // 7 + /*1264*/ uint16(xSetOp), uint16(SGDT), + /*1266*/ uint16(xArgM), + /*1267*/ uint16(xMatch), + /*1268*/ uint16(xSetOp), uint16(SIDT), + /*1270*/ uint16(xArgM), + /*1271*/ uint16(xMatch), + /*1272*/ uint16(xCondIs64), 1275, 1279, + /*1275*/ uint16(xSetOp), uint16(LGDT), + /*1277*/ uint16(xArgM16and32), + /*1278*/ uint16(xMatch), + /*1279*/ uint16(xSetOp), uint16(LGDT), + /*1281*/ uint16(xArgM16and64), + /*1282*/ uint16(xMatch), + /*1283*/ uint16(xCondIs64), 1286, 1290, + /*1286*/ uint16(xSetOp), uint16(LIDT), + /*1288*/ uint16(xArgM16and32), + /*1289*/ uint16(xMatch), + /*1290*/ uint16(xSetOp), uint16(LIDT), + /*1292*/ uint16(xArgM16and64), + /*1293*/ uint16(xMatch), + /*1294*/ uint16(xCondDataSize), 1298, 1302, 1306, + /*1298*/ uint16(xSetOp), uint16(SMSW), + /*1300*/ uint16(xArgRM16), + /*1301*/ uint16(xMatch), + /*1302*/ uint16(xSetOp), uint16(SMSW), + /*1304*/ uint16(xArgR32M16), + /*1305*/ uint16(xMatch), + /*1306*/ uint16(xSetOp), uint16(SMSW), + /*1308*/ uint16(xArgR64M16), + /*1309*/ uint16(xMatch), + /*1310*/ uint16(xSetOp), uint16(LMSW), + /*1312*/ uint16(xArgRM16), + /*1313*/ uint16(xMatch), + /*1314*/ uint16(xSetOp), uint16(INVLPG), + /*1316*/ uint16(xArgM), + /*1317*/ uint16(xMatch), + /*1318*/ uint16(xSetOp), uint16(MONITOR), + /*1320*/ uint16(xMatch), + /*1321*/ uint16(xSetOp), uint16(MWAIT), + /*1323*/ uint16(xMatch), + /*1324*/ uint16(xSetOp), uint16(XGETBV), + /*1326*/ uint16(xMatch), + /*1327*/ uint16(xSetOp), uint16(XSETBV), + /*1329*/ uint16(xMatch), + /*1330*/ uint16(xSetOp), uint16(XEND), + /*1332*/ uint16(xMatch), + /*1333*/ uint16(xSetOp), uint16(XTEST), + /*1335*/ uint16(xMatch), + /*1336*/ uint16(xCondIs64), 0, 1339, + /*1339*/ uint16(xSetOp), uint16(SWAPGS), + /*1341*/ uint16(xMatch), + /*1342*/ uint16(xSetOp), uint16(RDTSCP), + /*1344*/ uint16(xMatch), + /*1345*/ uint16(xCondDataSize), 1349, 1355, 1361, + /*1349*/ uint16(xSetOp), uint16(LAR), + /*1351*/ uint16(xReadSlashR), + /*1352*/ uint16(xArgR16), + /*1353*/ uint16(xArgRM16), + /*1354*/ uint16(xMatch), + /*1355*/ uint16(xSetOp), uint16(LAR), + /*1357*/ uint16(xReadSlashR), + /*1358*/ uint16(xArgR32), + /*1359*/ uint16(xArgR32M16), + /*1360*/ uint16(xMatch), + /*1361*/ uint16(xSetOp), uint16(LAR), + /*1363*/ uint16(xReadSlashR), + /*1364*/ uint16(xArgR64), + /*1365*/ uint16(xArgR64M16), + /*1366*/ uint16(xMatch), + /*1367*/ uint16(xCondDataSize), 1371, 1377, 1383, + /*1371*/ uint16(xSetOp), uint16(LSL), + /*1373*/ uint16(xReadSlashR), + /*1374*/ uint16(xArgR16), + /*1375*/ uint16(xArgRM16), + /*1376*/ uint16(xMatch), + /*1377*/ uint16(xSetOp), uint16(LSL), + /*1379*/ uint16(xReadSlashR), + /*1380*/ uint16(xArgR32), + /*1381*/ uint16(xArgR32M16), + /*1382*/ uint16(xMatch), + /*1383*/ uint16(xSetOp), uint16(LSL), + /*1385*/ uint16(xReadSlashR), + /*1386*/ uint16(xArgR64), + /*1387*/ uint16(xArgR32M16), + /*1388*/ uint16(xMatch), + /*1389*/ uint16(xCondIs64), 0, 1392, + /*1392*/ uint16(xSetOp), uint16(SYSCALL), + /*1394*/ uint16(xMatch), + /*1395*/ uint16(xSetOp), uint16(CLTS), + /*1397*/ uint16(xMatch), + /*1398*/ uint16(xCondIs64), 0, 1401, + /*1401*/ uint16(xSetOp), uint16(SYSRET), + /*1403*/ uint16(xMatch), + /*1404*/ uint16(xSetOp), uint16(INVD), + /*1406*/ uint16(xMatch), + /*1407*/ uint16(xSetOp), uint16(WBINVD), + /*1409*/ uint16(xMatch), + /*1410*/ uint16(xSetOp), uint16(UD2), + /*1412*/ uint16(xMatch), + /*1413*/ uint16(xCondSlashR), + 0, // 0 + 1422, // 1 + 0, // 2 + 0, // 3 + 0, // 4 + 0, // 5 + 0, // 6 + 0, // 7 + /*1422*/ uint16(xSetOp), uint16(PREFETCHW), + /*1424*/ uint16(xArgM8), + /*1425*/ uint16(xMatch), + /*1426*/ uint16(xCondPrefix), 4, + 0xF3, 1454, + 0xF2, 1448, + 0x66, 1442, + 0x0, 1436, + /*1436*/ uint16(xSetOp), uint16(MOVUPS), + /*1438*/ uint16(xReadSlashR), + /*1439*/ uint16(xArgXmm1), + /*1440*/ uint16(xArgXmm2M128), + /*1441*/ uint16(xMatch), + /*1442*/ uint16(xSetOp), uint16(MOVUPD), + /*1444*/ uint16(xReadSlashR), + /*1445*/ uint16(xArgXmm1), + /*1446*/ uint16(xArgXmm2M128), + /*1447*/ uint16(xMatch), + /*1448*/ uint16(xSetOp), uint16(MOVSD_XMM), + /*1450*/ uint16(xReadSlashR), + /*1451*/ uint16(xArgXmm1), + /*1452*/ uint16(xArgXmm2M64), + /*1453*/ uint16(xMatch), + /*1454*/ uint16(xSetOp), uint16(MOVSS), + /*1456*/ uint16(xReadSlashR), + /*1457*/ uint16(xArgXmm1), + /*1458*/ uint16(xArgXmm2M32), + /*1459*/ uint16(xMatch), + /*1460*/ uint16(xCondPrefix), 4, + 0xF3, 1488, + 0xF2, 1482, + 0x66, 1476, + 0x0, 1470, + /*1470*/ uint16(xSetOp), uint16(MOVUPS), + /*1472*/ uint16(xReadSlashR), + /*1473*/ uint16(xArgXmm2M128), + /*1474*/ uint16(xArgXmm1), + /*1475*/ uint16(xMatch), + /*1476*/ uint16(xSetOp), uint16(MOVUPD), + /*1478*/ uint16(xReadSlashR), + /*1479*/ uint16(xArgXmm2M128), + /*1480*/ uint16(xArgXmm), + /*1481*/ uint16(xMatch), + /*1482*/ uint16(xSetOp), uint16(MOVSD_XMM), + /*1484*/ uint16(xReadSlashR), + /*1485*/ uint16(xArgXmm2M64), + /*1486*/ uint16(xArgXmm1), + /*1487*/ uint16(xMatch), + /*1488*/ uint16(xSetOp), uint16(MOVSS), + /*1490*/ uint16(xReadSlashR), + /*1491*/ uint16(xArgXmm2M32), + /*1492*/ uint16(xArgXmm), + /*1493*/ uint16(xMatch), + /*1494*/ uint16(xCondPrefix), 4, + 0xF3, 1531, + 0xF2, 1525, + 0x66, 1519, + 0x0, 1504, + /*1504*/ uint16(xCondIsMem), 1507, 1513, + /*1507*/ uint16(xSetOp), uint16(MOVHLPS), + /*1509*/ uint16(xReadSlashR), + /*1510*/ uint16(xArgXmm1), + /*1511*/ uint16(xArgXmm2), + /*1512*/ uint16(xMatch), + /*1513*/ uint16(xSetOp), uint16(MOVLPS), + /*1515*/ uint16(xReadSlashR), + /*1516*/ uint16(xArgXmm), + /*1517*/ uint16(xArgM64), + /*1518*/ uint16(xMatch), + /*1519*/ uint16(xSetOp), uint16(MOVLPD), + /*1521*/ uint16(xReadSlashR), + /*1522*/ uint16(xArgXmm), + /*1523*/ uint16(xArgXmm2M64), + /*1524*/ uint16(xMatch), + /*1525*/ uint16(xSetOp), uint16(MOVDDUP), + /*1527*/ uint16(xReadSlashR), + /*1528*/ uint16(xArgXmm1), + /*1529*/ uint16(xArgXmm2M64), + /*1530*/ uint16(xMatch), + /*1531*/ uint16(xSetOp), uint16(MOVSLDUP), + /*1533*/ uint16(xReadSlashR), + /*1534*/ uint16(xArgXmm1), + /*1535*/ uint16(xArgXmm2M128), + /*1536*/ uint16(xMatch), + /*1537*/ uint16(xCondPrefix), 2, + 0x66, 1549, + 0x0, 1543, + /*1543*/ uint16(xSetOp), uint16(MOVLPS), + /*1545*/ uint16(xReadSlashR), + /*1546*/ uint16(xArgM64), + /*1547*/ uint16(xArgXmm), + /*1548*/ uint16(xMatch), + /*1549*/ uint16(xSetOp), uint16(MOVLPD), + /*1551*/ uint16(xReadSlashR), + /*1552*/ uint16(xArgXmm2M64), + /*1553*/ uint16(xArgXmm), + /*1554*/ uint16(xMatch), + /*1555*/ uint16(xCondPrefix), 2, + 0x66, 1567, + 0x0, 1561, + /*1561*/ uint16(xSetOp), uint16(UNPCKLPS), + /*1563*/ uint16(xReadSlashR), + /*1564*/ uint16(xArgXmm1), + /*1565*/ uint16(xArgXmm2M128), + /*1566*/ uint16(xMatch), + /*1567*/ uint16(xSetOp), uint16(UNPCKLPD), + /*1569*/ uint16(xReadSlashR), + /*1570*/ uint16(xArgXmm1), + /*1571*/ uint16(xArgXmm2M128), + /*1572*/ uint16(xMatch), + /*1573*/ uint16(xCondPrefix), 2, + 0x66, 1585, + 0x0, 1579, + /*1579*/ uint16(xSetOp), uint16(UNPCKHPS), + /*1581*/ uint16(xReadSlashR), + /*1582*/ uint16(xArgXmm1), + /*1583*/ uint16(xArgXmm2M128), + /*1584*/ uint16(xMatch), + /*1585*/ uint16(xSetOp), uint16(UNPCKHPD), + /*1587*/ uint16(xReadSlashR), + /*1588*/ uint16(xArgXmm1), + /*1589*/ uint16(xArgXmm2M128), + /*1590*/ uint16(xMatch), + /*1591*/ uint16(xCondPrefix), 3, + 0xF3, 1620, + 0x66, 1614, + 0x0, 1599, + /*1599*/ uint16(xCondIsMem), 1602, 1608, + /*1602*/ uint16(xSetOp), uint16(MOVLHPS), + /*1604*/ uint16(xReadSlashR), + /*1605*/ uint16(xArgXmm1), + /*1606*/ uint16(xArgXmm2), + /*1607*/ uint16(xMatch), + /*1608*/ uint16(xSetOp), uint16(MOVHPS), + /*1610*/ uint16(xReadSlashR), + /*1611*/ uint16(xArgXmm), + /*1612*/ uint16(xArgM64), + /*1613*/ uint16(xMatch), + /*1614*/ uint16(xSetOp), uint16(MOVHPD), + /*1616*/ uint16(xReadSlashR), + /*1617*/ uint16(xArgXmm), + /*1618*/ uint16(xArgXmm2M64), + /*1619*/ uint16(xMatch), + /*1620*/ uint16(xSetOp), uint16(MOVSHDUP), + /*1622*/ uint16(xReadSlashR), + /*1623*/ uint16(xArgXmm1), + /*1624*/ uint16(xArgXmm2M128), + /*1625*/ uint16(xMatch), + /*1626*/ uint16(xCondPrefix), 2, + 0x66, 1638, + 0x0, 1632, + /*1632*/ uint16(xSetOp), uint16(MOVHPS), + /*1634*/ uint16(xReadSlashR), + /*1635*/ uint16(xArgM64), + /*1636*/ uint16(xArgXmm), + /*1637*/ uint16(xMatch), + /*1638*/ uint16(xSetOp), uint16(MOVHPD), + /*1640*/ uint16(xReadSlashR), + /*1641*/ uint16(xArgXmm2M64), + /*1642*/ uint16(xArgXmm), + /*1643*/ uint16(xMatch), + /*1644*/ uint16(xCondSlashR), + 1653, // 0 + 1657, // 1 + 1661, // 2 + 1665, // 3 + 0, // 4 + 0, // 5 + 0, // 6 + 0, // 7 + /*1653*/ uint16(xSetOp), uint16(PREFETCHNTA), + /*1655*/ uint16(xArgM8), + /*1656*/ uint16(xMatch), + /*1657*/ uint16(xSetOp), uint16(PREFETCHT0), + /*1659*/ uint16(xArgM8), + /*1660*/ uint16(xMatch), + /*1661*/ uint16(xSetOp), uint16(PREFETCHT1), + /*1663*/ uint16(xArgM8), + /*1664*/ uint16(xMatch), + /*1665*/ uint16(xSetOp), uint16(PREFETCHT2), + /*1667*/ uint16(xArgM8), + /*1668*/ uint16(xMatch), + /*1669*/ uint16(xCondSlashR), + 1678, // 0 + 0, // 1 + 0, // 2 + 0, // 3 + 0, // 4 + 0, // 5 + 0, // 6 + 0, // 7 + /*1678*/ uint16(xCondDataSize), 1682, 1686, 0, + /*1682*/ uint16(xSetOp), uint16(NOP), + /*1684*/ uint16(xArgRM16), + /*1685*/ uint16(xMatch), + /*1686*/ uint16(xSetOp), uint16(NOP), + /*1688*/ uint16(xArgRM32), + /*1689*/ uint16(xMatch), + /*1690*/ uint16(xCondIs64), 1693, 1699, + /*1693*/ uint16(xSetOp), uint16(MOV), + /*1695*/ uint16(xReadSlashR), + /*1696*/ uint16(xArgRmf32), + /*1697*/ uint16(xArgCR0dashCR7), + /*1698*/ uint16(xMatch), + /*1699*/ uint16(xSetOp), uint16(MOV), + /*1701*/ uint16(xReadSlashR), + /*1702*/ uint16(xArgRmf64), + /*1703*/ uint16(xArgCR0dashCR7), + /*1704*/ uint16(xMatch), + /*1705*/ uint16(xCondIs64), 1708, 1714, + /*1708*/ uint16(xSetOp), uint16(MOV), + /*1710*/ uint16(xReadSlashR), + /*1711*/ uint16(xArgRmf32), + /*1712*/ uint16(xArgDR0dashDR7), + /*1713*/ uint16(xMatch), + /*1714*/ uint16(xSetOp), uint16(MOV), + /*1716*/ uint16(xReadSlashR), + /*1717*/ uint16(xArgRmf64), + /*1718*/ uint16(xArgDR0dashDR7), + /*1719*/ uint16(xMatch), + /*1720*/ uint16(xCondIs64), 1723, 1729, + /*1723*/ uint16(xSetOp), uint16(MOV), + /*1725*/ uint16(xReadSlashR), + /*1726*/ uint16(xArgCR0dashCR7), + /*1727*/ uint16(xArgRmf32), + /*1728*/ uint16(xMatch), + /*1729*/ uint16(xSetOp), uint16(MOV), + /*1731*/ uint16(xReadSlashR), + /*1732*/ uint16(xArgCR0dashCR7), + /*1733*/ uint16(xArgRmf64), + /*1734*/ uint16(xMatch), + /*1735*/ uint16(xCondIs64), 1738, 1744, + /*1738*/ uint16(xSetOp), uint16(MOV), + /*1740*/ uint16(xReadSlashR), + /*1741*/ uint16(xArgDR0dashDR7), + /*1742*/ uint16(xArgRmf32), + /*1743*/ uint16(xMatch), + /*1744*/ uint16(xSetOp), uint16(MOV), + /*1746*/ uint16(xReadSlashR), + /*1747*/ uint16(xArgDR0dashDR7), + /*1748*/ uint16(xArgRmf64), + /*1749*/ uint16(xMatch), + /*1750*/ uint16(xCondIs64), 1753, 1759, + /*1753*/ uint16(xSetOp), uint16(MOV), + /*1755*/ uint16(xReadSlashR), + /*1756*/ uint16(xArgRmf32), + /*1757*/ uint16(xArgTR0dashTR7), + /*1758*/ uint16(xMatch), + /*1759*/ uint16(xSetOp), uint16(MOV), + /*1761*/ uint16(xReadSlashR), + /*1762*/ uint16(xArgRmf64), + /*1763*/ uint16(xArgTR0dashTR7), + /*1764*/ uint16(xMatch), + /*1765*/ uint16(xCondIs64), 1768, 1774, + /*1768*/ uint16(xSetOp), uint16(MOV), + /*1770*/ uint16(xReadSlashR), + /*1771*/ uint16(xArgTR0dashTR7), + /*1772*/ uint16(xArgRmf32), + /*1773*/ uint16(xMatch), + /*1774*/ uint16(xSetOp), uint16(MOV), + /*1776*/ uint16(xReadSlashR), + /*1777*/ uint16(xArgTR0dashTR7), + /*1778*/ uint16(xArgRmf64), + /*1779*/ uint16(xMatch), + /*1780*/ uint16(xCondPrefix), 2, + 0x66, 1792, + 0x0, 1786, + /*1786*/ uint16(xSetOp), uint16(MOVAPS), + /*1788*/ uint16(xReadSlashR), + /*1789*/ uint16(xArgXmm1), + /*1790*/ uint16(xArgXmm2M128), + /*1791*/ uint16(xMatch), + /*1792*/ uint16(xSetOp), uint16(MOVAPD), + /*1794*/ uint16(xReadSlashR), + /*1795*/ uint16(xArgXmm1), + /*1796*/ uint16(xArgXmm2M128), + /*1797*/ uint16(xMatch), + /*1798*/ uint16(xCondPrefix), 2, + 0x66, 1810, + 0x0, 1804, + /*1804*/ uint16(xSetOp), uint16(MOVAPS), + /*1806*/ uint16(xReadSlashR), + /*1807*/ uint16(xArgXmm2M128), + /*1808*/ uint16(xArgXmm1), + /*1809*/ uint16(xMatch), + /*1810*/ uint16(xSetOp), uint16(MOVAPD), + /*1812*/ uint16(xReadSlashR), + /*1813*/ uint16(xArgXmm2M128), + /*1814*/ uint16(xArgXmm1), + /*1815*/ uint16(xMatch), + /*1816*/ uint16(xCondIs64), 1819, 1873, + /*1819*/ uint16(xCondPrefix), 4, + 0xF3, 1857, + 0xF2, 1841, + 0x66, 1835, + 0x0, 1829, + /*1829*/ uint16(xSetOp), uint16(CVTPI2PS), + /*1831*/ uint16(xReadSlashR), + /*1832*/ uint16(xArgXmm), + /*1833*/ uint16(xArgMmM64), + /*1834*/ uint16(xMatch), + /*1835*/ uint16(xSetOp), uint16(CVTPI2PD), + /*1837*/ uint16(xReadSlashR), + /*1838*/ uint16(xArgXmm), + /*1839*/ uint16(xArgMmM64), + /*1840*/ uint16(xMatch), + /*1841*/ uint16(xCondDataSize), 1845, 1851, 0, + /*1845*/ uint16(xSetOp), uint16(CVTSI2SD), + /*1847*/ uint16(xReadSlashR), + /*1848*/ uint16(xArgXmm), + /*1849*/ uint16(xArgRM32), + /*1850*/ uint16(xMatch), + /*1851*/ uint16(xSetOp), uint16(CVTSI2SD), + /*1853*/ uint16(xReadSlashR), + /*1854*/ uint16(xArgXmm), + /*1855*/ uint16(xArgRM32), + /*1856*/ uint16(xMatch), + /*1857*/ uint16(xCondDataSize), 1861, 1867, 0, + /*1861*/ uint16(xSetOp), uint16(CVTSI2SS), + /*1863*/ uint16(xReadSlashR), + /*1864*/ uint16(xArgXmm), + /*1865*/ uint16(xArgRM32), + /*1866*/ uint16(xMatch), + /*1867*/ uint16(xSetOp), uint16(CVTSI2SS), + /*1869*/ uint16(xReadSlashR), + /*1870*/ uint16(xArgXmm), + /*1871*/ uint16(xArgRM32), + /*1872*/ uint16(xMatch), + /*1873*/ uint16(xCondPrefix), 4, + 0xF3, 1893, + 0xF2, 1883, + 0x66, 1835, + 0x0, 1829, + /*1883*/ uint16(xCondDataSize), 1845, 1851, 1887, + /*1887*/ uint16(xSetOp), uint16(CVTSI2SD), + /*1889*/ uint16(xReadSlashR), + /*1890*/ uint16(xArgXmm), + /*1891*/ uint16(xArgRM64), + /*1892*/ uint16(xMatch), + /*1893*/ uint16(xCondDataSize), 1861, 1867, 1897, + /*1897*/ uint16(xSetOp), uint16(CVTSI2SS), + /*1899*/ uint16(xReadSlashR), + /*1900*/ uint16(xArgXmm), + /*1901*/ uint16(xArgRM64), + /*1902*/ uint16(xMatch), + /*1903*/ uint16(xCondPrefix), 4, + 0xF3, 1931, + 0xF2, 1925, + 0x66, 1919, + 0x0, 1913, + /*1913*/ uint16(xSetOp), uint16(MOVNTPS), + /*1915*/ uint16(xReadSlashR), + /*1916*/ uint16(xArgM128), + /*1917*/ uint16(xArgXmm), + /*1918*/ uint16(xMatch), + /*1919*/ uint16(xSetOp), uint16(MOVNTPD), + /*1921*/ uint16(xReadSlashR), + /*1922*/ uint16(xArgM128), + /*1923*/ uint16(xArgXmm), + /*1924*/ uint16(xMatch), + /*1925*/ uint16(xSetOp), uint16(MOVNTSD), + /*1927*/ uint16(xReadSlashR), + /*1928*/ uint16(xArgM64), + /*1929*/ uint16(xArgXmm), + /*1930*/ uint16(xMatch), + /*1931*/ uint16(xSetOp), uint16(MOVNTSS), + /*1933*/ uint16(xReadSlashR), + /*1934*/ uint16(xArgM32), + /*1935*/ uint16(xArgXmm), + /*1936*/ uint16(xMatch), + /*1937*/ uint16(xCondIs64), 1940, 1994, + /*1940*/ uint16(xCondPrefix), 4, + 0xF3, 1978, + 0xF2, 1962, + 0x66, 1956, + 0x0, 1950, + /*1950*/ uint16(xSetOp), uint16(CVTTPS2PI), + /*1952*/ uint16(xReadSlashR), + /*1953*/ uint16(xArgMm), + /*1954*/ uint16(xArgXmmM64), + /*1955*/ uint16(xMatch), + /*1956*/ uint16(xSetOp), uint16(CVTTPD2PI), + /*1958*/ uint16(xReadSlashR), + /*1959*/ uint16(xArgMm), + /*1960*/ uint16(xArgXmmM128), + /*1961*/ uint16(xMatch), + /*1962*/ uint16(xCondDataSize), 1966, 1972, 0, + /*1966*/ uint16(xSetOp), uint16(CVTTSD2SI), + /*1968*/ uint16(xReadSlashR), + /*1969*/ uint16(xArgR32), + /*1970*/ uint16(xArgXmmM64), + /*1971*/ uint16(xMatch), + /*1972*/ uint16(xSetOp), uint16(CVTTSD2SI), + /*1974*/ uint16(xReadSlashR), + /*1975*/ uint16(xArgR32), + /*1976*/ uint16(xArgXmmM64), + /*1977*/ uint16(xMatch), + /*1978*/ uint16(xCondDataSize), 1982, 1988, 0, + /*1982*/ uint16(xSetOp), uint16(CVTTSS2SI), + /*1984*/ uint16(xReadSlashR), + /*1985*/ uint16(xArgR32), + /*1986*/ uint16(xArgXmmM32), + /*1987*/ uint16(xMatch), + /*1988*/ uint16(xSetOp), uint16(CVTTSS2SI), + /*1990*/ uint16(xReadSlashR), + /*1991*/ uint16(xArgR32), + /*1992*/ uint16(xArgXmmM32), + /*1993*/ uint16(xMatch), + /*1994*/ uint16(xCondPrefix), 4, + 0xF3, 2014, + 0xF2, 2004, + 0x66, 1956, + 0x0, 1950, + /*2004*/ uint16(xCondDataSize), 1966, 1972, 2008, + /*2008*/ uint16(xSetOp), uint16(CVTTSD2SI), + /*2010*/ uint16(xReadSlashR), + /*2011*/ uint16(xArgR64), + /*2012*/ uint16(xArgXmmM64), + /*2013*/ uint16(xMatch), + /*2014*/ uint16(xCondDataSize), 1982, 1988, 2018, + /*2018*/ uint16(xSetOp), uint16(CVTTSS2SI), + /*2020*/ uint16(xReadSlashR), + /*2021*/ uint16(xArgR64), + /*2022*/ uint16(xArgXmmM32), + /*2023*/ uint16(xMatch), + /*2024*/ uint16(xCondIs64), 2027, 2081, + /*2027*/ uint16(xCondPrefix), 4, + 0xF3, 2065, + 0xF2, 2049, + 0x66, 2043, + 0x0, 2037, + /*2037*/ uint16(xSetOp), uint16(CVTPS2PI), + /*2039*/ uint16(xReadSlashR), + /*2040*/ uint16(xArgMm), + /*2041*/ uint16(xArgXmmM64), + /*2042*/ uint16(xMatch), + /*2043*/ uint16(xSetOp), uint16(CVTPD2PI), + /*2045*/ uint16(xReadSlashR), + /*2046*/ uint16(xArgMm), + /*2047*/ uint16(xArgXmmM128), + /*2048*/ uint16(xMatch), + /*2049*/ uint16(xCondDataSize), 2053, 2059, 0, + /*2053*/ uint16(xSetOp), uint16(CVTSD2SI), + /*2055*/ uint16(xReadSlashR), + /*2056*/ uint16(xArgR32), + /*2057*/ uint16(xArgXmmM64), + /*2058*/ uint16(xMatch), + /*2059*/ uint16(xSetOp), uint16(CVTSD2SI), + /*2061*/ uint16(xReadSlashR), + /*2062*/ uint16(xArgR32), + /*2063*/ uint16(xArgXmmM64), + /*2064*/ uint16(xMatch), + /*2065*/ uint16(xCondDataSize), 2069, 2075, 0, + /*2069*/ uint16(xSetOp), uint16(CVTSS2SI), + /*2071*/ uint16(xReadSlashR), + /*2072*/ uint16(xArgR32), + /*2073*/ uint16(xArgXmmM32), + /*2074*/ uint16(xMatch), + /*2075*/ uint16(xSetOp), uint16(CVTSS2SI), + /*2077*/ uint16(xReadSlashR), + /*2078*/ uint16(xArgR32), + /*2079*/ uint16(xArgXmmM32), + /*2080*/ uint16(xMatch), + /*2081*/ uint16(xCondPrefix), 4, + 0xF3, 2101, + 0xF2, 2091, + 0x66, 2043, + 0x0, 2037, + /*2091*/ uint16(xCondDataSize), 2053, 2059, 2095, + /*2095*/ uint16(xSetOp), uint16(CVTSD2SI), + /*2097*/ uint16(xReadSlashR), + /*2098*/ uint16(xArgR64), + /*2099*/ uint16(xArgXmmM64), + /*2100*/ uint16(xMatch), + /*2101*/ uint16(xCondDataSize), 2069, 2075, 2105, + /*2105*/ uint16(xSetOp), uint16(CVTSS2SI), + /*2107*/ uint16(xReadSlashR), + /*2108*/ uint16(xArgR64), + /*2109*/ uint16(xArgXmmM32), + /*2110*/ uint16(xMatch), + /*2111*/ uint16(xCondPrefix), 2, + 0x66, 2123, + 0x0, 2117, + /*2117*/ uint16(xSetOp), uint16(UCOMISS), + /*2119*/ uint16(xReadSlashR), + /*2120*/ uint16(xArgXmm1), + /*2121*/ uint16(xArgXmm2M32), + /*2122*/ uint16(xMatch), + /*2123*/ uint16(xSetOp), uint16(UCOMISD), + /*2125*/ uint16(xReadSlashR), + /*2126*/ uint16(xArgXmm1), + /*2127*/ uint16(xArgXmm2M64), + /*2128*/ uint16(xMatch), + /*2129*/ uint16(xCondPrefix), 2, + 0x66, 2141, + 0x0, 2135, + /*2135*/ uint16(xSetOp), uint16(COMISS), + /*2137*/ uint16(xReadSlashR), + /*2138*/ uint16(xArgXmm1), + /*2139*/ uint16(xArgXmm2M32), + /*2140*/ uint16(xMatch), + /*2141*/ uint16(xSetOp), uint16(COMISD), + /*2143*/ uint16(xReadSlashR), + /*2144*/ uint16(xArgXmm1), + /*2145*/ uint16(xArgXmm2M64), + /*2146*/ uint16(xMatch), + /*2147*/ uint16(xSetOp), uint16(WRMSR), + /*2149*/ uint16(xMatch), + /*2150*/ uint16(xSetOp), uint16(RDTSC), + /*2152*/ uint16(xMatch), + /*2153*/ uint16(xSetOp), uint16(RDMSR), + /*2155*/ uint16(xMatch), + /*2156*/ uint16(xSetOp), uint16(RDPMC), + /*2158*/ uint16(xMatch), + /*2159*/ uint16(xSetOp), uint16(SYSENTER), + /*2161*/ uint16(xMatch), + /*2162*/ uint16(xCondDataSize), 2166, 2166, 2169, + /*2166*/ uint16(xSetOp), uint16(SYSEXIT), + /*2168*/ uint16(xMatch), + /*2169*/ uint16(xSetOp), uint16(SYSEXIT), + /*2171*/ uint16(xMatch), + /*2172*/ uint16(xCondByte), 54, + 0x00, 2283, + 0x01, 2301, + 0x02, 2319, + 0x03, 2337, + 0x04, 2355, + 0x05, 2373, + 0x06, 2391, + 0x07, 2409, + 0x08, 2427, + 0x09, 2445, + 0x0A, 2463, + 0x0B, 2481, + 0x10, 2499, + 0x14, 2510, + 0x15, 2521, + 0x17, 2532, + 0x1C, 2542, + 0x1D, 2560, + 0x1E, 2578, + 0x20, 2596, + 0x21, 2606, + 0x22, 2616, + 0x23, 2626, + 0x24, 2636, + 0x25, 2646, + 0x28, 2656, + 0x29, 2666, + 0x2A, 2676, + 0x2B, 2686, + 0x30, 2696, + 0x31, 2706, + 0x32, 2716, + 0x33, 2726, + 0x34, 2736, + 0x35, 2746, + 0x37, 2756, + 0x38, 2766, + 0x39, 2776, + 0x3A, 2786, + 0x3B, 2796, + 0x3C, 2806, + 0x3D, 2816, + 0x3E, 2826, + 0x3F, 2836, + 0x40, 2846, + 0x41, 2856, + 0x82, 2866, + 0xDB, 2889, + 0xDC, 2899, + 0xDD, 2909, + 0xDE, 2919, + 0xDF, 2929, + 0xF0, 2939, + 0xF1, 3006, + uint16(xFail), + /*2283*/ uint16(xCondPrefix), 2, + 0x66, 2295, + 0x0, 2289, + /*2289*/ uint16(xSetOp), uint16(PSHUFB), + /*2291*/ uint16(xReadSlashR), + /*2292*/ uint16(xArgMm1), + /*2293*/ uint16(xArgMm2M64), + /*2294*/ uint16(xMatch), + /*2295*/ uint16(xSetOp), uint16(PSHUFB), + /*2297*/ uint16(xReadSlashR), + /*2298*/ uint16(xArgXmm1), + /*2299*/ uint16(xArgXmm2M128), + /*2300*/ uint16(xMatch), + /*2301*/ uint16(xCondPrefix), 2, + 0x66, 2313, + 0x0, 2307, + /*2307*/ uint16(xSetOp), uint16(PHADDW), + /*2309*/ uint16(xReadSlashR), + /*2310*/ uint16(xArgMm1), + /*2311*/ uint16(xArgMm2M64), + /*2312*/ uint16(xMatch), + /*2313*/ uint16(xSetOp), uint16(PHADDW), + /*2315*/ uint16(xReadSlashR), + /*2316*/ uint16(xArgXmm1), + /*2317*/ uint16(xArgXmm2M128), + /*2318*/ uint16(xMatch), + /*2319*/ uint16(xCondPrefix), 2, + 0x66, 2331, + 0x0, 2325, + /*2325*/ uint16(xSetOp), uint16(PHADDD), + /*2327*/ uint16(xReadSlashR), + /*2328*/ uint16(xArgMm1), + /*2329*/ uint16(xArgMm2M64), + /*2330*/ uint16(xMatch), + /*2331*/ uint16(xSetOp), uint16(PHADDD), + /*2333*/ uint16(xReadSlashR), + /*2334*/ uint16(xArgXmm1), + /*2335*/ uint16(xArgXmm2M128), + /*2336*/ uint16(xMatch), + /*2337*/ uint16(xCondPrefix), 2, + 0x66, 2349, + 0x0, 2343, + /*2343*/ uint16(xSetOp), uint16(PHADDSW), + /*2345*/ uint16(xReadSlashR), + /*2346*/ uint16(xArgMm1), + /*2347*/ uint16(xArgMm2M64), + /*2348*/ uint16(xMatch), + /*2349*/ uint16(xSetOp), uint16(PHADDSW), + /*2351*/ uint16(xReadSlashR), + /*2352*/ uint16(xArgXmm1), + /*2353*/ uint16(xArgXmm2M128), + /*2354*/ uint16(xMatch), + /*2355*/ uint16(xCondPrefix), 2, + 0x66, 2367, + 0x0, 2361, + /*2361*/ uint16(xSetOp), uint16(PMADDUBSW), + /*2363*/ uint16(xReadSlashR), + /*2364*/ uint16(xArgMm1), + /*2365*/ uint16(xArgMm2M64), + /*2366*/ uint16(xMatch), + /*2367*/ uint16(xSetOp), uint16(PMADDUBSW), + /*2369*/ uint16(xReadSlashR), + /*2370*/ uint16(xArgXmm1), + /*2371*/ uint16(xArgXmm2M128), + /*2372*/ uint16(xMatch), + /*2373*/ uint16(xCondPrefix), 2, + 0x66, 2385, + 0x0, 2379, + /*2379*/ uint16(xSetOp), uint16(PHSUBW), + /*2381*/ uint16(xReadSlashR), + /*2382*/ uint16(xArgMm1), + /*2383*/ uint16(xArgMm2M64), + /*2384*/ uint16(xMatch), + /*2385*/ uint16(xSetOp), uint16(PHSUBW), + /*2387*/ uint16(xReadSlashR), + /*2388*/ uint16(xArgXmm1), + /*2389*/ uint16(xArgXmm2M128), + /*2390*/ uint16(xMatch), + /*2391*/ uint16(xCondPrefix), 2, + 0x66, 2403, + 0x0, 2397, + /*2397*/ uint16(xSetOp), uint16(PHSUBD), + /*2399*/ uint16(xReadSlashR), + /*2400*/ uint16(xArgMm1), + /*2401*/ uint16(xArgMm2M64), + /*2402*/ uint16(xMatch), + /*2403*/ uint16(xSetOp), uint16(PHSUBD), + /*2405*/ uint16(xReadSlashR), + /*2406*/ uint16(xArgXmm1), + /*2407*/ uint16(xArgXmm2M128), + /*2408*/ uint16(xMatch), + /*2409*/ uint16(xCondPrefix), 2, + 0x66, 2421, + 0x0, 2415, + /*2415*/ uint16(xSetOp), uint16(PHSUBSW), + /*2417*/ uint16(xReadSlashR), + /*2418*/ uint16(xArgMm1), + /*2419*/ uint16(xArgMm2M64), + /*2420*/ uint16(xMatch), + /*2421*/ uint16(xSetOp), uint16(PHSUBSW), + /*2423*/ uint16(xReadSlashR), + /*2424*/ uint16(xArgXmm1), + /*2425*/ uint16(xArgXmm2M128), + /*2426*/ uint16(xMatch), + /*2427*/ uint16(xCondPrefix), 2, + 0x66, 2439, + 0x0, 2433, + /*2433*/ uint16(xSetOp), uint16(PSIGNB), + /*2435*/ uint16(xReadSlashR), + /*2436*/ uint16(xArgMm1), + /*2437*/ uint16(xArgMm2M64), + /*2438*/ uint16(xMatch), + /*2439*/ uint16(xSetOp), uint16(PSIGNB), + /*2441*/ uint16(xReadSlashR), + /*2442*/ uint16(xArgXmm1), + /*2443*/ uint16(xArgXmm2M128), + /*2444*/ uint16(xMatch), + /*2445*/ uint16(xCondPrefix), 2, + 0x66, 2457, + 0x0, 2451, + /*2451*/ uint16(xSetOp), uint16(PSIGNW), + /*2453*/ uint16(xReadSlashR), + /*2454*/ uint16(xArgMm1), + /*2455*/ uint16(xArgMm2M64), + /*2456*/ uint16(xMatch), + /*2457*/ uint16(xSetOp), uint16(PSIGNW), + /*2459*/ uint16(xReadSlashR), + /*2460*/ uint16(xArgXmm1), + /*2461*/ uint16(xArgXmm2M128), + /*2462*/ uint16(xMatch), + /*2463*/ uint16(xCondPrefix), 2, + 0x66, 2475, + 0x0, 2469, + /*2469*/ uint16(xSetOp), uint16(PSIGND), + /*2471*/ uint16(xReadSlashR), + /*2472*/ uint16(xArgMm1), + /*2473*/ uint16(xArgMm2M64), + /*2474*/ uint16(xMatch), + /*2475*/ uint16(xSetOp), uint16(PSIGND), + /*2477*/ uint16(xReadSlashR), + /*2478*/ uint16(xArgXmm1), + /*2479*/ uint16(xArgXmm2M128), + /*2480*/ uint16(xMatch), + /*2481*/ uint16(xCondPrefix), 2, + 0x66, 2493, + 0x0, 2487, + /*2487*/ uint16(xSetOp), uint16(PMULHRSW), + /*2489*/ uint16(xReadSlashR), + /*2490*/ uint16(xArgMm1), + /*2491*/ uint16(xArgMm2M64), + /*2492*/ uint16(xMatch), + /*2493*/ uint16(xSetOp), uint16(PMULHRSW), + /*2495*/ uint16(xReadSlashR), + /*2496*/ uint16(xArgXmm1), + /*2497*/ uint16(xArgXmm2M128), + /*2498*/ uint16(xMatch), + /*2499*/ uint16(xCondPrefix), 1, + 0x66, 2503, + /*2503*/ uint16(xSetOp), uint16(PBLENDVB), + /*2505*/ uint16(xReadSlashR), + /*2506*/ uint16(xArgXmm1), + /*2507*/ uint16(xArgXmm2M128), + /*2508*/ uint16(xArgXMM0), + /*2509*/ uint16(xMatch), + /*2510*/ uint16(xCondPrefix), 1, + 0x66, 2514, + /*2514*/ uint16(xSetOp), uint16(BLENDVPS), + /*2516*/ uint16(xReadSlashR), + /*2517*/ uint16(xArgXmm1), + /*2518*/ uint16(xArgXmm2M128), + /*2519*/ uint16(xArgXMM0), + /*2520*/ uint16(xMatch), + /*2521*/ uint16(xCondPrefix), 1, + 0x66, 2525, + /*2525*/ uint16(xSetOp), uint16(BLENDVPD), + /*2527*/ uint16(xReadSlashR), + /*2528*/ uint16(xArgXmm1), + /*2529*/ uint16(xArgXmm2M128), + /*2530*/ uint16(xArgXMM0), + /*2531*/ uint16(xMatch), + /*2532*/ uint16(xCondPrefix), 1, + 0x66, 2536, + /*2536*/ uint16(xSetOp), uint16(PTEST), + /*2538*/ uint16(xReadSlashR), + /*2539*/ uint16(xArgXmm1), + /*2540*/ uint16(xArgXmm2M128), + /*2541*/ uint16(xMatch), + /*2542*/ uint16(xCondPrefix), 2, + 0x66, 2554, + 0x0, 2548, + /*2548*/ uint16(xSetOp), uint16(PABSB), + /*2550*/ uint16(xReadSlashR), + /*2551*/ uint16(xArgMm1), + /*2552*/ uint16(xArgMm2M64), + /*2553*/ uint16(xMatch), + /*2554*/ uint16(xSetOp), uint16(PABSB), + /*2556*/ uint16(xReadSlashR), + /*2557*/ uint16(xArgXmm1), + /*2558*/ uint16(xArgXmm2M128), + /*2559*/ uint16(xMatch), + /*2560*/ uint16(xCondPrefix), 2, + 0x66, 2572, + 0x0, 2566, + /*2566*/ uint16(xSetOp), uint16(PABSW), + /*2568*/ uint16(xReadSlashR), + /*2569*/ uint16(xArgMm1), + /*2570*/ uint16(xArgMm2M64), + /*2571*/ uint16(xMatch), + /*2572*/ uint16(xSetOp), uint16(PABSW), + /*2574*/ uint16(xReadSlashR), + /*2575*/ uint16(xArgXmm1), + /*2576*/ uint16(xArgXmm2M128), + /*2577*/ uint16(xMatch), + /*2578*/ uint16(xCondPrefix), 2, + 0x66, 2590, + 0x0, 2584, + /*2584*/ uint16(xSetOp), uint16(PABSD), + /*2586*/ uint16(xReadSlashR), + /*2587*/ uint16(xArgMm1), + /*2588*/ uint16(xArgMm2M64), + /*2589*/ uint16(xMatch), + /*2590*/ uint16(xSetOp), uint16(PABSD), + /*2592*/ uint16(xReadSlashR), + /*2593*/ uint16(xArgXmm1), + /*2594*/ uint16(xArgXmm2M128), + /*2595*/ uint16(xMatch), + /*2596*/ uint16(xCondPrefix), 1, + 0x66, 2600, + /*2600*/ uint16(xSetOp), uint16(PMOVSXBW), + /*2602*/ uint16(xReadSlashR), + /*2603*/ uint16(xArgXmm1), + /*2604*/ uint16(xArgXmm2M64), + /*2605*/ uint16(xMatch), + /*2606*/ uint16(xCondPrefix), 1, + 0x66, 2610, + /*2610*/ uint16(xSetOp), uint16(PMOVSXBD), + /*2612*/ uint16(xReadSlashR), + /*2613*/ uint16(xArgXmm1), + /*2614*/ uint16(xArgXmm2M32), + /*2615*/ uint16(xMatch), + /*2616*/ uint16(xCondPrefix), 1, + 0x66, 2620, + /*2620*/ uint16(xSetOp), uint16(PMOVSXBQ), + /*2622*/ uint16(xReadSlashR), + /*2623*/ uint16(xArgXmm1), + /*2624*/ uint16(xArgXmm2M16), + /*2625*/ uint16(xMatch), + /*2626*/ uint16(xCondPrefix), 1, + 0x66, 2630, + /*2630*/ uint16(xSetOp), uint16(PMOVSXWD), + /*2632*/ uint16(xReadSlashR), + /*2633*/ uint16(xArgXmm1), + /*2634*/ uint16(xArgXmm2M64), + /*2635*/ uint16(xMatch), + /*2636*/ uint16(xCondPrefix), 1, + 0x66, 2640, + /*2640*/ uint16(xSetOp), uint16(PMOVSXWQ), + /*2642*/ uint16(xReadSlashR), + /*2643*/ uint16(xArgXmm1), + /*2644*/ uint16(xArgXmm2M32), + /*2645*/ uint16(xMatch), + /*2646*/ uint16(xCondPrefix), 1, + 0x66, 2650, + /*2650*/ uint16(xSetOp), uint16(PMOVSXDQ), + /*2652*/ uint16(xReadSlashR), + /*2653*/ uint16(xArgXmm1), + /*2654*/ uint16(xArgXmm2M64), + /*2655*/ uint16(xMatch), + /*2656*/ uint16(xCondPrefix), 1, + 0x66, 2660, + /*2660*/ uint16(xSetOp), uint16(PMULDQ), + /*2662*/ uint16(xReadSlashR), + /*2663*/ uint16(xArgXmm1), + /*2664*/ uint16(xArgXmm2M128), + /*2665*/ uint16(xMatch), + /*2666*/ uint16(xCondPrefix), 1, + 0x66, 2670, + /*2670*/ uint16(xSetOp), uint16(PCMPEQQ), + /*2672*/ uint16(xReadSlashR), + /*2673*/ uint16(xArgXmm1), + /*2674*/ uint16(xArgXmm2M128), + /*2675*/ uint16(xMatch), + /*2676*/ uint16(xCondPrefix), 1, + 0x66, 2680, + /*2680*/ uint16(xSetOp), uint16(MOVNTDQA), + /*2682*/ uint16(xReadSlashR), + /*2683*/ uint16(xArgXmm1), + /*2684*/ uint16(xArgM128), + /*2685*/ uint16(xMatch), + /*2686*/ uint16(xCondPrefix), 1, + 0x66, 2690, + /*2690*/ uint16(xSetOp), uint16(PACKUSDW), + /*2692*/ uint16(xReadSlashR), + /*2693*/ uint16(xArgXmm1), + /*2694*/ uint16(xArgXmm2M128), + /*2695*/ uint16(xMatch), + /*2696*/ uint16(xCondPrefix), 1, + 0x66, 2700, + /*2700*/ uint16(xSetOp), uint16(PMOVZXBW), + /*2702*/ uint16(xReadSlashR), + /*2703*/ uint16(xArgXmm1), + /*2704*/ uint16(xArgXmm2M64), + /*2705*/ uint16(xMatch), + /*2706*/ uint16(xCondPrefix), 1, + 0x66, 2710, + /*2710*/ uint16(xSetOp), uint16(PMOVZXBD), + /*2712*/ uint16(xReadSlashR), + /*2713*/ uint16(xArgXmm1), + /*2714*/ uint16(xArgXmm2M32), + /*2715*/ uint16(xMatch), + /*2716*/ uint16(xCondPrefix), 1, + 0x66, 2720, + /*2720*/ uint16(xSetOp), uint16(PMOVZXBQ), + /*2722*/ uint16(xReadSlashR), + /*2723*/ uint16(xArgXmm1), + /*2724*/ uint16(xArgXmm2M16), + /*2725*/ uint16(xMatch), + /*2726*/ uint16(xCondPrefix), 1, + 0x66, 2730, + /*2730*/ uint16(xSetOp), uint16(PMOVZXWD), + /*2732*/ uint16(xReadSlashR), + /*2733*/ uint16(xArgXmm1), + /*2734*/ uint16(xArgXmm2M64), + /*2735*/ uint16(xMatch), + /*2736*/ uint16(xCondPrefix), 1, + 0x66, 2740, + /*2740*/ uint16(xSetOp), uint16(PMOVZXWQ), + /*2742*/ uint16(xReadSlashR), + /*2743*/ uint16(xArgXmm1), + /*2744*/ uint16(xArgXmm2M32), + /*2745*/ uint16(xMatch), + /*2746*/ uint16(xCondPrefix), 1, + 0x66, 2750, + /*2750*/ uint16(xSetOp), uint16(PMOVZXDQ), + /*2752*/ uint16(xReadSlashR), + /*2753*/ uint16(xArgXmm1), + /*2754*/ uint16(xArgXmm2M64), + /*2755*/ uint16(xMatch), + /*2756*/ uint16(xCondPrefix), 1, + 0x66, 2760, + /*2760*/ uint16(xSetOp), uint16(PCMPGTQ), + /*2762*/ uint16(xReadSlashR), + /*2763*/ uint16(xArgXmm1), + /*2764*/ uint16(xArgXmm2M128), + /*2765*/ uint16(xMatch), + /*2766*/ uint16(xCondPrefix), 1, + 0x66, 2770, + /*2770*/ uint16(xSetOp), uint16(PMINSB), + /*2772*/ uint16(xReadSlashR), + /*2773*/ uint16(xArgXmm1), + /*2774*/ uint16(xArgXmm2M128), + /*2775*/ uint16(xMatch), + /*2776*/ uint16(xCondPrefix), 1, + 0x66, 2780, + /*2780*/ uint16(xSetOp), uint16(PMINSD), + /*2782*/ uint16(xReadSlashR), + /*2783*/ uint16(xArgXmm1), + /*2784*/ uint16(xArgXmm2M128), + /*2785*/ uint16(xMatch), + /*2786*/ uint16(xCondPrefix), 1, + 0x66, 2790, + /*2790*/ uint16(xSetOp), uint16(PMINUW), + /*2792*/ uint16(xReadSlashR), + /*2793*/ uint16(xArgXmm1), + /*2794*/ uint16(xArgXmm2M128), + /*2795*/ uint16(xMatch), + /*2796*/ uint16(xCondPrefix), 1, + 0x66, 2800, + /*2800*/ uint16(xSetOp), uint16(PMINUD), + /*2802*/ uint16(xReadSlashR), + /*2803*/ uint16(xArgXmm1), + /*2804*/ uint16(xArgXmm2M128), + /*2805*/ uint16(xMatch), + /*2806*/ uint16(xCondPrefix), 1, + 0x66, 2810, + /*2810*/ uint16(xSetOp), uint16(PMAXSB), + /*2812*/ uint16(xReadSlashR), + /*2813*/ uint16(xArgXmm1), + /*2814*/ uint16(xArgXmm2M128), + /*2815*/ uint16(xMatch), + /*2816*/ uint16(xCondPrefix), 1, + 0x66, 2820, + /*2820*/ uint16(xSetOp), uint16(PMAXSD), + /*2822*/ uint16(xReadSlashR), + /*2823*/ uint16(xArgXmm1), + /*2824*/ uint16(xArgXmm2M128), + /*2825*/ uint16(xMatch), + /*2826*/ uint16(xCondPrefix), 1, + 0x66, 2830, + /*2830*/ uint16(xSetOp), uint16(PMAXUW), + /*2832*/ uint16(xReadSlashR), + /*2833*/ uint16(xArgXmm1), + /*2834*/ uint16(xArgXmm2M128), + /*2835*/ uint16(xMatch), + /*2836*/ uint16(xCondPrefix), 1, + 0x66, 2840, + /*2840*/ uint16(xSetOp), uint16(PMAXUD), + /*2842*/ uint16(xReadSlashR), + /*2843*/ uint16(xArgXmm1), + /*2844*/ uint16(xArgXmm2M128), + /*2845*/ uint16(xMatch), + /*2846*/ uint16(xCondPrefix), 1, + 0x66, 2850, + /*2850*/ uint16(xSetOp), uint16(PMULLD), + /*2852*/ uint16(xReadSlashR), + /*2853*/ uint16(xArgXmm1), + /*2854*/ uint16(xArgXmm2M128), + /*2855*/ uint16(xMatch), + /*2856*/ uint16(xCondPrefix), 1, + 0x66, 2860, + /*2860*/ uint16(xSetOp), uint16(PHMINPOSUW), + /*2862*/ uint16(xReadSlashR), + /*2863*/ uint16(xArgXmm1), + /*2864*/ uint16(xArgXmm2M128), + /*2865*/ uint16(xMatch), + /*2866*/ uint16(xCondIs64), 2869, 2879, + /*2869*/ uint16(xCondPrefix), 1, + 0x66, 2873, + /*2873*/ uint16(xSetOp), uint16(INVPCID), + /*2875*/ uint16(xReadSlashR), + /*2876*/ uint16(xArgR32), + /*2877*/ uint16(xArgM128), + /*2878*/ uint16(xMatch), + /*2879*/ uint16(xCondPrefix), 1, + 0x66, 2883, + /*2883*/ uint16(xSetOp), uint16(INVPCID), + /*2885*/ uint16(xReadSlashR), + /*2886*/ uint16(xArgR64), + /*2887*/ uint16(xArgM128), + /*2888*/ uint16(xMatch), + /*2889*/ uint16(xCondPrefix), 1, + 0x66, 2893, + /*2893*/ uint16(xSetOp), uint16(AESIMC), + /*2895*/ uint16(xReadSlashR), + /*2896*/ uint16(xArgXmm1), + /*2897*/ uint16(xArgXmm2M128), + /*2898*/ uint16(xMatch), + /*2899*/ uint16(xCondPrefix), 1, + 0x66, 2903, + /*2903*/ uint16(xSetOp), uint16(AESENC), + /*2905*/ uint16(xReadSlashR), + /*2906*/ uint16(xArgXmm1), + /*2907*/ uint16(xArgXmm2M128), + /*2908*/ uint16(xMatch), + /*2909*/ uint16(xCondPrefix), 1, + 0x66, 2913, + /*2913*/ uint16(xSetOp), uint16(AESENCLAST), + /*2915*/ uint16(xReadSlashR), + /*2916*/ uint16(xArgXmm1), + /*2917*/ uint16(xArgXmm2M128), + /*2918*/ uint16(xMatch), + /*2919*/ uint16(xCondPrefix), 1, + 0x66, 2923, + /*2923*/ uint16(xSetOp), uint16(AESDEC), + /*2925*/ uint16(xReadSlashR), + /*2926*/ uint16(xArgXmm1), + /*2927*/ uint16(xArgXmm2M128), + /*2928*/ uint16(xMatch), + /*2929*/ uint16(xCondPrefix), 1, + 0x66, 2933, + /*2933*/ uint16(xSetOp), uint16(AESDECLAST), + /*2935*/ uint16(xReadSlashR), + /*2936*/ uint16(xArgXmm1), + /*2937*/ uint16(xArgXmm2M128), + /*2938*/ uint16(xMatch), + /*2939*/ uint16(xCondIs64), 2942, 2980, + /*2942*/ uint16(xCondPrefix), 2, + 0xF2, 2964, + 0x0, 2948, + /*2948*/ uint16(xCondDataSize), 2952, 2958, 0, + /*2952*/ uint16(xSetOp), uint16(MOVBE), + /*2954*/ uint16(xReadSlashR), + /*2955*/ uint16(xArgR16), + /*2956*/ uint16(xArgM16), + /*2957*/ uint16(xMatch), + /*2958*/ uint16(xSetOp), uint16(MOVBE), + /*2960*/ uint16(xReadSlashR), + /*2961*/ uint16(xArgR32), + /*2962*/ uint16(xArgM32), + /*2963*/ uint16(xMatch), + /*2964*/ uint16(xCondDataSize), 2968, 2974, 0, + /*2968*/ uint16(xSetOp), uint16(CRC32), + /*2970*/ uint16(xReadSlashR), + /*2971*/ uint16(xArgR32), + /*2972*/ uint16(xArgRM8), + /*2973*/ uint16(xMatch), + /*2974*/ uint16(xSetOp), uint16(CRC32), + /*2976*/ uint16(xReadSlashR), + /*2977*/ uint16(xArgR32), + /*2978*/ uint16(xArgRM8), + /*2979*/ uint16(xMatch), + /*2980*/ uint16(xCondPrefix), 2, + 0xF2, 2996, + 0x0, 2986, + /*2986*/ uint16(xCondDataSize), 2952, 2958, 2990, + /*2990*/ uint16(xSetOp), uint16(MOVBE), + /*2992*/ uint16(xReadSlashR), + /*2993*/ uint16(xArgR64), + /*2994*/ uint16(xArgM64), + /*2995*/ uint16(xMatch), + /*2996*/ uint16(xCondDataSize), 2968, 2974, 3000, + /*3000*/ uint16(xSetOp), uint16(CRC32), + /*3002*/ uint16(xReadSlashR), + /*3003*/ uint16(xArgR64), + /*3004*/ uint16(xArgRM8), + /*3005*/ uint16(xMatch), + /*3006*/ uint16(xCondIs64), 3009, 3047, + /*3009*/ uint16(xCondPrefix), 2, + 0xF2, 3031, + 0x0, 3015, + /*3015*/ uint16(xCondDataSize), 3019, 3025, 0, + /*3019*/ uint16(xSetOp), uint16(MOVBE), + /*3021*/ uint16(xReadSlashR), + /*3022*/ uint16(xArgM16), + /*3023*/ uint16(xArgR16), + /*3024*/ uint16(xMatch), + /*3025*/ uint16(xSetOp), uint16(MOVBE), + /*3027*/ uint16(xReadSlashR), + /*3028*/ uint16(xArgM32), + /*3029*/ uint16(xArgR32), + /*3030*/ uint16(xMatch), + /*3031*/ uint16(xCondDataSize), 3035, 3041, 0, + /*3035*/ uint16(xSetOp), uint16(CRC32), + /*3037*/ uint16(xReadSlashR), + /*3038*/ uint16(xArgR32), + /*3039*/ uint16(xArgRM16), + /*3040*/ uint16(xMatch), + /*3041*/ uint16(xSetOp), uint16(CRC32), + /*3043*/ uint16(xReadSlashR), + /*3044*/ uint16(xArgR32), + /*3045*/ uint16(xArgRM32), + /*3046*/ uint16(xMatch), + /*3047*/ uint16(xCondPrefix), 2, + 0xF2, 3063, + 0x0, 3053, + /*3053*/ uint16(xCondDataSize), 3019, 3025, 3057, + /*3057*/ uint16(xSetOp), uint16(MOVBE), + /*3059*/ uint16(xReadSlashR), + /*3060*/ uint16(xArgM64), + /*3061*/ uint16(xArgR64), + /*3062*/ uint16(xMatch), + /*3063*/ uint16(xCondDataSize), 3035, 3041, 3067, + /*3067*/ uint16(xSetOp), uint16(CRC32), + /*3069*/ uint16(xReadSlashR), + /*3070*/ uint16(xArgR64), + /*3071*/ uint16(xArgRM64), + /*3072*/ uint16(xMatch), + /*3073*/ uint16(xCondByte), 24, + 0x08, 3124, + 0x09, 3136, + 0x0A, 3148, + 0x0B, 3160, + 0x0C, 3172, + 0x0D, 3184, + 0x0E, 3196, + 0x0F, 3208, + 0x14, 3230, + 0x15, 3242, + 0x16, 3254, + 0x17, 3297, + 0x20, 3309, + 0x21, 3321, + 0x22, 3333, + 0x40, 3376, + 0x41, 3388, + 0x42, 3400, + 0x44, 3412, + 0x60, 3424, + 0x61, 3436, + 0x62, 3448, + 0x63, 3460, + 0xDF, 3472, + uint16(xFail), + /*3124*/ uint16(xCondPrefix), 1, + 0x66, 3128, + /*3128*/ uint16(xSetOp), uint16(ROUNDPS), + /*3130*/ uint16(xReadSlashR), + /*3131*/ uint16(xReadIb), + /*3132*/ uint16(xArgXmm1), + /*3133*/ uint16(xArgXmm2M128), + /*3134*/ uint16(xArgImm8u), + /*3135*/ uint16(xMatch), + /*3136*/ uint16(xCondPrefix), 1, + 0x66, 3140, + /*3140*/ uint16(xSetOp), uint16(ROUNDPD), + /*3142*/ uint16(xReadSlashR), + /*3143*/ uint16(xReadIb), + /*3144*/ uint16(xArgXmm1), + /*3145*/ uint16(xArgXmm2M128), + /*3146*/ uint16(xArgImm8u), + /*3147*/ uint16(xMatch), + /*3148*/ uint16(xCondPrefix), 1, + 0x66, 3152, + /*3152*/ uint16(xSetOp), uint16(ROUNDSS), + /*3154*/ uint16(xReadSlashR), + /*3155*/ uint16(xReadIb), + /*3156*/ uint16(xArgXmm1), + /*3157*/ uint16(xArgXmm2M32), + /*3158*/ uint16(xArgImm8u), + /*3159*/ uint16(xMatch), + /*3160*/ uint16(xCondPrefix), 1, + 0x66, 3164, + /*3164*/ uint16(xSetOp), uint16(ROUNDSD), + /*3166*/ uint16(xReadSlashR), + /*3167*/ uint16(xReadIb), + /*3168*/ uint16(xArgXmm1), + /*3169*/ uint16(xArgXmm2M64), + /*3170*/ uint16(xArgImm8u), + /*3171*/ uint16(xMatch), + /*3172*/ uint16(xCondPrefix), 1, + 0x66, 3176, + /*3176*/ uint16(xSetOp), uint16(BLENDPS), + /*3178*/ uint16(xReadSlashR), + /*3179*/ uint16(xReadIb), + /*3180*/ uint16(xArgXmm1), + /*3181*/ uint16(xArgXmm2M128), + /*3182*/ uint16(xArgImm8u), + /*3183*/ uint16(xMatch), + /*3184*/ uint16(xCondPrefix), 1, + 0x66, 3188, + /*3188*/ uint16(xSetOp), uint16(BLENDPD), + /*3190*/ uint16(xReadSlashR), + /*3191*/ uint16(xReadIb), + /*3192*/ uint16(xArgXmm1), + /*3193*/ uint16(xArgXmm2M128), + /*3194*/ uint16(xArgImm8u), + /*3195*/ uint16(xMatch), + /*3196*/ uint16(xCondPrefix), 1, + 0x66, 3200, + /*3200*/ uint16(xSetOp), uint16(PBLENDW), + /*3202*/ uint16(xReadSlashR), + /*3203*/ uint16(xReadIb), + /*3204*/ uint16(xArgXmm1), + /*3205*/ uint16(xArgXmm2M128), + /*3206*/ uint16(xArgImm8u), + /*3207*/ uint16(xMatch), + /*3208*/ uint16(xCondPrefix), 2, + 0x66, 3222, + 0x0, 3214, + /*3214*/ uint16(xSetOp), uint16(PALIGNR), + /*3216*/ uint16(xReadSlashR), + /*3217*/ uint16(xReadIb), + /*3218*/ uint16(xArgMm1), + /*3219*/ uint16(xArgMm2M64), + /*3220*/ uint16(xArgImm8u), + /*3221*/ uint16(xMatch), + /*3222*/ uint16(xSetOp), uint16(PALIGNR), + /*3224*/ uint16(xReadSlashR), + /*3225*/ uint16(xReadIb), + /*3226*/ uint16(xArgXmm1), + /*3227*/ uint16(xArgXmm2M128), + /*3228*/ uint16(xArgImm8u), + /*3229*/ uint16(xMatch), + /*3230*/ uint16(xCondPrefix), 1, + 0x66, 3234, + /*3234*/ uint16(xSetOp), uint16(PEXTRB), + /*3236*/ uint16(xReadSlashR), + /*3237*/ uint16(xReadIb), + /*3238*/ uint16(xArgR32M8), + /*3239*/ uint16(xArgXmm1), + /*3240*/ uint16(xArgImm8u), + /*3241*/ uint16(xMatch), + /*3242*/ uint16(xCondPrefix), 1, + 0x66, 3246, + /*3246*/ uint16(xSetOp), uint16(PEXTRW), + /*3248*/ uint16(xReadSlashR), + /*3249*/ uint16(xReadIb), + /*3250*/ uint16(xArgR32M16), + /*3251*/ uint16(xArgXmm1), + /*3252*/ uint16(xArgImm8u), + /*3253*/ uint16(xMatch), + /*3254*/ uint16(xCondIs64), 3257, 3281, + /*3257*/ uint16(xCondPrefix), 1, + 0x66, 3261, + /*3261*/ uint16(xCondDataSize), 3265, 3273, 0, + /*3265*/ uint16(xSetOp), uint16(PEXTRD), + /*3267*/ uint16(xReadSlashR), + /*3268*/ uint16(xReadIb), + /*3269*/ uint16(xArgRM32), + /*3270*/ uint16(xArgXmm1), + /*3271*/ uint16(xArgImm8u), + /*3272*/ uint16(xMatch), + /*3273*/ uint16(xSetOp), uint16(PEXTRD), + /*3275*/ uint16(xReadSlashR), + /*3276*/ uint16(xReadIb), + /*3277*/ uint16(xArgRM32), + /*3278*/ uint16(xArgXmm1), + /*3279*/ uint16(xArgImm8u), + /*3280*/ uint16(xMatch), + /*3281*/ uint16(xCondPrefix), 1, + 0x66, 3285, + /*3285*/ uint16(xCondDataSize), 3265, 3273, 3289, + /*3289*/ uint16(xSetOp), uint16(PEXTRQ), + /*3291*/ uint16(xReadSlashR), + /*3292*/ uint16(xReadIb), + /*3293*/ uint16(xArgRM64), + /*3294*/ uint16(xArgXmm1), + /*3295*/ uint16(xArgImm8u), + /*3296*/ uint16(xMatch), + /*3297*/ uint16(xCondPrefix), 1, + 0x66, 3301, + /*3301*/ uint16(xSetOp), uint16(EXTRACTPS), + /*3303*/ uint16(xReadSlashR), + /*3304*/ uint16(xReadIb), + /*3305*/ uint16(xArgRM32), + /*3306*/ uint16(xArgXmm1), + /*3307*/ uint16(xArgImm8u), + /*3308*/ uint16(xMatch), + /*3309*/ uint16(xCondPrefix), 1, + 0x66, 3313, + /*3313*/ uint16(xSetOp), uint16(PINSRB), + /*3315*/ uint16(xReadSlashR), + /*3316*/ uint16(xReadIb), + /*3317*/ uint16(xArgXmm1), + /*3318*/ uint16(xArgR32M8), + /*3319*/ uint16(xArgImm8u), + /*3320*/ uint16(xMatch), + /*3321*/ uint16(xCondPrefix), 1, + 0x66, 3325, + /*3325*/ uint16(xSetOp), uint16(INSERTPS), + /*3327*/ uint16(xReadSlashR), + /*3328*/ uint16(xReadIb), + /*3329*/ uint16(xArgXmm1), + /*3330*/ uint16(xArgXmm2M32), + /*3331*/ uint16(xArgImm8u), + /*3332*/ uint16(xMatch), + /*3333*/ uint16(xCondIs64), 3336, 3360, + /*3336*/ uint16(xCondPrefix), 1, + 0x66, 3340, + /*3340*/ uint16(xCondDataSize), 3344, 3352, 0, + /*3344*/ uint16(xSetOp), uint16(PINSRD), + /*3346*/ uint16(xReadSlashR), + /*3347*/ uint16(xReadIb), + /*3348*/ uint16(xArgXmm1), + /*3349*/ uint16(xArgRM32), + /*3350*/ uint16(xArgImm8u), + /*3351*/ uint16(xMatch), + /*3352*/ uint16(xSetOp), uint16(PINSRD), + /*3354*/ uint16(xReadSlashR), + /*3355*/ uint16(xReadIb), + /*3356*/ uint16(xArgXmm1), + /*3357*/ uint16(xArgRM32), + /*3358*/ uint16(xArgImm8u), + /*3359*/ uint16(xMatch), + /*3360*/ uint16(xCondPrefix), 1, + 0x66, 3364, + /*3364*/ uint16(xCondDataSize), 3344, 3352, 3368, + /*3368*/ uint16(xSetOp), uint16(PINSRQ), + /*3370*/ uint16(xReadSlashR), + /*3371*/ uint16(xReadIb), + /*3372*/ uint16(xArgXmm1), + /*3373*/ uint16(xArgRM64), + /*3374*/ uint16(xArgImm8u), + /*3375*/ uint16(xMatch), + /*3376*/ uint16(xCondPrefix), 1, + 0x66, 3380, + /*3380*/ uint16(xSetOp), uint16(DPPS), + /*3382*/ uint16(xReadSlashR), + /*3383*/ uint16(xReadIb), + /*3384*/ uint16(xArgXmm1), + /*3385*/ uint16(xArgXmm2M128), + /*3386*/ uint16(xArgImm8u), + /*3387*/ uint16(xMatch), + /*3388*/ uint16(xCondPrefix), 1, + 0x66, 3392, + /*3392*/ uint16(xSetOp), uint16(DPPD), + /*3394*/ uint16(xReadSlashR), + /*3395*/ uint16(xReadIb), + /*3396*/ uint16(xArgXmm1), + /*3397*/ uint16(xArgXmm2M128), + /*3398*/ uint16(xArgImm8u), + /*3399*/ uint16(xMatch), + /*3400*/ uint16(xCondPrefix), 1, + 0x66, 3404, + /*3404*/ uint16(xSetOp), uint16(MPSADBW), + /*3406*/ uint16(xReadSlashR), + /*3407*/ uint16(xReadIb), + /*3408*/ uint16(xArgXmm1), + /*3409*/ uint16(xArgXmm2M128), + /*3410*/ uint16(xArgImm8u), + /*3411*/ uint16(xMatch), + /*3412*/ uint16(xCondPrefix), 1, + 0x66, 3416, + /*3416*/ uint16(xSetOp), uint16(PCLMULQDQ), + /*3418*/ uint16(xReadSlashR), + /*3419*/ uint16(xReadIb), + /*3420*/ uint16(xArgXmm1), + /*3421*/ uint16(xArgXmm2M128), + /*3422*/ uint16(xArgImm8u), + /*3423*/ uint16(xMatch), + /*3424*/ uint16(xCondPrefix), 1, + 0x66, 3428, + /*3428*/ uint16(xSetOp), uint16(PCMPESTRM), + /*3430*/ uint16(xReadSlashR), + /*3431*/ uint16(xReadIb), + /*3432*/ uint16(xArgXmm1), + /*3433*/ uint16(xArgXmm2M128), + /*3434*/ uint16(xArgImm8u), + /*3435*/ uint16(xMatch), + /*3436*/ uint16(xCondPrefix), 1, + 0x66, 3440, + /*3440*/ uint16(xSetOp), uint16(PCMPESTRI), + /*3442*/ uint16(xReadSlashR), + /*3443*/ uint16(xReadIb), + /*3444*/ uint16(xArgXmm1), + /*3445*/ uint16(xArgXmm2M128), + /*3446*/ uint16(xArgImm8u), + /*3447*/ uint16(xMatch), + /*3448*/ uint16(xCondPrefix), 1, + 0x66, 3452, + /*3452*/ uint16(xSetOp), uint16(PCMPISTRM), + /*3454*/ uint16(xReadSlashR), + /*3455*/ uint16(xReadIb), + /*3456*/ uint16(xArgXmm1), + /*3457*/ uint16(xArgXmm2M128), + /*3458*/ uint16(xArgImm8u), + /*3459*/ uint16(xMatch), + /*3460*/ uint16(xCondPrefix), 1, + 0x66, 3464, + /*3464*/ uint16(xSetOp), uint16(PCMPISTRI), + /*3466*/ uint16(xReadSlashR), + /*3467*/ uint16(xReadIb), + /*3468*/ uint16(xArgXmm1), + /*3469*/ uint16(xArgXmm2M128), + /*3470*/ uint16(xArgImm8u), + /*3471*/ uint16(xMatch), + /*3472*/ uint16(xCondPrefix), 1, + 0x66, 3476, + /*3476*/ uint16(xSetOp), uint16(AESKEYGENASSIST), + /*3478*/ uint16(xReadSlashR), + /*3479*/ uint16(xReadIb), + /*3480*/ uint16(xArgXmm1), + /*3481*/ uint16(xArgXmm2M128), + /*3482*/ uint16(xArgImm8u), + /*3483*/ uint16(xMatch), + /*3484*/ uint16(xCondIs64), 3487, 3503, + /*3487*/ uint16(xCondDataSize), 3491, 3497, 0, + /*3491*/ uint16(xSetOp), uint16(CMOVO), + /*3493*/ uint16(xReadSlashR), + /*3494*/ uint16(xArgR16), + /*3495*/ uint16(xArgRM16), + /*3496*/ uint16(xMatch), + /*3497*/ uint16(xSetOp), uint16(CMOVO), + /*3499*/ uint16(xReadSlashR), + /*3500*/ uint16(xArgR32), + /*3501*/ uint16(xArgRM32), + /*3502*/ uint16(xMatch), + /*3503*/ uint16(xCondDataSize), 3491, 3497, 3507, + /*3507*/ uint16(xSetOp), uint16(CMOVO), + /*3509*/ uint16(xReadSlashR), + /*3510*/ uint16(xArgR64), + /*3511*/ uint16(xArgRM64), + /*3512*/ uint16(xMatch), + /*3513*/ uint16(xCondIs64), 3516, 3532, + /*3516*/ uint16(xCondDataSize), 3520, 3526, 0, + /*3520*/ uint16(xSetOp), uint16(CMOVNO), + /*3522*/ uint16(xReadSlashR), + /*3523*/ uint16(xArgR16), + /*3524*/ uint16(xArgRM16), + /*3525*/ uint16(xMatch), + /*3526*/ uint16(xSetOp), uint16(CMOVNO), + /*3528*/ uint16(xReadSlashR), + /*3529*/ uint16(xArgR32), + /*3530*/ uint16(xArgRM32), + /*3531*/ uint16(xMatch), + /*3532*/ uint16(xCondDataSize), 3520, 3526, 3536, + /*3536*/ uint16(xSetOp), uint16(CMOVNO), + /*3538*/ uint16(xReadSlashR), + /*3539*/ uint16(xArgR64), + /*3540*/ uint16(xArgRM64), + /*3541*/ uint16(xMatch), + /*3542*/ uint16(xCondIs64), 3545, 3561, + /*3545*/ uint16(xCondDataSize), 3549, 3555, 0, + /*3549*/ uint16(xSetOp), uint16(CMOVB), + /*3551*/ uint16(xReadSlashR), + /*3552*/ uint16(xArgR16), + /*3553*/ uint16(xArgRM16), + /*3554*/ uint16(xMatch), + /*3555*/ uint16(xSetOp), uint16(CMOVB), + /*3557*/ uint16(xReadSlashR), + /*3558*/ uint16(xArgR32), + /*3559*/ uint16(xArgRM32), + /*3560*/ uint16(xMatch), + /*3561*/ uint16(xCondDataSize), 3549, 3555, 3565, + /*3565*/ uint16(xSetOp), uint16(CMOVB), + /*3567*/ uint16(xReadSlashR), + /*3568*/ uint16(xArgR64), + /*3569*/ uint16(xArgRM64), + /*3570*/ uint16(xMatch), + /*3571*/ uint16(xCondIs64), 3574, 3590, + /*3574*/ uint16(xCondDataSize), 3578, 3584, 0, + /*3578*/ uint16(xSetOp), uint16(CMOVAE), + /*3580*/ uint16(xReadSlashR), + /*3581*/ uint16(xArgR16), + /*3582*/ uint16(xArgRM16), + /*3583*/ uint16(xMatch), + /*3584*/ uint16(xSetOp), uint16(CMOVAE), + /*3586*/ uint16(xReadSlashR), + /*3587*/ uint16(xArgR32), + /*3588*/ uint16(xArgRM32), + /*3589*/ uint16(xMatch), + /*3590*/ uint16(xCondDataSize), 3578, 3584, 3594, + /*3594*/ uint16(xSetOp), uint16(CMOVAE), + /*3596*/ uint16(xReadSlashR), + /*3597*/ uint16(xArgR64), + /*3598*/ uint16(xArgRM64), + /*3599*/ uint16(xMatch), + /*3600*/ uint16(xCondIs64), 3603, 3619, + /*3603*/ uint16(xCondDataSize), 3607, 3613, 0, + /*3607*/ uint16(xSetOp), uint16(CMOVE), + /*3609*/ uint16(xReadSlashR), + /*3610*/ uint16(xArgR16), + /*3611*/ uint16(xArgRM16), + /*3612*/ uint16(xMatch), + /*3613*/ uint16(xSetOp), uint16(CMOVE), + /*3615*/ uint16(xReadSlashR), + /*3616*/ uint16(xArgR32), + /*3617*/ uint16(xArgRM32), + /*3618*/ uint16(xMatch), + /*3619*/ uint16(xCondDataSize), 3607, 3613, 3623, + /*3623*/ uint16(xSetOp), uint16(CMOVE), + /*3625*/ uint16(xReadSlashR), + /*3626*/ uint16(xArgR64), + /*3627*/ uint16(xArgRM64), + /*3628*/ uint16(xMatch), + /*3629*/ uint16(xCondIs64), 3632, 3648, + /*3632*/ uint16(xCondDataSize), 3636, 3642, 0, + /*3636*/ uint16(xSetOp), uint16(CMOVNE), + /*3638*/ uint16(xReadSlashR), + /*3639*/ uint16(xArgR16), + /*3640*/ uint16(xArgRM16), + /*3641*/ uint16(xMatch), + /*3642*/ uint16(xSetOp), uint16(CMOVNE), + /*3644*/ uint16(xReadSlashR), + /*3645*/ uint16(xArgR32), + /*3646*/ uint16(xArgRM32), + /*3647*/ uint16(xMatch), + /*3648*/ uint16(xCondDataSize), 3636, 3642, 3652, + /*3652*/ uint16(xSetOp), uint16(CMOVNE), + /*3654*/ uint16(xReadSlashR), + /*3655*/ uint16(xArgR64), + /*3656*/ uint16(xArgRM64), + /*3657*/ uint16(xMatch), + /*3658*/ uint16(xCondIs64), 3661, 3677, + /*3661*/ uint16(xCondDataSize), 3665, 3671, 0, + /*3665*/ uint16(xSetOp), uint16(CMOVBE), + /*3667*/ uint16(xReadSlashR), + /*3668*/ uint16(xArgR16), + /*3669*/ uint16(xArgRM16), + /*3670*/ uint16(xMatch), + /*3671*/ uint16(xSetOp), uint16(CMOVBE), + /*3673*/ uint16(xReadSlashR), + /*3674*/ uint16(xArgR32), + /*3675*/ uint16(xArgRM32), + /*3676*/ uint16(xMatch), + /*3677*/ uint16(xCondDataSize), 3665, 3671, 3681, + /*3681*/ uint16(xSetOp), uint16(CMOVBE), + /*3683*/ uint16(xReadSlashR), + /*3684*/ uint16(xArgR64), + /*3685*/ uint16(xArgRM64), + /*3686*/ uint16(xMatch), + /*3687*/ uint16(xCondIs64), 3690, 3706, + /*3690*/ uint16(xCondDataSize), 3694, 3700, 0, + /*3694*/ uint16(xSetOp), uint16(CMOVA), + /*3696*/ uint16(xReadSlashR), + /*3697*/ uint16(xArgR16), + /*3698*/ uint16(xArgRM16), + /*3699*/ uint16(xMatch), + /*3700*/ uint16(xSetOp), uint16(CMOVA), + /*3702*/ uint16(xReadSlashR), + /*3703*/ uint16(xArgR32), + /*3704*/ uint16(xArgRM32), + /*3705*/ uint16(xMatch), + /*3706*/ uint16(xCondDataSize), 3694, 3700, 3710, + /*3710*/ uint16(xSetOp), uint16(CMOVA), + /*3712*/ uint16(xReadSlashR), + /*3713*/ uint16(xArgR64), + /*3714*/ uint16(xArgRM64), + /*3715*/ uint16(xMatch), + /*3716*/ uint16(xCondIs64), 3719, 3735, + /*3719*/ uint16(xCondDataSize), 3723, 3729, 0, + /*3723*/ uint16(xSetOp), uint16(CMOVS), + /*3725*/ uint16(xReadSlashR), + /*3726*/ uint16(xArgR16), + /*3727*/ uint16(xArgRM16), + /*3728*/ uint16(xMatch), + /*3729*/ uint16(xSetOp), uint16(CMOVS), + /*3731*/ uint16(xReadSlashR), + /*3732*/ uint16(xArgR32), + /*3733*/ uint16(xArgRM32), + /*3734*/ uint16(xMatch), + /*3735*/ uint16(xCondDataSize), 3723, 3729, 3739, + /*3739*/ uint16(xSetOp), uint16(CMOVS), + /*3741*/ uint16(xReadSlashR), + /*3742*/ uint16(xArgR64), + /*3743*/ uint16(xArgRM64), + /*3744*/ uint16(xMatch), + /*3745*/ uint16(xCondIs64), 3748, 3764, + /*3748*/ uint16(xCondDataSize), 3752, 3758, 0, + /*3752*/ uint16(xSetOp), uint16(CMOVNS), + /*3754*/ uint16(xReadSlashR), + /*3755*/ uint16(xArgR16), + /*3756*/ uint16(xArgRM16), + /*3757*/ uint16(xMatch), + /*3758*/ uint16(xSetOp), uint16(CMOVNS), + /*3760*/ uint16(xReadSlashR), + /*3761*/ uint16(xArgR32), + /*3762*/ uint16(xArgRM32), + /*3763*/ uint16(xMatch), + /*3764*/ uint16(xCondDataSize), 3752, 3758, 3768, + /*3768*/ uint16(xSetOp), uint16(CMOVNS), + /*3770*/ uint16(xReadSlashR), + /*3771*/ uint16(xArgR64), + /*3772*/ uint16(xArgRM64), + /*3773*/ uint16(xMatch), + /*3774*/ uint16(xCondIs64), 3777, 3793, + /*3777*/ uint16(xCondDataSize), 3781, 3787, 0, + /*3781*/ uint16(xSetOp), uint16(CMOVP), + /*3783*/ uint16(xReadSlashR), + /*3784*/ uint16(xArgR16), + /*3785*/ uint16(xArgRM16), + /*3786*/ uint16(xMatch), + /*3787*/ uint16(xSetOp), uint16(CMOVP), + /*3789*/ uint16(xReadSlashR), + /*3790*/ uint16(xArgR32), + /*3791*/ uint16(xArgRM32), + /*3792*/ uint16(xMatch), + /*3793*/ uint16(xCondDataSize), 3781, 3787, 3797, + /*3797*/ uint16(xSetOp), uint16(CMOVP), + /*3799*/ uint16(xReadSlashR), + /*3800*/ uint16(xArgR64), + /*3801*/ uint16(xArgRM64), + /*3802*/ uint16(xMatch), + /*3803*/ uint16(xCondIs64), 3806, 3822, + /*3806*/ uint16(xCondDataSize), 3810, 3816, 0, + /*3810*/ uint16(xSetOp), uint16(CMOVNP), + /*3812*/ uint16(xReadSlashR), + /*3813*/ uint16(xArgR16), + /*3814*/ uint16(xArgRM16), + /*3815*/ uint16(xMatch), + /*3816*/ uint16(xSetOp), uint16(CMOVNP), + /*3818*/ uint16(xReadSlashR), + /*3819*/ uint16(xArgR32), + /*3820*/ uint16(xArgRM32), + /*3821*/ uint16(xMatch), + /*3822*/ uint16(xCondDataSize), 3810, 3816, 3826, + /*3826*/ uint16(xSetOp), uint16(CMOVNP), + /*3828*/ uint16(xReadSlashR), + /*3829*/ uint16(xArgR64), + /*3830*/ uint16(xArgRM64), + /*3831*/ uint16(xMatch), + /*3832*/ uint16(xCondIs64), 3835, 3851, + /*3835*/ uint16(xCondDataSize), 3839, 3845, 0, + /*3839*/ uint16(xSetOp), uint16(CMOVL), + /*3841*/ uint16(xReadSlashR), + /*3842*/ uint16(xArgR16), + /*3843*/ uint16(xArgRM16), + /*3844*/ uint16(xMatch), + /*3845*/ uint16(xSetOp), uint16(CMOVL), + /*3847*/ uint16(xReadSlashR), + /*3848*/ uint16(xArgR32), + /*3849*/ uint16(xArgRM32), + /*3850*/ uint16(xMatch), + /*3851*/ uint16(xCondDataSize), 3839, 3845, 3855, + /*3855*/ uint16(xSetOp), uint16(CMOVL), + /*3857*/ uint16(xReadSlashR), + /*3858*/ uint16(xArgR64), + /*3859*/ uint16(xArgRM64), + /*3860*/ uint16(xMatch), + /*3861*/ uint16(xCondIs64), 3864, 3880, + /*3864*/ uint16(xCondDataSize), 3868, 3874, 0, + /*3868*/ uint16(xSetOp), uint16(CMOVGE), + /*3870*/ uint16(xReadSlashR), + /*3871*/ uint16(xArgR16), + /*3872*/ uint16(xArgRM16), + /*3873*/ uint16(xMatch), + /*3874*/ uint16(xSetOp), uint16(CMOVGE), + /*3876*/ uint16(xReadSlashR), + /*3877*/ uint16(xArgR32), + /*3878*/ uint16(xArgRM32), + /*3879*/ uint16(xMatch), + /*3880*/ uint16(xCondDataSize), 3868, 3874, 3884, + /*3884*/ uint16(xSetOp), uint16(CMOVGE), + /*3886*/ uint16(xReadSlashR), + /*3887*/ uint16(xArgR64), + /*3888*/ uint16(xArgRM64), + /*3889*/ uint16(xMatch), + /*3890*/ uint16(xCondIs64), 3893, 3909, + /*3893*/ uint16(xCondDataSize), 3897, 3903, 0, + /*3897*/ uint16(xSetOp), uint16(CMOVLE), + /*3899*/ uint16(xReadSlashR), + /*3900*/ uint16(xArgR16), + /*3901*/ uint16(xArgRM16), + /*3902*/ uint16(xMatch), + /*3903*/ uint16(xSetOp), uint16(CMOVLE), + /*3905*/ uint16(xReadSlashR), + /*3906*/ uint16(xArgR32), + /*3907*/ uint16(xArgRM32), + /*3908*/ uint16(xMatch), + /*3909*/ uint16(xCondDataSize), 3897, 3903, 3913, + /*3913*/ uint16(xSetOp), uint16(CMOVLE), + /*3915*/ uint16(xReadSlashR), + /*3916*/ uint16(xArgR64), + /*3917*/ uint16(xArgRM64), + /*3918*/ uint16(xMatch), + /*3919*/ uint16(xCondIs64), 3922, 3938, + /*3922*/ uint16(xCondDataSize), 3926, 3932, 0, + /*3926*/ uint16(xSetOp), uint16(CMOVG), + /*3928*/ uint16(xReadSlashR), + /*3929*/ uint16(xArgR16), + /*3930*/ uint16(xArgRM16), + /*3931*/ uint16(xMatch), + /*3932*/ uint16(xSetOp), uint16(CMOVG), + /*3934*/ uint16(xReadSlashR), + /*3935*/ uint16(xArgR32), + /*3936*/ uint16(xArgRM32), + /*3937*/ uint16(xMatch), + /*3938*/ uint16(xCondDataSize), 3926, 3932, 3942, + /*3942*/ uint16(xSetOp), uint16(CMOVG), + /*3944*/ uint16(xReadSlashR), + /*3945*/ uint16(xArgR64), + /*3946*/ uint16(xArgRM64), + /*3947*/ uint16(xMatch), + /*3948*/ uint16(xCondPrefix), 2, + 0x66, 3960, + 0x0, 3954, + /*3954*/ uint16(xSetOp), uint16(MOVMSKPS), + /*3956*/ uint16(xReadSlashR), + /*3957*/ uint16(xArgR32), + /*3958*/ uint16(xArgXmm2), + /*3959*/ uint16(xMatch), + /*3960*/ uint16(xSetOp), uint16(MOVMSKPD), + /*3962*/ uint16(xReadSlashR), + /*3963*/ uint16(xArgR32), + /*3964*/ uint16(xArgXmm2), + /*3965*/ uint16(xMatch), + /*3966*/ uint16(xCondPrefix), 4, + 0xF3, 3994, + 0xF2, 3988, + 0x66, 3982, + 0x0, 3976, + /*3976*/ uint16(xSetOp), uint16(SQRTPS), + /*3978*/ uint16(xReadSlashR), + /*3979*/ uint16(xArgXmm1), + /*3980*/ uint16(xArgXmm2M128), + /*3981*/ uint16(xMatch), + /*3982*/ uint16(xSetOp), uint16(SQRTPD), + /*3984*/ uint16(xReadSlashR), + /*3985*/ uint16(xArgXmm1), + /*3986*/ uint16(xArgXmm2M128), + /*3987*/ uint16(xMatch), + /*3988*/ uint16(xSetOp), uint16(SQRTSD), + /*3990*/ uint16(xReadSlashR), + /*3991*/ uint16(xArgXmm1), + /*3992*/ uint16(xArgXmm2M64), + /*3993*/ uint16(xMatch), + /*3994*/ uint16(xSetOp), uint16(SQRTSS), + /*3996*/ uint16(xReadSlashR), + /*3997*/ uint16(xArgXmm1), + /*3998*/ uint16(xArgXmm2M32), + /*3999*/ uint16(xMatch), + /*4000*/ uint16(xCondPrefix), 2, + 0xF3, 4012, + 0x0, 4006, + /*4006*/ uint16(xSetOp), uint16(RSQRTPS), + /*4008*/ uint16(xReadSlashR), + /*4009*/ uint16(xArgXmm1), + /*4010*/ uint16(xArgXmm2M128), + /*4011*/ uint16(xMatch), + /*4012*/ uint16(xSetOp), uint16(RSQRTSS), + /*4014*/ uint16(xReadSlashR), + /*4015*/ uint16(xArgXmm1), + /*4016*/ uint16(xArgXmm2M32), + /*4017*/ uint16(xMatch), + /*4018*/ uint16(xCondPrefix), 2, + 0xF3, 4030, + 0x0, 4024, + /*4024*/ uint16(xSetOp), uint16(RCPPS), + /*4026*/ uint16(xReadSlashR), + /*4027*/ uint16(xArgXmm1), + /*4028*/ uint16(xArgXmm2M128), + /*4029*/ uint16(xMatch), + /*4030*/ uint16(xSetOp), uint16(RCPSS), + /*4032*/ uint16(xReadSlashR), + /*4033*/ uint16(xArgXmm1), + /*4034*/ uint16(xArgXmm2M32), + /*4035*/ uint16(xMatch), + /*4036*/ uint16(xCondPrefix), 2, + 0x66, 4048, + 0x0, 4042, + /*4042*/ uint16(xSetOp), uint16(ANDPS), + /*4044*/ uint16(xReadSlashR), + /*4045*/ uint16(xArgXmm1), + /*4046*/ uint16(xArgXmm2M128), + /*4047*/ uint16(xMatch), + /*4048*/ uint16(xSetOp), uint16(ANDPD), + /*4050*/ uint16(xReadSlashR), + /*4051*/ uint16(xArgXmm1), + /*4052*/ uint16(xArgXmm2M128), + /*4053*/ uint16(xMatch), + /*4054*/ uint16(xCondPrefix), 2, + 0x66, 4066, + 0x0, 4060, + /*4060*/ uint16(xSetOp), uint16(ANDNPS), + /*4062*/ uint16(xReadSlashR), + /*4063*/ uint16(xArgXmm1), + /*4064*/ uint16(xArgXmm2M128), + /*4065*/ uint16(xMatch), + /*4066*/ uint16(xSetOp), uint16(ANDNPD), + /*4068*/ uint16(xReadSlashR), + /*4069*/ uint16(xArgXmm1), + /*4070*/ uint16(xArgXmm2M128), + /*4071*/ uint16(xMatch), + /*4072*/ uint16(xCondPrefix), 2, + 0x66, 4084, + 0x0, 4078, + /*4078*/ uint16(xSetOp), uint16(ORPS), + /*4080*/ uint16(xReadSlashR), + /*4081*/ uint16(xArgXmm1), + /*4082*/ uint16(xArgXmm2M128), + /*4083*/ uint16(xMatch), + /*4084*/ uint16(xSetOp), uint16(ORPD), + /*4086*/ uint16(xReadSlashR), + /*4087*/ uint16(xArgXmm1), + /*4088*/ uint16(xArgXmm2M128), + /*4089*/ uint16(xMatch), + /*4090*/ uint16(xCondPrefix), 2, + 0x66, 4102, + 0x0, 4096, + /*4096*/ uint16(xSetOp), uint16(XORPS), + /*4098*/ uint16(xReadSlashR), + /*4099*/ uint16(xArgXmm1), + /*4100*/ uint16(xArgXmm2M128), + /*4101*/ uint16(xMatch), + /*4102*/ uint16(xSetOp), uint16(XORPD), + /*4104*/ uint16(xReadSlashR), + /*4105*/ uint16(xArgXmm1), + /*4106*/ uint16(xArgXmm2M128), + /*4107*/ uint16(xMatch), + /*4108*/ uint16(xCondPrefix), 4, + 0xF3, 4136, + 0xF2, 4130, + 0x66, 4124, + 0x0, 4118, + /*4118*/ uint16(xSetOp), uint16(ADDPS), + /*4120*/ uint16(xReadSlashR), + /*4121*/ uint16(xArgXmm1), + /*4122*/ uint16(xArgXmm2M128), + /*4123*/ uint16(xMatch), + /*4124*/ uint16(xSetOp), uint16(ADDPD), + /*4126*/ uint16(xReadSlashR), + /*4127*/ uint16(xArgXmm1), + /*4128*/ uint16(xArgXmm2M128), + /*4129*/ uint16(xMatch), + /*4130*/ uint16(xSetOp), uint16(ADDSD), + /*4132*/ uint16(xReadSlashR), + /*4133*/ uint16(xArgXmm1), + /*4134*/ uint16(xArgXmm2M64), + /*4135*/ uint16(xMatch), + /*4136*/ uint16(xSetOp), uint16(ADDSS), + /*4138*/ uint16(xReadSlashR), + /*4139*/ uint16(xArgXmm1), + /*4140*/ uint16(xArgXmm2M32), + /*4141*/ uint16(xMatch), + /*4142*/ uint16(xCondPrefix), 4, + 0xF3, 4170, + 0xF2, 4164, + 0x66, 4158, + 0x0, 4152, + /*4152*/ uint16(xSetOp), uint16(MULPS), + /*4154*/ uint16(xReadSlashR), + /*4155*/ uint16(xArgXmm1), + /*4156*/ uint16(xArgXmm2M128), + /*4157*/ uint16(xMatch), + /*4158*/ uint16(xSetOp), uint16(MULPD), + /*4160*/ uint16(xReadSlashR), + /*4161*/ uint16(xArgXmm1), + /*4162*/ uint16(xArgXmm2M128), + /*4163*/ uint16(xMatch), + /*4164*/ uint16(xSetOp), uint16(MULSD), + /*4166*/ uint16(xReadSlashR), + /*4167*/ uint16(xArgXmm1), + /*4168*/ uint16(xArgXmm2M64), + /*4169*/ uint16(xMatch), + /*4170*/ uint16(xSetOp), uint16(MULSS), + /*4172*/ uint16(xReadSlashR), + /*4173*/ uint16(xArgXmm1), + /*4174*/ uint16(xArgXmm2M32), + /*4175*/ uint16(xMatch), + /*4176*/ uint16(xCondPrefix), 4, + 0xF3, 4204, + 0xF2, 4198, + 0x66, 4192, + 0x0, 4186, + /*4186*/ uint16(xSetOp), uint16(CVTPS2PD), + /*4188*/ uint16(xReadSlashR), + /*4189*/ uint16(xArgXmm1), + /*4190*/ uint16(xArgXmm2M64), + /*4191*/ uint16(xMatch), + /*4192*/ uint16(xSetOp), uint16(CVTPD2PS), + /*4194*/ uint16(xReadSlashR), + /*4195*/ uint16(xArgXmm1), + /*4196*/ uint16(xArgXmm2M128), + /*4197*/ uint16(xMatch), + /*4198*/ uint16(xSetOp), uint16(CVTSD2SS), + /*4200*/ uint16(xReadSlashR), + /*4201*/ uint16(xArgXmm1), + /*4202*/ uint16(xArgXmm2M64), + /*4203*/ uint16(xMatch), + /*4204*/ uint16(xSetOp), uint16(CVTSS2SD), + /*4206*/ uint16(xReadSlashR), + /*4207*/ uint16(xArgXmm1), + /*4208*/ uint16(xArgXmm2M32), + /*4209*/ uint16(xMatch), + /*4210*/ uint16(xCondPrefix), 3, + 0xF3, 4230, + 0x66, 4224, + 0x0, 4218, + /*4218*/ uint16(xSetOp), uint16(CVTDQ2PS), + /*4220*/ uint16(xReadSlashR), + /*4221*/ uint16(xArgXmm1), + /*4222*/ uint16(xArgXmm2M128), + /*4223*/ uint16(xMatch), + /*4224*/ uint16(xSetOp), uint16(CVTPS2DQ), + /*4226*/ uint16(xReadSlashR), + /*4227*/ uint16(xArgXmm1), + /*4228*/ uint16(xArgXmm2M128), + /*4229*/ uint16(xMatch), + /*4230*/ uint16(xSetOp), uint16(CVTTPS2DQ), + /*4232*/ uint16(xReadSlashR), + /*4233*/ uint16(xArgXmm1), + /*4234*/ uint16(xArgXmm2M128), + /*4235*/ uint16(xMatch), + /*4236*/ uint16(xCondPrefix), 4, + 0xF3, 4264, + 0xF2, 4258, + 0x66, 4252, + 0x0, 4246, + /*4246*/ uint16(xSetOp), uint16(SUBPS), + /*4248*/ uint16(xReadSlashR), + /*4249*/ uint16(xArgXmm1), + /*4250*/ uint16(xArgXmm2M128), + /*4251*/ uint16(xMatch), + /*4252*/ uint16(xSetOp), uint16(SUBPD), + /*4254*/ uint16(xReadSlashR), + /*4255*/ uint16(xArgXmm1), + /*4256*/ uint16(xArgXmm2M128), + /*4257*/ uint16(xMatch), + /*4258*/ uint16(xSetOp), uint16(SUBSD), + /*4260*/ uint16(xReadSlashR), + /*4261*/ uint16(xArgXmm1), + /*4262*/ uint16(xArgXmm2M64), + /*4263*/ uint16(xMatch), + /*4264*/ uint16(xSetOp), uint16(SUBSS), + /*4266*/ uint16(xReadSlashR), + /*4267*/ uint16(xArgXmm1), + /*4268*/ uint16(xArgXmm2M32), + /*4269*/ uint16(xMatch), + /*4270*/ uint16(xCondPrefix), 4, + 0xF3, 4298, + 0xF2, 4292, + 0x66, 4286, + 0x0, 4280, + /*4280*/ uint16(xSetOp), uint16(MINPS), + /*4282*/ uint16(xReadSlashR), + /*4283*/ uint16(xArgXmm1), + /*4284*/ uint16(xArgXmm2M128), + /*4285*/ uint16(xMatch), + /*4286*/ uint16(xSetOp), uint16(MINPD), + /*4288*/ uint16(xReadSlashR), + /*4289*/ uint16(xArgXmm1), + /*4290*/ uint16(xArgXmm2M128), + /*4291*/ uint16(xMatch), + /*4292*/ uint16(xSetOp), uint16(MINSD), + /*4294*/ uint16(xReadSlashR), + /*4295*/ uint16(xArgXmm1), + /*4296*/ uint16(xArgXmm2M64), + /*4297*/ uint16(xMatch), + /*4298*/ uint16(xSetOp), uint16(MINSS), + /*4300*/ uint16(xReadSlashR), + /*4301*/ uint16(xArgXmm1), + /*4302*/ uint16(xArgXmm2M32), + /*4303*/ uint16(xMatch), + /*4304*/ uint16(xCondPrefix), 4, + 0xF3, 4332, + 0xF2, 4326, + 0x66, 4320, + 0x0, 4314, + /*4314*/ uint16(xSetOp), uint16(DIVPS), + /*4316*/ uint16(xReadSlashR), + /*4317*/ uint16(xArgXmm1), + /*4318*/ uint16(xArgXmm2M128), + /*4319*/ uint16(xMatch), + /*4320*/ uint16(xSetOp), uint16(DIVPD), + /*4322*/ uint16(xReadSlashR), + /*4323*/ uint16(xArgXmm1), + /*4324*/ uint16(xArgXmm2M128), + /*4325*/ uint16(xMatch), + /*4326*/ uint16(xSetOp), uint16(DIVSD), + /*4328*/ uint16(xReadSlashR), + /*4329*/ uint16(xArgXmm1), + /*4330*/ uint16(xArgXmm2M64), + /*4331*/ uint16(xMatch), + /*4332*/ uint16(xSetOp), uint16(DIVSS), + /*4334*/ uint16(xReadSlashR), + /*4335*/ uint16(xArgXmm1), + /*4336*/ uint16(xArgXmm2M32), + /*4337*/ uint16(xMatch), + /*4338*/ uint16(xCondPrefix), 4, + 0xF3, 4366, + 0xF2, 4360, + 0x66, 4354, + 0x0, 4348, + /*4348*/ uint16(xSetOp), uint16(MAXPS), + /*4350*/ uint16(xReadSlashR), + /*4351*/ uint16(xArgXmm1), + /*4352*/ uint16(xArgXmm2M128), + /*4353*/ uint16(xMatch), + /*4354*/ uint16(xSetOp), uint16(MAXPD), + /*4356*/ uint16(xReadSlashR), + /*4357*/ uint16(xArgXmm1), + /*4358*/ uint16(xArgXmm2M128), + /*4359*/ uint16(xMatch), + /*4360*/ uint16(xSetOp), uint16(MAXSD), + /*4362*/ uint16(xReadSlashR), + /*4363*/ uint16(xArgXmm1), + /*4364*/ uint16(xArgXmm2M64), + /*4365*/ uint16(xMatch), + /*4366*/ uint16(xSetOp), uint16(MAXSS), + /*4368*/ uint16(xReadSlashR), + /*4369*/ uint16(xArgXmm1), + /*4370*/ uint16(xArgXmm2M32), + /*4371*/ uint16(xMatch), + /*4372*/ uint16(xCondPrefix), 2, + 0x66, 4384, + 0x0, 4378, + /*4378*/ uint16(xSetOp), uint16(PUNPCKLBW), + /*4380*/ uint16(xReadSlashR), + /*4381*/ uint16(xArgMm), + /*4382*/ uint16(xArgMmM32), + /*4383*/ uint16(xMatch), + /*4384*/ uint16(xSetOp), uint16(PUNPCKLBW), + /*4386*/ uint16(xReadSlashR), + /*4387*/ uint16(xArgXmm1), + /*4388*/ uint16(xArgXmm2M128), + /*4389*/ uint16(xMatch), + /*4390*/ uint16(xCondPrefix), 2, + 0x66, 4402, + 0x0, 4396, + /*4396*/ uint16(xSetOp), uint16(PUNPCKLWD), + /*4398*/ uint16(xReadSlashR), + /*4399*/ uint16(xArgMm), + /*4400*/ uint16(xArgMmM32), + /*4401*/ uint16(xMatch), + /*4402*/ uint16(xSetOp), uint16(PUNPCKLWD), + /*4404*/ uint16(xReadSlashR), + /*4405*/ uint16(xArgXmm1), + /*4406*/ uint16(xArgXmm2M128), + /*4407*/ uint16(xMatch), + /*4408*/ uint16(xCondPrefix), 2, + 0x66, 4420, + 0x0, 4414, + /*4414*/ uint16(xSetOp), uint16(PUNPCKLDQ), + /*4416*/ uint16(xReadSlashR), + /*4417*/ uint16(xArgMm), + /*4418*/ uint16(xArgMmM32), + /*4419*/ uint16(xMatch), + /*4420*/ uint16(xSetOp), uint16(PUNPCKLDQ), + /*4422*/ uint16(xReadSlashR), + /*4423*/ uint16(xArgXmm1), + /*4424*/ uint16(xArgXmm2M128), + /*4425*/ uint16(xMatch), + /*4426*/ uint16(xCondPrefix), 2, + 0x66, 4438, + 0x0, 4432, + /*4432*/ uint16(xSetOp), uint16(PACKSSWB), + /*4434*/ uint16(xReadSlashR), + /*4435*/ uint16(xArgMm1), + /*4436*/ uint16(xArgMm2M64), + /*4437*/ uint16(xMatch), + /*4438*/ uint16(xSetOp), uint16(PACKSSWB), + /*4440*/ uint16(xReadSlashR), + /*4441*/ uint16(xArgXmm1), + /*4442*/ uint16(xArgXmm2M128), + /*4443*/ uint16(xMatch), + /*4444*/ uint16(xCondPrefix), 2, + 0x66, 4456, + 0x0, 4450, + /*4450*/ uint16(xSetOp), uint16(PCMPGTB), + /*4452*/ uint16(xReadSlashR), + /*4453*/ uint16(xArgMm), + /*4454*/ uint16(xArgMmM64), + /*4455*/ uint16(xMatch), + /*4456*/ uint16(xSetOp), uint16(PCMPGTB), + /*4458*/ uint16(xReadSlashR), + /*4459*/ uint16(xArgXmm1), + /*4460*/ uint16(xArgXmm2M128), + /*4461*/ uint16(xMatch), + /*4462*/ uint16(xCondPrefix), 2, + 0x66, 4474, + 0x0, 4468, + /*4468*/ uint16(xSetOp), uint16(PCMPGTW), + /*4470*/ uint16(xReadSlashR), + /*4471*/ uint16(xArgMm), + /*4472*/ uint16(xArgMmM64), + /*4473*/ uint16(xMatch), + /*4474*/ uint16(xSetOp), uint16(PCMPGTW), + /*4476*/ uint16(xReadSlashR), + /*4477*/ uint16(xArgXmm1), + /*4478*/ uint16(xArgXmm2M128), + /*4479*/ uint16(xMatch), + /*4480*/ uint16(xCondPrefix), 2, + 0x66, 4492, + 0x0, 4486, + /*4486*/ uint16(xSetOp), uint16(PCMPGTD), + /*4488*/ uint16(xReadSlashR), + /*4489*/ uint16(xArgMm), + /*4490*/ uint16(xArgMmM64), + /*4491*/ uint16(xMatch), + /*4492*/ uint16(xSetOp), uint16(PCMPGTD), + /*4494*/ uint16(xReadSlashR), + /*4495*/ uint16(xArgXmm1), + /*4496*/ uint16(xArgXmm2M128), + /*4497*/ uint16(xMatch), + /*4498*/ uint16(xCondPrefix), 2, + 0x66, 4510, + 0x0, 4504, + /*4504*/ uint16(xSetOp), uint16(PACKUSWB), + /*4506*/ uint16(xReadSlashR), + /*4507*/ uint16(xArgMm), + /*4508*/ uint16(xArgMmM64), + /*4509*/ uint16(xMatch), + /*4510*/ uint16(xSetOp), uint16(PACKUSWB), + /*4512*/ uint16(xReadSlashR), + /*4513*/ uint16(xArgXmm1), + /*4514*/ uint16(xArgXmm2M128), + /*4515*/ uint16(xMatch), + /*4516*/ uint16(xCondPrefix), 2, + 0x66, 4528, + 0x0, 4522, + /*4522*/ uint16(xSetOp), uint16(PUNPCKHBW), + /*4524*/ uint16(xReadSlashR), + /*4525*/ uint16(xArgMm), + /*4526*/ uint16(xArgMmM64), + /*4527*/ uint16(xMatch), + /*4528*/ uint16(xSetOp), uint16(PUNPCKHBW), + /*4530*/ uint16(xReadSlashR), + /*4531*/ uint16(xArgXmm1), + /*4532*/ uint16(xArgXmm2M128), + /*4533*/ uint16(xMatch), + /*4534*/ uint16(xCondPrefix), 2, + 0x66, 4546, + 0x0, 4540, + /*4540*/ uint16(xSetOp), uint16(PUNPCKHWD), + /*4542*/ uint16(xReadSlashR), + /*4543*/ uint16(xArgMm), + /*4544*/ uint16(xArgMmM64), + /*4545*/ uint16(xMatch), + /*4546*/ uint16(xSetOp), uint16(PUNPCKHWD), + /*4548*/ uint16(xReadSlashR), + /*4549*/ uint16(xArgXmm1), + /*4550*/ uint16(xArgXmm2M128), + /*4551*/ uint16(xMatch), + /*4552*/ uint16(xCondPrefix), 2, + 0x66, 4564, + 0x0, 4558, + /*4558*/ uint16(xSetOp), uint16(PUNPCKHDQ), + /*4560*/ uint16(xReadSlashR), + /*4561*/ uint16(xArgMm), + /*4562*/ uint16(xArgMmM64), + /*4563*/ uint16(xMatch), + /*4564*/ uint16(xSetOp), uint16(PUNPCKHDQ), + /*4566*/ uint16(xReadSlashR), + /*4567*/ uint16(xArgXmm1), + /*4568*/ uint16(xArgXmm2M128), + /*4569*/ uint16(xMatch), + /*4570*/ uint16(xCondPrefix), 2, + 0x66, 4582, + 0x0, 4576, + /*4576*/ uint16(xSetOp), uint16(PACKSSDW), + /*4578*/ uint16(xReadSlashR), + /*4579*/ uint16(xArgMm1), + /*4580*/ uint16(xArgMm2M64), + /*4581*/ uint16(xMatch), + /*4582*/ uint16(xSetOp), uint16(PACKSSDW), + /*4584*/ uint16(xReadSlashR), + /*4585*/ uint16(xArgXmm1), + /*4586*/ uint16(xArgXmm2M128), + /*4587*/ uint16(xMatch), + /*4588*/ uint16(xCondPrefix), 1, + 0x66, 4592, + /*4592*/ uint16(xSetOp), uint16(PUNPCKLQDQ), + /*4594*/ uint16(xReadSlashR), + /*4595*/ uint16(xArgXmm1), + /*4596*/ uint16(xArgXmm2M128), + /*4597*/ uint16(xMatch), + /*4598*/ uint16(xCondPrefix), 1, + 0x66, 4602, + /*4602*/ uint16(xSetOp), uint16(PUNPCKHQDQ), + /*4604*/ uint16(xReadSlashR), + /*4605*/ uint16(xArgXmm1), + /*4606*/ uint16(xArgXmm2M128), + /*4607*/ uint16(xMatch), + /*4608*/ uint16(xCondIs64), 4611, 4649, + /*4611*/ uint16(xCondPrefix), 2, + 0x66, 4633, + 0x0, 4617, + /*4617*/ uint16(xCondDataSize), 4621, 4627, 0, + /*4621*/ uint16(xSetOp), uint16(MOVD), + /*4623*/ uint16(xReadSlashR), + /*4624*/ uint16(xArgMm), + /*4625*/ uint16(xArgRM32), + /*4626*/ uint16(xMatch), + /*4627*/ uint16(xSetOp), uint16(MOVD), + /*4629*/ uint16(xReadSlashR), + /*4630*/ uint16(xArgMm), + /*4631*/ uint16(xArgRM32), + /*4632*/ uint16(xMatch), + /*4633*/ uint16(xCondDataSize), 4637, 4643, 0, + /*4637*/ uint16(xSetOp), uint16(MOVD), + /*4639*/ uint16(xReadSlashR), + /*4640*/ uint16(xArgXmm), + /*4641*/ uint16(xArgRM32), + /*4642*/ uint16(xMatch), + /*4643*/ uint16(xSetOp), uint16(MOVD), + /*4645*/ uint16(xReadSlashR), + /*4646*/ uint16(xArgXmm), + /*4647*/ uint16(xArgRM32), + /*4648*/ uint16(xMatch), + /*4649*/ uint16(xCondPrefix), 2, + 0x66, 4665, + 0x0, 4655, + /*4655*/ uint16(xCondDataSize), 4621, 4627, 4659, + /*4659*/ uint16(xSetOp), uint16(MOVQ), + /*4661*/ uint16(xReadSlashR), + /*4662*/ uint16(xArgMm), + /*4663*/ uint16(xArgRM64), + /*4664*/ uint16(xMatch), + /*4665*/ uint16(xCondDataSize), 4637, 4643, 4669, + /*4669*/ uint16(xSetOp), uint16(MOVQ), + /*4671*/ uint16(xReadSlashR), + /*4672*/ uint16(xArgXmm), + /*4673*/ uint16(xArgRM64), + /*4674*/ uint16(xMatch), + /*4675*/ uint16(xCondPrefix), 3, + 0xF3, 4695, + 0x66, 4689, + 0x0, 4683, + /*4683*/ uint16(xSetOp), uint16(MOVQ), + /*4685*/ uint16(xReadSlashR), + /*4686*/ uint16(xArgMm), + /*4687*/ uint16(xArgMmM64), + /*4688*/ uint16(xMatch), + /*4689*/ uint16(xSetOp), uint16(MOVDQA), + /*4691*/ uint16(xReadSlashR), + /*4692*/ uint16(xArgXmm1), + /*4693*/ uint16(xArgXmm2M128), + /*4694*/ uint16(xMatch), + /*4695*/ uint16(xSetOp), uint16(MOVDQU), + /*4697*/ uint16(xReadSlashR), + /*4698*/ uint16(xArgXmm1), + /*4699*/ uint16(xArgXmm2M128), + /*4700*/ uint16(xMatch), + /*4701*/ uint16(xCondPrefix), 4, + 0xF3, 4735, + 0xF2, 4727, + 0x66, 4719, + 0x0, 4711, + /*4711*/ uint16(xSetOp), uint16(PSHUFW), + /*4713*/ uint16(xReadSlashR), + /*4714*/ uint16(xReadIb), + /*4715*/ uint16(xArgMm1), + /*4716*/ uint16(xArgMm2M64), + /*4717*/ uint16(xArgImm8u), + /*4718*/ uint16(xMatch), + /*4719*/ uint16(xSetOp), uint16(PSHUFD), + /*4721*/ uint16(xReadSlashR), + /*4722*/ uint16(xReadIb), + /*4723*/ uint16(xArgXmm1), + /*4724*/ uint16(xArgXmm2M128), + /*4725*/ uint16(xArgImm8u), + /*4726*/ uint16(xMatch), + /*4727*/ uint16(xSetOp), uint16(PSHUFLW), + /*4729*/ uint16(xReadSlashR), + /*4730*/ uint16(xReadIb), + /*4731*/ uint16(xArgXmm1), + /*4732*/ uint16(xArgXmm2M128), + /*4733*/ uint16(xArgImm8u), + /*4734*/ uint16(xMatch), + /*4735*/ uint16(xSetOp), uint16(PSHUFHW), + /*4737*/ uint16(xReadSlashR), + /*4738*/ uint16(xReadIb), + /*4739*/ uint16(xArgXmm1), + /*4740*/ uint16(xArgXmm2M128), + /*4741*/ uint16(xArgImm8u), + /*4742*/ uint16(xMatch), + /*4743*/ uint16(xCondSlashR), + 0, // 0 + 0, // 1 + 4752, // 2 + 0, // 3 + 4770, // 4 + 0, // 5 + 4788, // 6 + 0, // 7 + /*4752*/ uint16(xCondPrefix), 2, + 0x66, 4764, + 0x0, 4758, + /*4758*/ uint16(xSetOp), uint16(PSRLW), + /*4760*/ uint16(xReadIb), + /*4761*/ uint16(xArgMm2), + /*4762*/ uint16(xArgImm8u), + /*4763*/ uint16(xMatch), + /*4764*/ uint16(xSetOp), uint16(PSRLW), + /*4766*/ uint16(xReadIb), + /*4767*/ uint16(xArgXmm2), + /*4768*/ uint16(xArgImm8u), + /*4769*/ uint16(xMatch), + /*4770*/ uint16(xCondPrefix), 2, + 0x66, 4782, + 0x0, 4776, + /*4776*/ uint16(xSetOp), uint16(PSRAW), + /*4778*/ uint16(xReadIb), + /*4779*/ uint16(xArgMm2), + /*4780*/ uint16(xArgImm8u), + /*4781*/ uint16(xMatch), + /*4782*/ uint16(xSetOp), uint16(PSRAW), + /*4784*/ uint16(xReadIb), + /*4785*/ uint16(xArgXmm2), + /*4786*/ uint16(xArgImm8u), + /*4787*/ uint16(xMatch), + /*4788*/ uint16(xCondPrefix), 2, + 0x66, 4800, + 0x0, 4794, + /*4794*/ uint16(xSetOp), uint16(PSLLW), + /*4796*/ uint16(xReadIb), + /*4797*/ uint16(xArgMm2), + /*4798*/ uint16(xArgImm8u), + /*4799*/ uint16(xMatch), + /*4800*/ uint16(xSetOp), uint16(PSLLW), + /*4802*/ uint16(xReadIb), + /*4803*/ uint16(xArgXmm2), + /*4804*/ uint16(xArgImm8u), + /*4805*/ uint16(xMatch), + /*4806*/ uint16(xCondSlashR), + 0, // 0 + 0, // 1 + 4815, // 2 + 0, // 3 + 4833, // 4 + 0, // 5 + 4851, // 6 + 0, // 7 + /*4815*/ uint16(xCondPrefix), 2, + 0x66, 4827, + 0x0, 4821, + /*4821*/ uint16(xSetOp), uint16(PSRLD), + /*4823*/ uint16(xReadIb), + /*4824*/ uint16(xArgMm2), + /*4825*/ uint16(xArgImm8u), + /*4826*/ uint16(xMatch), + /*4827*/ uint16(xSetOp), uint16(PSRLD), + /*4829*/ uint16(xReadIb), + /*4830*/ uint16(xArgXmm2), + /*4831*/ uint16(xArgImm8u), + /*4832*/ uint16(xMatch), + /*4833*/ uint16(xCondPrefix), 2, + 0x66, 4845, + 0x0, 4839, + /*4839*/ uint16(xSetOp), uint16(PSRAD), + /*4841*/ uint16(xReadIb), + /*4842*/ uint16(xArgMm2), + /*4843*/ uint16(xArgImm8u), + /*4844*/ uint16(xMatch), + /*4845*/ uint16(xSetOp), uint16(PSRAD), + /*4847*/ uint16(xReadIb), + /*4848*/ uint16(xArgXmm2), + /*4849*/ uint16(xArgImm8u), + /*4850*/ uint16(xMatch), + /*4851*/ uint16(xCondPrefix), 2, + 0x66, 4863, + 0x0, 4857, + /*4857*/ uint16(xSetOp), uint16(PSLLD), + /*4859*/ uint16(xReadIb), + /*4860*/ uint16(xArgMm2), + /*4861*/ uint16(xArgImm8u), + /*4862*/ uint16(xMatch), + /*4863*/ uint16(xSetOp), uint16(PSLLD), + /*4865*/ uint16(xReadIb), + /*4866*/ uint16(xArgXmm2), + /*4867*/ uint16(xArgImm8u), + /*4868*/ uint16(xMatch), + /*4869*/ uint16(xCondSlashR), + 0, // 0 + 0, // 1 + 4878, // 2 + 4896, // 3 + 0, // 4 + 0, // 5 + 4906, // 6 + 4924, // 7 + /*4878*/ uint16(xCondPrefix), 2, + 0x66, 4890, + 0x0, 4884, + /*4884*/ uint16(xSetOp), uint16(PSRLQ), + /*4886*/ uint16(xReadIb), + /*4887*/ uint16(xArgMm2), + /*4888*/ uint16(xArgImm8u), + /*4889*/ uint16(xMatch), + /*4890*/ uint16(xSetOp), uint16(PSRLQ), + /*4892*/ uint16(xReadIb), + /*4893*/ uint16(xArgXmm2), + /*4894*/ uint16(xArgImm8u), + /*4895*/ uint16(xMatch), + /*4896*/ uint16(xCondPrefix), 1, + 0x66, 4900, + /*4900*/ uint16(xSetOp), uint16(PSRLDQ), + /*4902*/ uint16(xReadIb), + /*4903*/ uint16(xArgXmm2), + /*4904*/ uint16(xArgImm8u), + /*4905*/ uint16(xMatch), + /*4906*/ uint16(xCondPrefix), 2, + 0x66, 4918, + 0x0, 4912, + /*4912*/ uint16(xSetOp), uint16(PSLLQ), + /*4914*/ uint16(xReadIb), + /*4915*/ uint16(xArgMm2), + /*4916*/ uint16(xArgImm8u), + /*4917*/ uint16(xMatch), + /*4918*/ uint16(xSetOp), uint16(PSLLQ), + /*4920*/ uint16(xReadIb), + /*4921*/ uint16(xArgXmm2), + /*4922*/ uint16(xArgImm8u), + /*4923*/ uint16(xMatch), + /*4924*/ uint16(xCondPrefix), 1, + 0x66, 4928, + /*4928*/ uint16(xSetOp), uint16(PSLLDQ), + /*4930*/ uint16(xReadIb), + /*4931*/ uint16(xArgXmm2), + /*4932*/ uint16(xArgImm8u), + /*4933*/ uint16(xMatch), + /*4934*/ uint16(xCondPrefix), 2, + 0x66, 4946, + 0x0, 4940, + /*4940*/ uint16(xSetOp), uint16(PCMPEQB), + /*4942*/ uint16(xReadSlashR), + /*4943*/ uint16(xArgMm), + /*4944*/ uint16(xArgMmM64), + /*4945*/ uint16(xMatch), + /*4946*/ uint16(xSetOp), uint16(PCMPEQB), + /*4948*/ uint16(xReadSlashR), + /*4949*/ uint16(xArgXmm1), + /*4950*/ uint16(xArgXmm2M128), + /*4951*/ uint16(xMatch), + /*4952*/ uint16(xCondPrefix), 2, + 0x66, 4964, + 0x0, 4958, + /*4958*/ uint16(xSetOp), uint16(PCMPEQW), + /*4960*/ uint16(xReadSlashR), + /*4961*/ uint16(xArgMm), + /*4962*/ uint16(xArgMmM64), + /*4963*/ uint16(xMatch), + /*4964*/ uint16(xSetOp), uint16(PCMPEQW), + /*4966*/ uint16(xReadSlashR), + /*4967*/ uint16(xArgXmm1), + /*4968*/ uint16(xArgXmm2M128), + /*4969*/ uint16(xMatch), + /*4970*/ uint16(xCondPrefix), 2, + 0x66, 4982, + 0x0, 4976, + /*4976*/ uint16(xSetOp), uint16(PCMPEQD), + /*4978*/ uint16(xReadSlashR), + /*4979*/ uint16(xArgMm), + /*4980*/ uint16(xArgMmM64), + /*4981*/ uint16(xMatch), + /*4982*/ uint16(xSetOp), uint16(PCMPEQD), + /*4984*/ uint16(xReadSlashR), + /*4985*/ uint16(xArgXmm1), + /*4986*/ uint16(xArgXmm2M128), + /*4987*/ uint16(xMatch), + /*4988*/ uint16(xSetOp), uint16(EMMS), + /*4990*/ uint16(xMatch), + /*4991*/ uint16(xCondPrefix), 2, + 0xF2, 5003, + 0x66, 4997, + /*4997*/ uint16(xSetOp), uint16(HADDPD), + /*4999*/ uint16(xReadSlashR), + /*5000*/ uint16(xArgXmm1), + /*5001*/ uint16(xArgXmm2M128), + /*5002*/ uint16(xMatch), + /*5003*/ uint16(xSetOp), uint16(HADDPS), + /*5005*/ uint16(xReadSlashR), + /*5006*/ uint16(xArgXmm1), + /*5007*/ uint16(xArgXmm2M128), + /*5008*/ uint16(xMatch), + /*5009*/ uint16(xCondPrefix), 2, + 0xF2, 5021, + 0x66, 5015, + /*5015*/ uint16(xSetOp), uint16(HSUBPD), + /*5017*/ uint16(xReadSlashR), + /*5018*/ uint16(xArgXmm1), + /*5019*/ uint16(xArgXmm2M128), + /*5020*/ uint16(xMatch), + /*5021*/ uint16(xSetOp), uint16(HSUBPS), + /*5023*/ uint16(xReadSlashR), + /*5024*/ uint16(xArgXmm1), + /*5025*/ uint16(xArgXmm2M128), + /*5026*/ uint16(xMatch), + /*5027*/ uint16(xCondIs64), 5030, 5076, + /*5030*/ uint16(xCondPrefix), 3, + 0xF3, 5070, + 0x66, 5054, + 0x0, 5038, + /*5038*/ uint16(xCondDataSize), 5042, 5048, 0, + /*5042*/ uint16(xSetOp), uint16(MOVD), + /*5044*/ uint16(xReadSlashR), + /*5045*/ uint16(xArgRM32), + /*5046*/ uint16(xArgMm), + /*5047*/ uint16(xMatch), + /*5048*/ uint16(xSetOp), uint16(MOVD), + /*5050*/ uint16(xReadSlashR), + /*5051*/ uint16(xArgRM32), + /*5052*/ uint16(xArgMm), + /*5053*/ uint16(xMatch), + /*5054*/ uint16(xCondDataSize), 5058, 5064, 0, + /*5058*/ uint16(xSetOp), uint16(MOVD), + /*5060*/ uint16(xReadSlashR), + /*5061*/ uint16(xArgRM32), + /*5062*/ uint16(xArgXmm), + /*5063*/ uint16(xMatch), + /*5064*/ uint16(xSetOp), uint16(MOVD), + /*5066*/ uint16(xReadSlashR), + /*5067*/ uint16(xArgRM32), + /*5068*/ uint16(xArgXmm), + /*5069*/ uint16(xMatch), + /*5070*/ uint16(xSetOp), uint16(MOVQ), + /*5072*/ uint16(xReadSlashR), + /*5073*/ uint16(xArgXmm1), + /*5074*/ uint16(xArgXmm2M64), + /*5075*/ uint16(xMatch), + /*5076*/ uint16(xCondPrefix), 3, + 0xF3, 5070, + 0x66, 5094, + 0x0, 5084, + /*5084*/ uint16(xCondDataSize), 5042, 5048, 5088, + /*5088*/ uint16(xSetOp), uint16(MOVQ), + /*5090*/ uint16(xReadSlashR), + /*5091*/ uint16(xArgRM64), + /*5092*/ uint16(xArgMm), + /*5093*/ uint16(xMatch), + /*5094*/ uint16(xCondDataSize), 5058, 5064, 5098, + /*5098*/ uint16(xSetOp), uint16(MOVQ), + /*5100*/ uint16(xReadSlashR), + /*5101*/ uint16(xArgRM64), + /*5102*/ uint16(xArgXmm), + /*5103*/ uint16(xMatch), + /*5104*/ uint16(xCondPrefix), 3, + 0xF3, 5124, + 0x66, 5118, + 0x0, 5112, + /*5112*/ uint16(xSetOp), uint16(MOVQ), + /*5114*/ uint16(xReadSlashR), + /*5115*/ uint16(xArgMmM64), + /*5116*/ uint16(xArgMm), + /*5117*/ uint16(xMatch), + /*5118*/ uint16(xSetOp), uint16(MOVDQA), + /*5120*/ uint16(xReadSlashR), + /*5121*/ uint16(xArgXmm2M128), + /*5122*/ uint16(xArgXmm1), + /*5123*/ uint16(xMatch), + /*5124*/ uint16(xSetOp), uint16(MOVDQU), + /*5126*/ uint16(xReadSlashR), + /*5127*/ uint16(xArgXmm2M128), + /*5128*/ uint16(xArgXmm1), + /*5129*/ uint16(xMatch), + /*5130*/ uint16(xCondIs64), 5133, 5147, + /*5133*/ uint16(xCondDataSize), 5137, 5142, 0, + /*5137*/ uint16(xSetOp), uint16(JO), + /*5139*/ uint16(xReadCw), + /*5140*/ uint16(xArgRel16), + /*5141*/ uint16(xMatch), + /*5142*/ uint16(xSetOp), uint16(JO), + /*5144*/ uint16(xReadCd), + /*5145*/ uint16(xArgRel32), + /*5146*/ uint16(xMatch), + /*5147*/ uint16(xCondDataSize), 5151, 5142, 5156, + /*5151*/ uint16(xSetOp), uint16(JO), + /*5153*/ uint16(xReadCd), + /*5154*/ uint16(xArgRel32), + /*5155*/ uint16(xMatch), + /*5156*/ uint16(xSetOp), uint16(JO), + /*5158*/ uint16(xReadCd), + /*5159*/ uint16(xArgRel32), + /*5160*/ uint16(xMatch), + /*5161*/ uint16(xCondIs64), 5164, 5178, + /*5164*/ uint16(xCondDataSize), 5168, 5173, 0, + /*5168*/ uint16(xSetOp), uint16(JNO), + /*5170*/ uint16(xReadCw), + /*5171*/ uint16(xArgRel16), + /*5172*/ uint16(xMatch), + /*5173*/ uint16(xSetOp), uint16(JNO), + /*5175*/ uint16(xReadCd), + /*5176*/ uint16(xArgRel32), + /*5177*/ uint16(xMatch), + /*5178*/ uint16(xCondDataSize), 5182, 5173, 5187, + /*5182*/ uint16(xSetOp), uint16(JNO), + /*5184*/ uint16(xReadCd), + /*5185*/ uint16(xArgRel32), + /*5186*/ uint16(xMatch), + /*5187*/ uint16(xSetOp), uint16(JNO), + /*5189*/ uint16(xReadCd), + /*5190*/ uint16(xArgRel32), + /*5191*/ uint16(xMatch), + /*5192*/ uint16(xCondIs64), 5195, 5209, + /*5195*/ uint16(xCondDataSize), 5199, 5204, 0, + /*5199*/ uint16(xSetOp), uint16(JB), + /*5201*/ uint16(xReadCw), + /*5202*/ uint16(xArgRel16), + /*5203*/ uint16(xMatch), + /*5204*/ uint16(xSetOp), uint16(JB), + /*5206*/ uint16(xReadCd), + /*5207*/ uint16(xArgRel32), + /*5208*/ uint16(xMatch), + /*5209*/ uint16(xCondDataSize), 5213, 5204, 5218, + /*5213*/ uint16(xSetOp), uint16(JB), + /*5215*/ uint16(xReadCd), + /*5216*/ uint16(xArgRel32), + /*5217*/ uint16(xMatch), + /*5218*/ uint16(xSetOp), uint16(JB), + /*5220*/ uint16(xReadCd), + /*5221*/ uint16(xArgRel32), + /*5222*/ uint16(xMatch), + /*5223*/ uint16(xCondIs64), 5226, 5240, + /*5226*/ uint16(xCondDataSize), 5230, 5235, 0, + /*5230*/ uint16(xSetOp), uint16(JAE), + /*5232*/ uint16(xReadCw), + /*5233*/ uint16(xArgRel16), + /*5234*/ uint16(xMatch), + /*5235*/ uint16(xSetOp), uint16(JAE), + /*5237*/ uint16(xReadCd), + /*5238*/ uint16(xArgRel32), + /*5239*/ uint16(xMatch), + /*5240*/ uint16(xCondDataSize), 5244, 5235, 5249, + /*5244*/ uint16(xSetOp), uint16(JAE), + /*5246*/ uint16(xReadCd), + /*5247*/ uint16(xArgRel32), + /*5248*/ uint16(xMatch), + /*5249*/ uint16(xSetOp), uint16(JAE), + /*5251*/ uint16(xReadCd), + /*5252*/ uint16(xArgRel32), + /*5253*/ uint16(xMatch), + /*5254*/ uint16(xCondIs64), 5257, 5271, + /*5257*/ uint16(xCondDataSize), 5261, 5266, 0, + /*5261*/ uint16(xSetOp), uint16(JE), + /*5263*/ uint16(xReadCw), + /*5264*/ uint16(xArgRel16), + /*5265*/ uint16(xMatch), + /*5266*/ uint16(xSetOp), uint16(JE), + /*5268*/ uint16(xReadCd), + /*5269*/ uint16(xArgRel32), + /*5270*/ uint16(xMatch), + /*5271*/ uint16(xCondDataSize), 5275, 5266, 5280, + /*5275*/ uint16(xSetOp), uint16(JE), + /*5277*/ uint16(xReadCd), + /*5278*/ uint16(xArgRel32), + /*5279*/ uint16(xMatch), + /*5280*/ uint16(xSetOp), uint16(JE), + /*5282*/ uint16(xReadCd), + /*5283*/ uint16(xArgRel32), + /*5284*/ uint16(xMatch), + /*5285*/ uint16(xCondIs64), 5288, 5302, + /*5288*/ uint16(xCondDataSize), 5292, 5297, 0, + /*5292*/ uint16(xSetOp), uint16(JNE), + /*5294*/ uint16(xReadCw), + /*5295*/ uint16(xArgRel16), + /*5296*/ uint16(xMatch), + /*5297*/ uint16(xSetOp), uint16(JNE), + /*5299*/ uint16(xReadCd), + /*5300*/ uint16(xArgRel32), + /*5301*/ uint16(xMatch), + /*5302*/ uint16(xCondDataSize), 5306, 5297, 5311, + /*5306*/ uint16(xSetOp), uint16(JNE), + /*5308*/ uint16(xReadCd), + /*5309*/ uint16(xArgRel32), + /*5310*/ uint16(xMatch), + /*5311*/ uint16(xSetOp), uint16(JNE), + /*5313*/ uint16(xReadCd), + /*5314*/ uint16(xArgRel32), + /*5315*/ uint16(xMatch), + /*5316*/ uint16(xCondIs64), 5319, 5333, + /*5319*/ uint16(xCondDataSize), 5323, 5328, 0, + /*5323*/ uint16(xSetOp), uint16(JBE), + /*5325*/ uint16(xReadCw), + /*5326*/ uint16(xArgRel16), + /*5327*/ uint16(xMatch), + /*5328*/ uint16(xSetOp), uint16(JBE), + /*5330*/ uint16(xReadCd), + /*5331*/ uint16(xArgRel32), + /*5332*/ uint16(xMatch), + /*5333*/ uint16(xCondDataSize), 5337, 5328, 5342, + /*5337*/ uint16(xSetOp), uint16(JBE), + /*5339*/ uint16(xReadCd), + /*5340*/ uint16(xArgRel32), + /*5341*/ uint16(xMatch), + /*5342*/ uint16(xSetOp), uint16(JBE), + /*5344*/ uint16(xReadCd), + /*5345*/ uint16(xArgRel32), + /*5346*/ uint16(xMatch), + /*5347*/ uint16(xCondIs64), 5350, 5364, + /*5350*/ uint16(xCondDataSize), 5354, 5359, 0, + /*5354*/ uint16(xSetOp), uint16(JA), + /*5356*/ uint16(xReadCw), + /*5357*/ uint16(xArgRel16), + /*5358*/ uint16(xMatch), + /*5359*/ uint16(xSetOp), uint16(JA), + /*5361*/ uint16(xReadCd), + /*5362*/ uint16(xArgRel32), + /*5363*/ uint16(xMatch), + /*5364*/ uint16(xCondDataSize), 5368, 5359, 5373, + /*5368*/ uint16(xSetOp), uint16(JA), + /*5370*/ uint16(xReadCd), + /*5371*/ uint16(xArgRel32), + /*5372*/ uint16(xMatch), + /*5373*/ uint16(xSetOp), uint16(JA), + /*5375*/ uint16(xReadCd), + /*5376*/ uint16(xArgRel32), + /*5377*/ uint16(xMatch), + /*5378*/ uint16(xCondIs64), 5381, 5395, + /*5381*/ uint16(xCondDataSize), 5385, 5390, 0, + /*5385*/ uint16(xSetOp), uint16(JS), + /*5387*/ uint16(xReadCw), + /*5388*/ uint16(xArgRel16), + /*5389*/ uint16(xMatch), + /*5390*/ uint16(xSetOp), uint16(JS), + /*5392*/ uint16(xReadCd), + /*5393*/ uint16(xArgRel32), + /*5394*/ uint16(xMatch), + /*5395*/ uint16(xCondDataSize), 5399, 5390, 5404, + /*5399*/ uint16(xSetOp), uint16(JS), + /*5401*/ uint16(xReadCd), + /*5402*/ uint16(xArgRel32), + /*5403*/ uint16(xMatch), + /*5404*/ uint16(xSetOp), uint16(JS), + /*5406*/ uint16(xReadCd), + /*5407*/ uint16(xArgRel32), + /*5408*/ uint16(xMatch), + /*5409*/ uint16(xCondIs64), 5412, 5426, + /*5412*/ uint16(xCondDataSize), 5416, 5421, 0, + /*5416*/ uint16(xSetOp), uint16(JNS), + /*5418*/ uint16(xReadCw), + /*5419*/ uint16(xArgRel16), + /*5420*/ uint16(xMatch), + /*5421*/ uint16(xSetOp), uint16(JNS), + /*5423*/ uint16(xReadCd), + /*5424*/ uint16(xArgRel32), + /*5425*/ uint16(xMatch), + /*5426*/ uint16(xCondDataSize), 5430, 5421, 5435, + /*5430*/ uint16(xSetOp), uint16(JNS), + /*5432*/ uint16(xReadCd), + /*5433*/ uint16(xArgRel32), + /*5434*/ uint16(xMatch), + /*5435*/ uint16(xSetOp), uint16(JNS), + /*5437*/ uint16(xReadCd), + /*5438*/ uint16(xArgRel32), + /*5439*/ uint16(xMatch), + /*5440*/ uint16(xCondIs64), 5443, 5457, + /*5443*/ uint16(xCondDataSize), 5447, 5452, 0, + /*5447*/ uint16(xSetOp), uint16(JP), + /*5449*/ uint16(xReadCw), + /*5450*/ uint16(xArgRel16), + /*5451*/ uint16(xMatch), + /*5452*/ uint16(xSetOp), uint16(JP), + /*5454*/ uint16(xReadCd), + /*5455*/ uint16(xArgRel32), + /*5456*/ uint16(xMatch), + /*5457*/ uint16(xCondDataSize), 5461, 5452, 5466, + /*5461*/ uint16(xSetOp), uint16(JP), + /*5463*/ uint16(xReadCd), + /*5464*/ uint16(xArgRel32), + /*5465*/ uint16(xMatch), + /*5466*/ uint16(xSetOp), uint16(JP), + /*5468*/ uint16(xReadCd), + /*5469*/ uint16(xArgRel32), + /*5470*/ uint16(xMatch), + /*5471*/ uint16(xCondIs64), 5474, 5488, + /*5474*/ uint16(xCondDataSize), 5478, 5483, 0, + /*5478*/ uint16(xSetOp), uint16(JNP), + /*5480*/ uint16(xReadCw), + /*5481*/ uint16(xArgRel16), + /*5482*/ uint16(xMatch), + /*5483*/ uint16(xSetOp), uint16(JNP), + /*5485*/ uint16(xReadCd), + /*5486*/ uint16(xArgRel32), + /*5487*/ uint16(xMatch), + /*5488*/ uint16(xCondDataSize), 5492, 5483, 5497, + /*5492*/ uint16(xSetOp), uint16(JNP), + /*5494*/ uint16(xReadCd), + /*5495*/ uint16(xArgRel32), + /*5496*/ uint16(xMatch), + /*5497*/ uint16(xSetOp), uint16(JNP), + /*5499*/ uint16(xReadCd), + /*5500*/ uint16(xArgRel32), + /*5501*/ uint16(xMatch), + /*5502*/ uint16(xCondIs64), 5505, 5519, + /*5505*/ uint16(xCondDataSize), 5509, 5514, 0, + /*5509*/ uint16(xSetOp), uint16(JL), + /*5511*/ uint16(xReadCw), + /*5512*/ uint16(xArgRel16), + /*5513*/ uint16(xMatch), + /*5514*/ uint16(xSetOp), uint16(JL), + /*5516*/ uint16(xReadCd), + /*5517*/ uint16(xArgRel32), + /*5518*/ uint16(xMatch), + /*5519*/ uint16(xCondDataSize), 5523, 5514, 5528, + /*5523*/ uint16(xSetOp), uint16(JL), + /*5525*/ uint16(xReadCd), + /*5526*/ uint16(xArgRel32), + /*5527*/ uint16(xMatch), + /*5528*/ uint16(xSetOp), uint16(JL), + /*5530*/ uint16(xReadCd), + /*5531*/ uint16(xArgRel32), + /*5532*/ uint16(xMatch), + /*5533*/ uint16(xCondIs64), 5536, 5550, + /*5536*/ uint16(xCondDataSize), 5540, 5545, 0, + /*5540*/ uint16(xSetOp), uint16(JGE), + /*5542*/ uint16(xReadCw), + /*5543*/ uint16(xArgRel16), + /*5544*/ uint16(xMatch), + /*5545*/ uint16(xSetOp), uint16(JGE), + /*5547*/ uint16(xReadCd), + /*5548*/ uint16(xArgRel32), + /*5549*/ uint16(xMatch), + /*5550*/ uint16(xCondDataSize), 5554, 5545, 5559, + /*5554*/ uint16(xSetOp), uint16(JGE), + /*5556*/ uint16(xReadCd), + /*5557*/ uint16(xArgRel32), + /*5558*/ uint16(xMatch), + /*5559*/ uint16(xSetOp), uint16(JGE), + /*5561*/ uint16(xReadCd), + /*5562*/ uint16(xArgRel32), + /*5563*/ uint16(xMatch), + /*5564*/ uint16(xCondIs64), 5567, 5581, + /*5567*/ uint16(xCondDataSize), 5571, 5576, 0, + /*5571*/ uint16(xSetOp), uint16(JLE), + /*5573*/ uint16(xReadCw), + /*5574*/ uint16(xArgRel16), + /*5575*/ uint16(xMatch), + /*5576*/ uint16(xSetOp), uint16(JLE), + /*5578*/ uint16(xReadCd), + /*5579*/ uint16(xArgRel32), + /*5580*/ uint16(xMatch), + /*5581*/ uint16(xCondDataSize), 5585, 5576, 5590, + /*5585*/ uint16(xSetOp), uint16(JLE), + /*5587*/ uint16(xReadCd), + /*5588*/ uint16(xArgRel32), + /*5589*/ uint16(xMatch), + /*5590*/ uint16(xSetOp), uint16(JLE), + /*5592*/ uint16(xReadCd), + /*5593*/ uint16(xArgRel32), + /*5594*/ uint16(xMatch), + /*5595*/ uint16(xCondIs64), 5598, 5612, + /*5598*/ uint16(xCondDataSize), 5602, 5607, 0, + /*5602*/ uint16(xSetOp), uint16(JG), + /*5604*/ uint16(xReadCw), + /*5605*/ uint16(xArgRel16), + /*5606*/ uint16(xMatch), + /*5607*/ uint16(xSetOp), uint16(JG), + /*5609*/ uint16(xReadCd), + /*5610*/ uint16(xArgRel32), + /*5611*/ uint16(xMatch), + /*5612*/ uint16(xCondDataSize), 5616, 5607, 5621, + /*5616*/ uint16(xSetOp), uint16(JG), + /*5618*/ uint16(xReadCd), + /*5619*/ uint16(xArgRel32), + /*5620*/ uint16(xMatch), + /*5621*/ uint16(xSetOp), uint16(JG), + /*5623*/ uint16(xReadCd), + /*5624*/ uint16(xArgRel32), + /*5625*/ uint16(xMatch), + /*5626*/ uint16(xSetOp), uint16(SETO), + /*5628*/ uint16(xReadSlashR), + /*5629*/ uint16(xArgRM8), + /*5630*/ uint16(xMatch), + /*5631*/ uint16(xSetOp), uint16(SETNO), + /*5633*/ uint16(xReadSlashR), + /*5634*/ uint16(xArgRM8), + /*5635*/ uint16(xMatch), + /*5636*/ uint16(xSetOp), uint16(SETB), + /*5638*/ uint16(xReadSlashR), + /*5639*/ uint16(xArgRM8), + /*5640*/ uint16(xMatch), + /*5641*/ uint16(xSetOp), uint16(SETAE), + /*5643*/ uint16(xReadSlashR), + /*5644*/ uint16(xArgRM8), + /*5645*/ uint16(xMatch), + /*5646*/ uint16(xSetOp), uint16(SETE), + /*5648*/ uint16(xReadSlashR), + /*5649*/ uint16(xArgRM8), + /*5650*/ uint16(xMatch), + /*5651*/ uint16(xSetOp), uint16(SETNE), + /*5653*/ uint16(xReadSlashR), + /*5654*/ uint16(xArgRM8), + /*5655*/ uint16(xMatch), + /*5656*/ uint16(xSetOp), uint16(SETBE), + /*5658*/ uint16(xReadSlashR), + /*5659*/ uint16(xArgRM8), + /*5660*/ uint16(xMatch), + /*5661*/ uint16(xSetOp), uint16(SETA), + /*5663*/ uint16(xReadSlashR), + /*5664*/ uint16(xArgRM8), + /*5665*/ uint16(xMatch), + /*5666*/ uint16(xSetOp), uint16(SETS), + /*5668*/ uint16(xReadSlashR), + /*5669*/ uint16(xArgRM8), + /*5670*/ uint16(xMatch), + /*5671*/ uint16(xSetOp), uint16(SETNS), + /*5673*/ uint16(xReadSlashR), + /*5674*/ uint16(xArgRM8), + /*5675*/ uint16(xMatch), + /*5676*/ uint16(xSetOp), uint16(SETP), + /*5678*/ uint16(xReadSlashR), + /*5679*/ uint16(xArgRM8), + /*5680*/ uint16(xMatch), + /*5681*/ uint16(xSetOp), uint16(SETNP), + /*5683*/ uint16(xReadSlashR), + /*5684*/ uint16(xArgRM8), + /*5685*/ uint16(xMatch), + /*5686*/ uint16(xSetOp), uint16(SETL), + /*5688*/ uint16(xReadSlashR), + /*5689*/ uint16(xArgRM8), + /*5690*/ uint16(xMatch), + /*5691*/ uint16(xSetOp), uint16(SETGE), + /*5693*/ uint16(xReadSlashR), + /*5694*/ uint16(xArgRM8), + /*5695*/ uint16(xMatch), + /*5696*/ uint16(xSetOp), uint16(SETLE), + /*5698*/ uint16(xReadSlashR), + /*5699*/ uint16(xArgRM8), + /*5700*/ uint16(xMatch), + /*5701*/ uint16(xSetOp), uint16(SETG), + /*5703*/ uint16(xReadSlashR), + /*5704*/ uint16(xArgRM8), + /*5705*/ uint16(xMatch), + /*5706*/ uint16(xSetOp), uint16(PUSH), + /*5708*/ uint16(xArgFS), + /*5709*/ uint16(xMatch), + /*5710*/ uint16(xCondIs64), 5713, 5725, + /*5713*/ uint16(xCondDataSize), 5717, 5721, 0, + /*5717*/ uint16(xSetOp), uint16(POP), + /*5719*/ uint16(xArgFS), + /*5720*/ uint16(xMatch), + /*5721*/ uint16(xSetOp), uint16(POP), + /*5723*/ uint16(xArgFS), + /*5724*/ uint16(xMatch), + /*5725*/ uint16(xCondDataSize), 5717, 5729, 5733, + /*5729*/ uint16(xSetOp), uint16(POP), + /*5731*/ uint16(xArgFS), + /*5732*/ uint16(xMatch), + /*5733*/ uint16(xSetOp), uint16(POP), + /*5735*/ uint16(xArgFS), + /*5736*/ uint16(xMatch), + /*5737*/ uint16(xSetOp), uint16(CPUID), + /*5739*/ uint16(xMatch), + /*5740*/ uint16(xCondIs64), 5743, 5759, + /*5743*/ uint16(xCondDataSize), 5747, 5753, 0, + /*5747*/ uint16(xSetOp), uint16(BT), + /*5749*/ uint16(xReadSlashR), + /*5750*/ uint16(xArgRM16), + /*5751*/ uint16(xArgR16), + /*5752*/ uint16(xMatch), + /*5753*/ uint16(xSetOp), uint16(BT), + /*5755*/ uint16(xReadSlashR), + /*5756*/ uint16(xArgRM32), + /*5757*/ uint16(xArgR32), + /*5758*/ uint16(xMatch), + /*5759*/ uint16(xCondDataSize), 5747, 5753, 5763, + /*5763*/ uint16(xSetOp), uint16(BT), + /*5765*/ uint16(xReadSlashR), + /*5766*/ uint16(xArgRM64), + /*5767*/ uint16(xArgR64), + /*5768*/ uint16(xMatch), + /*5769*/ uint16(xCondIs64), 5772, 5792, + /*5772*/ uint16(xCondDataSize), 5776, 5784, 0, + /*5776*/ uint16(xSetOp), uint16(SHLD), + /*5778*/ uint16(xReadSlashR), + /*5779*/ uint16(xReadIb), + /*5780*/ uint16(xArgRM16), + /*5781*/ uint16(xArgR16), + /*5782*/ uint16(xArgImm8u), + /*5783*/ uint16(xMatch), + /*5784*/ uint16(xSetOp), uint16(SHLD), + /*5786*/ uint16(xReadSlashR), + /*5787*/ uint16(xReadIb), + /*5788*/ uint16(xArgRM32), + /*5789*/ uint16(xArgR32), + /*5790*/ uint16(xArgImm8u), + /*5791*/ uint16(xMatch), + /*5792*/ uint16(xCondDataSize), 5776, 5784, 5796, + /*5796*/ uint16(xSetOp), uint16(SHLD), + /*5798*/ uint16(xReadSlashR), + /*5799*/ uint16(xReadIb), + /*5800*/ uint16(xArgRM64), + /*5801*/ uint16(xArgR64), + /*5802*/ uint16(xArgImm8u), + /*5803*/ uint16(xMatch), + /*5804*/ uint16(xCondIs64), 5807, 5825, + /*5807*/ uint16(xCondDataSize), 5811, 5818, 0, + /*5811*/ uint16(xSetOp), uint16(SHLD), + /*5813*/ uint16(xReadSlashR), + /*5814*/ uint16(xArgRM16), + /*5815*/ uint16(xArgR16), + /*5816*/ uint16(xArgCL), + /*5817*/ uint16(xMatch), + /*5818*/ uint16(xSetOp), uint16(SHLD), + /*5820*/ uint16(xReadSlashR), + /*5821*/ uint16(xArgRM32), + /*5822*/ uint16(xArgR32), + /*5823*/ uint16(xArgCL), + /*5824*/ uint16(xMatch), + /*5825*/ uint16(xCondDataSize), 5811, 5818, 5829, + /*5829*/ uint16(xSetOp), uint16(SHLD), + /*5831*/ uint16(xReadSlashR), + /*5832*/ uint16(xArgRM64), + /*5833*/ uint16(xArgR64), + /*5834*/ uint16(xArgCL), + /*5835*/ uint16(xMatch), + /*5836*/ uint16(xSetOp), uint16(PUSH), + /*5838*/ uint16(xArgGS), + /*5839*/ uint16(xMatch), + /*5840*/ uint16(xCondIs64), 5843, 5855, + /*5843*/ uint16(xCondDataSize), 5847, 5851, 0, + /*5847*/ uint16(xSetOp), uint16(POP), + /*5849*/ uint16(xArgGS), + /*5850*/ uint16(xMatch), + /*5851*/ uint16(xSetOp), uint16(POP), + /*5853*/ uint16(xArgGS), + /*5854*/ uint16(xMatch), + /*5855*/ uint16(xCondDataSize), 5847, 5859, 5863, + /*5859*/ uint16(xSetOp), uint16(POP), + /*5861*/ uint16(xArgGS), + /*5862*/ uint16(xMatch), + /*5863*/ uint16(xSetOp), uint16(POP), + /*5865*/ uint16(xArgGS), + /*5866*/ uint16(xMatch), + /*5867*/ uint16(xSetOp), uint16(RSM), + /*5869*/ uint16(xMatch), + /*5870*/ uint16(xCondIs64), 5873, 5889, + /*5873*/ uint16(xCondDataSize), 5877, 5883, 0, + /*5877*/ uint16(xSetOp), uint16(BTS), + /*5879*/ uint16(xReadSlashR), + /*5880*/ uint16(xArgRM16), + /*5881*/ uint16(xArgR16), + /*5882*/ uint16(xMatch), + /*5883*/ uint16(xSetOp), uint16(BTS), + /*5885*/ uint16(xReadSlashR), + /*5886*/ uint16(xArgRM32), + /*5887*/ uint16(xArgR32), + /*5888*/ uint16(xMatch), + /*5889*/ uint16(xCondDataSize), 5877, 5883, 5893, + /*5893*/ uint16(xSetOp), uint16(BTS), + /*5895*/ uint16(xReadSlashR), + /*5896*/ uint16(xArgRM64), + /*5897*/ uint16(xArgR64), + /*5898*/ uint16(xMatch), + /*5899*/ uint16(xCondIs64), 5902, 5922, + /*5902*/ uint16(xCondDataSize), 5906, 5914, 0, + /*5906*/ uint16(xSetOp), uint16(SHRD), + /*5908*/ uint16(xReadSlashR), + /*5909*/ uint16(xReadIb), + /*5910*/ uint16(xArgRM16), + /*5911*/ uint16(xArgR16), + /*5912*/ uint16(xArgImm8u), + /*5913*/ uint16(xMatch), + /*5914*/ uint16(xSetOp), uint16(SHRD), + /*5916*/ uint16(xReadSlashR), + /*5917*/ uint16(xReadIb), + /*5918*/ uint16(xArgRM32), + /*5919*/ uint16(xArgR32), + /*5920*/ uint16(xArgImm8u), + /*5921*/ uint16(xMatch), + /*5922*/ uint16(xCondDataSize), 5906, 5914, 5926, + /*5926*/ uint16(xSetOp), uint16(SHRD), + /*5928*/ uint16(xReadSlashR), + /*5929*/ uint16(xReadIb), + /*5930*/ uint16(xArgRM64), + /*5931*/ uint16(xArgR64), + /*5932*/ uint16(xArgImm8u), + /*5933*/ uint16(xMatch), + /*5934*/ uint16(xCondIs64), 5937, 5955, + /*5937*/ uint16(xCondDataSize), 5941, 5948, 0, + /*5941*/ uint16(xSetOp), uint16(SHRD), + /*5943*/ uint16(xReadSlashR), + /*5944*/ uint16(xArgRM16), + /*5945*/ uint16(xArgR16), + /*5946*/ uint16(xArgCL), + /*5947*/ uint16(xMatch), + /*5948*/ uint16(xSetOp), uint16(SHRD), + /*5950*/ uint16(xReadSlashR), + /*5951*/ uint16(xArgRM32), + /*5952*/ uint16(xArgR32), + /*5953*/ uint16(xArgCL), + /*5954*/ uint16(xMatch), + /*5955*/ uint16(xCondDataSize), 5941, 5948, 5959, + /*5959*/ uint16(xSetOp), uint16(SHRD), + /*5961*/ uint16(xReadSlashR), + /*5962*/ uint16(xArgRM64), + /*5963*/ uint16(xArgR64), + /*5964*/ uint16(xArgCL), + /*5965*/ uint16(xMatch), + /*5966*/ uint16(xCondByte), 3, + 0xE8, 6215, + 0xF0, 6218, + 0xF8, 6221, + /*5974*/ uint16(xCondSlashR), + 5983, // 0 + 6037, // 1 + 6091, // 2 + 6120, // 3 + 6149, // 4 + 6172, // 5 + 6195, // 6 + 6211, // 7 + /*5983*/ uint16(xCondIs64), 5986, 5998, + /*5986*/ uint16(xCondDataSize), 5990, 5994, 0, + /*5990*/ uint16(xSetOp), uint16(FXSAVE), + /*5992*/ uint16(xArgM512byte), + /*5993*/ uint16(xMatch), + /*5994*/ uint16(xSetOp), uint16(FXSAVE), + /*5996*/ uint16(xArgM512byte), + /*5997*/ uint16(xMatch), + /*5998*/ uint16(xCondPrefix), 2, + 0xF3, 6012, + 0x0, 6004, + /*6004*/ uint16(xCondDataSize), 5990, 5994, 6008, + /*6008*/ uint16(xSetOp), uint16(FXSAVE64), + /*6010*/ uint16(xArgM512byte), + /*6011*/ uint16(xMatch), + /*6012*/ uint16(xCondDataSize), 6016, 6023, 6030, + /*6016*/ uint16(xCondIsMem), 6019, 0, + /*6019*/ uint16(xSetOp), uint16(RDFSBASE), + /*6021*/ uint16(xArgRM32), + /*6022*/ uint16(xMatch), + /*6023*/ uint16(xCondIsMem), 6026, 0, + /*6026*/ uint16(xSetOp), uint16(RDFSBASE), + /*6028*/ uint16(xArgRM32), + /*6029*/ uint16(xMatch), + /*6030*/ uint16(xCondIsMem), 6033, 0, + /*6033*/ uint16(xSetOp), uint16(RDFSBASE), + /*6035*/ uint16(xArgRM64), + /*6036*/ uint16(xMatch), + /*6037*/ uint16(xCondIs64), 6040, 6052, + /*6040*/ uint16(xCondDataSize), 6044, 6048, 0, + /*6044*/ uint16(xSetOp), uint16(FXRSTOR), + /*6046*/ uint16(xArgM512byte), + /*6047*/ uint16(xMatch), + /*6048*/ uint16(xSetOp), uint16(FXRSTOR), + /*6050*/ uint16(xArgM512byte), + /*6051*/ uint16(xMatch), + /*6052*/ uint16(xCondPrefix), 2, + 0xF3, 6066, + 0x0, 6058, + /*6058*/ uint16(xCondDataSize), 6044, 6048, 6062, + /*6062*/ uint16(xSetOp), uint16(FXRSTOR64), + /*6064*/ uint16(xArgM512byte), + /*6065*/ uint16(xMatch), + /*6066*/ uint16(xCondDataSize), 6070, 6077, 6084, + /*6070*/ uint16(xCondIsMem), 6073, 0, + /*6073*/ uint16(xSetOp), uint16(RDGSBASE), + /*6075*/ uint16(xArgRM32), + /*6076*/ uint16(xMatch), + /*6077*/ uint16(xCondIsMem), 6080, 0, + /*6080*/ uint16(xSetOp), uint16(RDGSBASE), + /*6082*/ uint16(xArgRM32), + /*6083*/ uint16(xMatch), + /*6084*/ uint16(xCondIsMem), 6087, 0, + /*6087*/ uint16(xSetOp), uint16(RDGSBASE), + /*6089*/ uint16(xArgRM64), + /*6090*/ uint16(xMatch), + /*6091*/ uint16(xCondIs64), 6094, 6098, + /*6094*/ uint16(xSetOp), uint16(LDMXCSR), + /*6096*/ uint16(xArgM32), + /*6097*/ uint16(xMatch), + /*6098*/ uint16(xCondPrefix), 2, + 0xF3, 6104, + 0x0, 6094, + /*6104*/ uint16(xCondDataSize), 6108, 6112, 6116, + /*6108*/ uint16(xSetOp), uint16(WRFSBASE), + /*6110*/ uint16(xArgRM32), + /*6111*/ uint16(xMatch), + /*6112*/ uint16(xSetOp), uint16(WRFSBASE), + /*6114*/ uint16(xArgRM32), + /*6115*/ uint16(xMatch), + /*6116*/ uint16(xSetOp), uint16(WRFSBASE), + /*6118*/ uint16(xArgRM64), + /*6119*/ uint16(xMatch), + /*6120*/ uint16(xCondIs64), 6123, 6127, + /*6123*/ uint16(xSetOp), uint16(STMXCSR), + /*6125*/ uint16(xArgM32), + /*6126*/ uint16(xMatch), + /*6127*/ uint16(xCondPrefix), 2, + 0xF3, 6133, + 0x0, 6123, + /*6133*/ uint16(xCondDataSize), 6137, 6141, 6145, + /*6137*/ uint16(xSetOp), uint16(WRGSBASE), + /*6139*/ uint16(xArgRM32), + /*6140*/ uint16(xMatch), + /*6141*/ uint16(xSetOp), uint16(WRGSBASE), + /*6143*/ uint16(xArgRM32), + /*6144*/ uint16(xMatch), + /*6145*/ uint16(xSetOp), uint16(WRGSBASE), + /*6147*/ uint16(xArgRM64), + /*6148*/ uint16(xMatch), + /*6149*/ uint16(xCondIs64), 6152, 6164, + /*6152*/ uint16(xCondDataSize), 6156, 6160, 0, + /*6156*/ uint16(xSetOp), uint16(XSAVE), + /*6158*/ uint16(xArgMem), + /*6159*/ uint16(xMatch), + /*6160*/ uint16(xSetOp), uint16(XSAVE), + /*6162*/ uint16(xArgMem), + /*6163*/ uint16(xMatch), + /*6164*/ uint16(xCondDataSize), 6156, 6160, 6168, + /*6168*/ uint16(xSetOp), uint16(XSAVE64), + /*6170*/ uint16(xArgMem), + /*6171*/ uint16(xMatch), + /*6172*/ uint16(xCondIs64), 6175, 6187, + /*6175*/ uint16(xCondDataSize), 6179, 6183, 0, + /*6179*/ uint16(xSetOp), uint16(XRSTOR), + /*6181*/ uint16(xArgMem), + /*6182*/ uint16(xMatch), + /*6183*/ uint16(xSetOp), uint16(XRSTOR), + /*6185*/ uint16(xArgMem), + /*6186*/ uint16(xMatch), + /*6187*/ uint16(xCondDataSize), 6179, 6183, 6191, + /*6191*/ uint16(xSetOp), uint16(XRSTOR64), + /*6193*/ uint16(xArgMem), + /*6194*/ uint16(xMatch), + /*6195*/ uint16(xCondDataSize), 6199, 6203, 6207, + /*6199*/ uint16(xSetOp), uint16(XSAVEOPT), + /*6201*/ uint16(xArgMem), + /*6202*/ uint16(xMatch), + /*6203*/ uint16(xSetOp), uint16(XSAVEOPT), + /*6205*/ uint16(xArgMem), + /*6206*/ uint16(xMatch), + /*6207*/ uint16(xSetOp), uint16(XSAVEOPT64), + /*6209*/ uint16(xArgMem), + /*6210*/ uint16(xMatch), + /*6211*/ uint16(xSetOp), uint16(CLFLUSH), + /*6213*/ uint16(xArgM8), + /*6214*/ uint16(xMatch), + /*6215*/ uint16(xSetOp), uint16(LFENCE), + /*6217*/ uint16(xMatch), + /*6218*/ uint16(xSetOp), uint16(MFENCE), + /*6220*/ uint16(xMatch), + /*6221*/ uint16(xSetOp), uint16(SFENCE), + /*6223*/ uint16(xMatch), + /*6224*/ uint16(xCondIs64), 6227, 6243, + /*6227*/ uint16(xCondDataSize), 6231, 6237, 0, + /*6231*/ uint16(xSetOp), uint16(IMUL), + /*6233*/ uint16(xReadSlashR), + /*6234*/ uint16(xArgR16), + /*6235*/ uint16(xArgRM16), + /*6236*/ uint16(xMatch), + /*6237*/ uint16(xSetOp), uint16(IMUL), + /*6239*/ uint16(xReadSlashR), + /*6240*/ uint16(xArgR32), + /*6241*/ uint16(xArgRM32), + /*6242*/ uint16(xMatch), + /*6243*/ uint16(xCondDataSize), 6231, 6237, 6247, + /*6247*/ uint16(xSetOp), uint16(IMUL), + /*6249*/ uint16(xReadSlashR), + /*6250*/ uint16(xArgR64), + /*6251*/ uint16(xArgRM64), + /*6252*/ uint16(xMatch), + /*6253*/ uint16(xSetOp), uint16(CMPXCHG), + /*6255*/ uint16(xReadSlashR), + /*6256*/ uint16(xArgRM8), + /*6257*/ uint16(xArgR8), + /*6258*/ uint16(xMatch), + /*6259*/ uint16(xCondIs64), 6262, 6278, + /*6262*/ uint16(xCondDataSize), 6266, 6272, 0, + /*6266*/ uint16(xSetOp), uint16(CMPXCHG), + /*6268*/ uint16(xReadSlashR), + /*6269*/ uint16(xArgRM16), + /*6270*/ uint16(xArgR16), + /*6271*/ uint16(xMatch), + /*6272*/ uint16(xSetOp), uint16(CMPXCHG), + /*6274*/ uint16(xReadSlashR), + /*6275*/ uint16(xArgRM32), + /*6276*/ uint16(xArgR32), + /*6277*/ uint16(xMatch), + /*6278*/ uint16(xCondDataSize), 6266, 6272, 6282, + /*6282*/ uint16(xSetOp), uint16(CMPXCHG), + /*6284*/ uint16(xReadSlashR), + /*6285*/ uint16(xArgRM64), + /*6286*/ uint16(xArgR64), + /*6287*/ uint16(xMatch), + /*6288*/ uint16(xCondIs64), 6291, 6307, + /*6291*/ uint16(xCondDataSize), 6295, 6301, 0, + /*6295*/ uint16(xSetOp), uint16(LSS), + /*6297*/ uint16(xReadSlashR), + /*6298*/ uint16(xArgR16), + /*6299*/ uint16(xArgM16colon16), + /*6300*/ uint16(xMatch), + /*6301*/ uint16(xSetOp), uint16(LSS), + /*6303*/ uint16(xReadSlashR), + /*6304*/ uint16(xArgR32), + /*6305*/ uint16(xArgM16colon32), + /*6306*/ uint16(xMatch), + /*6307*/ uint16(xCondDataSize), 6295, 6301, 6311, + /*6311*/ uint16(xSetOp), uint16(LSS), + /*6313*/ uint16(xReadSlashR), + /*6314*/ uint16(xArgR64), + /*6315*/ uint16(xArgM16colon64), + /*6316*/ uint16(xMatch), + /*6317*/ uint16(xCondIs64), 6320, 6336, + /*6320*/ uint16(xCondDataSize), 6324, 6330, 0, + /*6324*/ uint16(xSetOp), uint16(BTR), + /*6326*/ uint16(xReadSlashR), + /*6327*/ uint16(xArgRM16), + /*6328*/ uint16(xArgR16), + /*6329*/ uint16(xMatch), + /*6330*/ uint16(xSetOp), uint16(BTR), + /*6332*/ uint16(xReadSlashR), + /*6333*/ uint16(xArgRM32), + /*6334*/ uint16(xArgR32), + /*6335*/ uint16(xMatch), + /*6336*/ uint16(xCondDataSize), 6324, 6330, 6340, + /*6340*/ uint16(xSetOp), uint16(BTR), + /*6342*/ uint16(xReadSlashR), + /*6343*/ uint16(xArgRM64), + /*6344*/ uint16(xArgR64), + /*6345*/ uint16(xMatch), + /*6346*/ uint16(xCondIs64), 6349, 6365, + /*6349*/ uint16(xCondDataSize), 6353, 6359, 0, + /*6353*/ uint16(xSetOp), uint16(LFS), + /*6355*/ uint16(xReadSlashR), + /*6356*/ uint16(xArgR16), + /*6357*/ uint16(xArgM16colon16), + /*6358*/ uint16(xMatch), + /*6359*/ uint16(xSetOp), uint16(LFS), + /*6361*/ uint16(xReadSlashR), + /*6362*/ uint16(xArgR32), + /*6363*/ uint16(xArgM16colon32), + /*6364*/ uint16(xMatch), + /*6365*/ uint16(xCondDataSize), 6353, 6359, 6369, + /*6369*/ uint16(xSetOp), uint16(LFS), + /*6371*/ uint16(xReadSlashR), + /*6372*/ uint16(xArgR64), + /*6373*/ uint16(xArgM16colon64), + /*6374*/ uint16(xMatch), + /*6375*/ uint16(xCondIs64), 6378, 6394, + /*6378*/ uint16(xCondDataSize), 6382, 6388, 0, + /*6382*/ uint16(xSetOp), uint16(LGS), + /*6384*/ uint16(xReadSlashR), + /*6385*/ uint16(xArgR16), + /*6386*/ uint16(xArgM16colon16), + /*6387*/ uint16(xMatch), + /*6388*/ uint16(xSetOp), uint16(LGS), + /*6390*/ uint16(xReadSlashR), + /*6391*/ uint16(xArgR32), + /*6392*/ uint16(xArgM16colon32), + /*6393*/ uint16(xMatch), + /*6394*/ uint16(xCondDataSize), 6382, 6388, 6398, + /*6398*/ uint16(xSetOp), uint16(LGS), + /*6400*/ uint16(xReadSlashR), + /*6401*/ uint16(xArgR64), + /*6402*/ uint16(xArgM16colon64), + /*6403*/ uint16(xMatch), + /*6404*/ uint16(xCondIs64), 6407, 6423, + /*6407*/ uint16(xCondDataSize), 6411, 6417, 0, + /*6411*/ uint16(xSetOp), uint16(MOVZX), + /*6413*/ uint16(xReadSlashR), + /*6414*/ uint16(xArgR16), + /*6415*/ uint16(xArgRM8), + /*6416*/ uint16(xMatch), + /*6417*/ uint16(xSetOp), uint16(MOVZX), + /*6419*/ uint16(xReadSlashR), + /*6420*/ uint16(xArgR32), + /*6421*/ uint16(xArgRM8), + /*6422*/ uint16(xMatch), + /*6423*/ uint16(xCondDataSize), 6411, 6417, 6427, + /*6427*/ uint16(xSetOp), uint16(MOVZX), + /*6429*/ uint16(xReadSlashR), + /*6430*/ uint16(xArgR64), + /*6431*/ uint16(xArgRM8), + /*6432*/ uint16(xMatch), + /*6433*/ uint16(xCondIs64), 6436, 6452, + /*6436*/ uint16(xCondDataSize), 6440, 6446, 0, + /*6440*/ uint16(xSetOp), uint16(MOVZX), + /*6442*/ uint16(xReadSlashR), + /*6443*/ uint16(xArgR16), + /*6444*/ uint16(xArgRM16), + /*6445*/ uint16(xMatch), + /*6446*/ uint16(xSetOp), uint16(MOVZX), + /*6448*/ uint16(xReadSlashR), + /*6449*/ uint16(xArgR32), + /*6450*/ uint16(xArgRM16), + /*6451*/ uint16(xMatch), + /*6452*/ uint16(xCondDataSize), 6440, 6446, 6456, + /*6456*/ uint16(xSetOp), uint16(MOVZX), + /*6458*/ uint16(xReadSlashR), + /*6459*/ uint16(xArgR64), + /*6460*/ uint16(xArgRM16), + /*6461*/ uint16(xMatch), + /*6462*/ uint16(xCondIs64), 6465, 6485, + /*6465*/ uint16(xCondPrefix), 1, + 0xF3, 6469, + /*6469*/ uint16(xCondDataSize), 6473, 6479, 0, + /*6473*/ uint16(xSetOp), uint16(POPCNT), + /*6475*/ uint16(xReadSlashR), + /*6476*/ uint16(xArgR16), + /*6477*/ uint16(xArgRM16), + /*6478*/ uint16(xMatch), + /*6479*/ uint16(xSetOp), uint16(POPCNT), + /*6481*/ uint16(xReadSlashR), + /*6482*/ uint16(xArgR32), + /*6483*/ uint16(xArgRM32), + /*6484*/ uint16(xMatch), + /*6485*/ uint16(xCondPrefix), 1, + 0xF3, 6489, + /*6489*/ uint16(xCondDataSize), 6473, 6479, 6493, + /*6493*/ uint16(xSetOp), uint16(POPCNT), + /*6495*/ uint16(xReadSlashR), + /*6496*/ uint16(xArgR64), + /*6497*/ uint16(xArgRM64), + /*6498*/ uint16(xMatch), + /*6499*/ uint16(xSetOp), uint16(UD1), + /*6501*/ uint16(xMatch), + /*6502*/ uint16(xCondSlashR), + 0, // 0 + 0, // 1 + 0, // 2 + 0, // 3 + 6511, // 4 + 6540, // 5 + 6569, // 6 + 6598, // 7 + /*6511*/ uint16(xCondIs64), 6514, 6530, + /*6514*/ uint16(xCondDataSize), 6518, 6524, 0, + /*6518*/ uint16(xSetOp), uint16(BT), + /*6520*/ uint16(xReadIb), + /*6521*/ uint16(xArgRM16), + /*6522*/ uint16(xArgImm8u), + /*6523*/ uint16(xMatch), + /*6524*/ uint16(xSetOp), uint16(BT), + /*6526*/ uint16(xReadIb), + /*6527*/ uint16(xArgRM32), + /*6528*/ uint16(xArgImm8u), + /*6529*/ uint16(xMatch), + /*6530*/ uint16(xCondDataSize), 6518, 6524, 6534, + /*6534*/ uint16(xSetOp), uint16(BT), + /*6536*/ uint16(xReadIb), + /*6537*/ uint16(xArgRM64), + /*6538*/ uint16(xArgImm8u), + /*6539*/ uint16(xMatch), + /*6540*/ uint16(xCondIs64), 6543, 6559, + /*6543*/ uint16(xCondDataSize), 6547, 6553, 0, + /*6547*/ uint16(xSetOp), uint16(BTS), + /*6549*/ uint16(xReadIb), + /*6550*/ uint16(xArgRM16), + /*6551*/ uint16(xArgImm8u), + /*6552*/ uint16(xMatch), + /*6553*/ uint16(xSetOp), uint16(BTS), + /*6555*/ uint16(xReadIb), + /*6556*/ uint16(xArgRM32), + /*6557*/ uint16(xArgImm8u), + /*6558*/ uint16(xMatch), + /*6559*/ uint16(xCondDataSize), 6547, 6553, 6563, + /*6563*/ uint16(xSetOp), uint16(BTS), + /*6565*/ uint16(xReadIb), + /*6566*/ uint16(xArgRM64), + /*6567*/ uint16(xArgImm8u), + /*6568*/ uint16(xMatch), + /*6569*/ uint16(xCondIs64), 6572, 6588, + /*6572*/ uint16(xCondDataSize), 6576, 6582, 0, + /*6576*/ uint16(xSetOp), uint16(BTR), + /*6578*/ uint16(xReadIb), + /*6579*/ uint16(xArgRM16), + /*6580*/ uint16(xArgImm8u), + /*6581*/ uint16(xMatch), + /*6582*/ uint16(xSetOp), uint16(BTR), + /*6584*/ uint16(xReadIb), + /*6585*/ uint16(xArgRM32), + /*6586*/ uint16(xArgImm8u), + /*6587*/ uint16(xMatch), + /*6588*/ uint16(xCondDataSize), 6576, 6582, 6592, + /*6592*/ uint16(xSetOp), uint16(BTR), + /*6594*/ uint16(xReadIb), + /*6595*/ uint16(xArgRM64), + /*6596*/ uint16(xArgImm8u), + /*6597*/ uint16(xMatch), + /*6598*/ uint16(xCondIs64), 6601, 6617, + /*6601*/ uint16(xCondDataSize), 6605, 6611, 0, + /*6605*/ uint16(xSetOp), uint16(BTC), + /*6607*/ uint16(xReadIb), + /*6608*/ uint16(xArgRM16), + /*6609*/ uint16(xArgImm8u), + /*6610*/ uint16(xMatch), + /*6611*/ uint16(xSetOp), uint16(BTC), + /*6613*/ uint16(xReadIb), + /*6614*/ uint16(xArgRM32), + /*6615*/ uint16(xArgImm8u), + /*6616*/ uint16(xMatch), + /*6617*/ uint16(xCondDataSize), 6605, 6611, 6621, + /*6621*/ uint16(xSetOp), uint16(BTC), + /*6623*/ uint16(xReadIb), + /*6624*/ uint16(xArgRM64), + /*6625*/ uint16(xArgImm8u), + /*6626*/ uint16(xMatch), + /*6627*/ uint16(xCondIs64), 6630, 6646, + /*6630*/ uint16(xCondDataSize), 6634, 6640, 0, + /*6634*/ uint16(xSetOp), uint16(BTC), + /*6636*/ uint16(xReadSlashR), + /*6637*/ uint16(xArgRM16), + /*6638*/ uint16(xArgR16), + /*6639*/ uint16(xMatch), + /*6640*/ uint16(xSetOp), uint16(BTC), + /*6642*/ uint16(xReadSlashR), + /*6643*/ uint16(xArgRM32), + /*6644*/ uint16(xArgR32), + /*6645*/ uint16(xMatch), + /*6646*/ uint16(xCondDataSize), 6634, 6640, 6650, + /*6650*/ uint16(xSetOp), uint16(BTC), + /*6652*/ uint16(xReadSlashR), + /*6653*/ uint16(xArgRM64), + /*6654*/ uint16(xArgR64), + /*6655*/ uint16(xMatch), + /*6656*/ uint16(xCondIs64), 6659, 6697, + /*6659*/ uint16(xCondPrefix), 2, + 0xF3, 6681, + 0x0, 6665, + /*6665*/ uint16(xCondDataSize), 6669, 6675, 0, + /*6669*/ uint16(xSetOp), uint16(BSF), + /*6671*/ uint16(xReadSlashR), + /*6672*/ uint16(xArgR16), + /*6673*/ uint16(xArgRM16), + /*6674*/ uint16(xMatch), + /*6675*/ uint16(xSetOp), uint16(BSF), + /*6677*/ uint16(xReadSlashR), + /*6678*/ uint16(xArgR32), + /*6679*/ uint16(xArgRM32), + /*6680*/ uint16(xMatch), + /*6681*/ uint16(xCondDataSize), 6685, 6691, 0, + /*6685*/ uint16(xSetOp), uint16(TZCNT), + /*6687*/ uint16(xReadSlashR), + /*6688*/ uint16(xArgR16), + /*6689*/ uint16(xArgRM16), + /*6690*/ uint16(xMatch), + /*6691*/ uint16(xSetOp), uint16(TZCNT), + /*6693*/ uint16(xReadSlashR), + /*6694*/ uint16(xArgR32), + /*6695*/ uint16(xArgRM32), + /*6696*/ uint16(xMatch), + /*6697*/ uint16(xCondPrefix), 2, + 0xF3, 6713, + 0x0, 6703, + /*6703*/ uint16(xCondDataSize), 6669, 6675, 6707, + /*6707*/ uint16(xSetOp), uint16(BSF), + /*6709*/ uint16(xReadSlashR), + /*6710*/ uint16(xArgR64), + /*6711*/ uint16(xArgRM64), + /*6712*/ uint16(xMatch), + /*6713*/ uint16(xCondDataSize), 6685, 6691, 6717, + /*6717*/ uint16(xSetOp), uint16(TZCNT), + /*6719*/ uint16(xReadSlashR), + /*6720*/ uint16(xArgR64), + /*6721*/ uint16(xArgRM64), + /*6722*/ uint16(xMatch), + /*6723*/ uint16(xCondIs64), 6726, 6764, + /*6726*/ uint16(xCondPrefix), 2, + 0xF3, 6748, + 0x0, 6732, + /*6732*/ uint16(xCondDataSize), 6736, 6742, 0, + /*6736*/ uint16(xSetOp), uint16(BSR), + /*6738*/ uint16(xReadSlashR), + /*6739*/ uint16(xArgR16), + /*6740*/ uint16(xArgRM16), + /*6741*/ uint16(xMatch), + /*6742*/ uint16(xSetOp), uint16(BSR), + /*6744*/ uint16(xReadSlashR), + /*6745*/ uint16(xArgR32), + /*6746*/ uint16(xArgRM32), + /*6747*/ uint16(xMatch), + /*6748*/ uint16(xCondDataSize), 6752, 6758, 0, + /*6752*/ uint16(xSetOp), uint16(LZCNT), + /*6754*/ uint16(xReadSlashR), + /*6755*/ uint16(xArgR16), + /*6756*/ uint16(xArgRM16), + /*6757*/ uint16(xMatch), + /*6758*/ uint16(xSetOp), uint16(LZCNT), + /*6760*/ uint16(xReadSlashR), + /*6761*/ uint16(xArgR32), + /*6762*/ uint16(xArgRM32), + /*6763*/ uint16(xMatch), + /*6764*/ uint16(xCondPrefix), 2, + 0xF3, 6780, + 0x0, 6770, + /*6770*/ uint16(xCondDataSize), 6736, 6742, 6774, + /*6774*/ uint16(xSetOp), uint16(BSR), + /*6776*/ uint16(xReadSlashR), + /*6777*/ uint16(xArgR64), + /*6778*/ uint16(xArgRM64), + /*6779*/ uint16(xMatch), + /*6780*/ uint16(xCondDataSize), 6752, 6758, 6784, + /*6784*/ uint16(xSetOp), uint16(LZCNT), + /*6786*/ uint16(xReadSlashR), + /*6787*/ uint16(xArgR64), + /*6788*/ uint16(xArgRM64), + /*6789*/ uint16(xMatch), + /*6790*/ uint16(xCondIs64), 6793, 6809, + /*6793*/ uint16(xCondDataSize), 6797, 6803, 0, + /*6797*/ uint16(xSetOp), uint16(MOVSX), + /*6799*/ uint16(xReadSlashR), + /*6800*/ uint16(xArgR16), + /*6801*/ uint16(xArgRM8), + /*6802*/ uint16(xMatch), + /*6803*/ uint16(xSetOp), uint16(MOVSX), + /*6805*/ uint16(xReadSlashR), + /*6806*/ uint16(xArgR32), + /*6807*/ uint16(xArgRM8), + /*6808*/ uint16(xMatch), + /*6809*/ uint16(xCondDataSize), 6797, 6803, 6813, + /*6813*/ uint16(xSetOp), uint16(MOVSX), + /*6815*/ uint16(xReadSlashR), + /*6816*/ uint16(xArgR64), + /*6817*/ uint16(xArgRM8), + /*6818*/ uint16(xMatch), + /*6819*/ uint16(xCondIs64), 6822, 6838, + /*6822*/ uint16(xCondDataSize), 6826, 6832, 0, + /*6826*/ uint16(xSetOp), uint16(MOVSX), + /*6828*/ uint16(xReadSlashR), + /*6829*/ uint16(xArgR16), + /*6830*/ uint16(xArgRM16), + /*6831*/ uint16(xMatch), + /*6832*/ uint16(xSetOp), uint16(MOVSX), + /*6834*/ uint16(xReadSlashR), + /*6835*/ uint16(xArgR32), + /*6836*/ uint16(xArgRM16), + /*6837*/ uint16(xMatch), + /*6838*/ uint16(xCondDataSize), 6826, 6832, 6842, + /*6842*/ uint16(xSetOp), uint16(MOVSX), + /*6844*/ uint16(xReadSlashR), + /*6845*/ uint16(xArgR64), + /*6846*/ uint16(xArgRM16), + /*6847*/ uint16(xMatch), + /*6848*/ uint16(xSetOp), uint16(XADD), + /*6850*/ uint16(xReadSlashR), + /*6851*/ uint16(xArgRM8), + /*6852*/ uint16(xArgR8), + /*6853*/ uint16(xMatch), + /*6854*/ uint16(xCondIs64), 6857, 6873, + /*6857*/ uint16(xCondDataSize), 6861, 6867, 0, + /*6861*/ uint16(xSetOp), uint16(XADD), + /*6863*/ uint16(xReadSlashR), + /*6864*/ uint16(xArgRM16), + /*6865*/ uint16(xArgR16), + /*6866*/ uint16(xMatch), + /*6867*/ uint16(xSetOp), uint16(XADD), + /*6869*/ uint16(xReadSlashR), + /*6870*/ uint16(xArgRM32), + /*6871*/ uint16(xArgR32), + /*6872*/ uint16(xMatch), + /*6873*/ uint16(xCondDataSize), 6861, 6867, 6877, + /*6877*/ uint16(xSetOp), uint16(XADD), + /*6879*/ uint16(xReadSlashR), + /*6880*/ uint16(xArgRM64), + /*6881*/ uint16(xArgR64), + /*6882*/ uint16(xMatch), + /*6883*/ uint16(xCondPrefix), 4, + 0xF3, 6917, + 0xF2, 6909, + 0x66, 6901, + 0x0, 6893, + /*6893*/ uint16(xSetOp), uint16(CMPPS), + /*6895*/ uint16(xReadSlashR), + /*6896*/ uint16(xReadIb), + /*6897*/ uint16(xArgXmm1), + /*6898*/ uint16(xArgXmm2M128), + /*6899*/ uint16(xArgImm8u), + /*6900*/ uint16(xMatch), + /*6901*/ uint16(xSetOp), uint16(CMPPD), + /*6903*/ uint16(xReadSlashR), + /*6904*/ uint16(xReadIb), + /*6905*/ uint16(xArgXmm1), + /*6906*/ uint16(xArgXmm2M128), + /*6907*/ uint16(xArgImm8u), + /*6908*/ uint16(xMatch), + /*6909*/ uint16(xSetOp), uint16(CMPSD_XMM), + /*6911*/ uint16(xReadSlashR), + /*6912*/ uint16(xReadIb), + /*6913*/ uint16(xArgXmm1), + /*6914*/ uint16(xArgXmm2M64), + /*6915*/ uint16(xArgImm8u), + /*6916*/ uint16(xMatch), + /*6917*/ uint16(xSetOp), uint16(CMPSS), + /*6919*/ uint16(xReadSlashR), + /*6920*/ uint16(xReadIb), + /*6921*/ uint16(xArgXmm1), + /*6922*/ uint16(xArgXmm2M32), + /*6923*/ uint16(xArgImm8u), + /*6924*/ uint16(xMatch), + /*6925*/ uint16(xCondIs64), 6928, 6944, + /*6928*/ uint16(xCondDataSize), 6932, 6938, 0, + /*6932*/ uint16(xSetOp), uint16(MOVNTI), + /*6934*/ uint16(xReadSlashR), + /*6935*/ uint16(xArgM32), + /*6936*/ uint16(xArgR32), + /*6937*/ uint16(xMatch), + /*6938*/ uint16(xSetOp), uint16(MOVNTI), + /*6940*/ uint16(xReadSlashR), + /*6941*/ uint16(xArgM32), + /*6942*/ uint16(xArgR32), + /*6943*/ uint16(xMatch), + /*6944*/ uint16(xCondDataSize), 6932, 6938, 6948, + /*6948*/ uint16(xSetOp), uint16(MOVNTI), + /*6950*/ uint16(xReadSlashR), + /*6951*/ uint16(xArgM64), + /*6952*/ uint16(xArgR64), + /*6953*/ uint16(xMatch), + /*6954*/ uint16(xCondPrefix), 2, + 0x66, 6968, + 0x0, 6960, + /*6960*/ uint16(xSetOp), uint16(PINSRW), + /*6962*/ uint16(xReadSlashR), + /*6963*/ uint16(xReadIb), + /*6964*/ uint16(xArgMm), + /*6965*/ uint16(xArgR32M16), + /*6966*/ uint16(xArgImm8u), + /*6967*/ uint16(xMatch), + /*6968*/ uint16(xSetOp), uint16(PINSRW), + /*6970*/ uint16(xReadSlashR), + /*6971*/ uint16(xReadIb), + /*6972*/ uint16(xArgXmm), + /*6973*/ uint16(xArgR32M16), + /*6974*/ uint16(xArgImm8u), + /*6975*/ uint16(xMatch), + /*6976*/ uint16(xCondPrefix), 2, + 0x66, 6990, + 0x0, 6982, + /*6982*/ uint16(xSetOp), uint16(PEXTRW), + /*6984*/ uint16(xReadSlashR), + /*6985*/ uint16(xReadIb), + /*6986*/ uint16(xArgR32), + /*6987*/ uint16(xArgMm2), + /*6988*/ uint16(xArgImm8u), + /*6989*/ uint16(xMatch), + /*6990*/ uint16(xSetOp), uint16(PEXTRW), + /*6992*/ uint16(xReadSlashR), + /*6993*/ uint16(xReadIb), + /*6994*/ uint16(xArgR32), + /*6995*/ uint16(xArgXmm2), + /*6996*/ uint16(xArgImm8u), + /*6997*/ uint16(xMatch), + /*6998*/ uint16(xCondPrefix), 2, + 0x66, 7012, + 0x0, 7004, + /*7004*/ uint16(xSetOp), uint16(SHUFPS), + /*7006*/ uint16(xReadSlashR), + /*7007*/ uint16(xReadIb), + /*7008*/ uint16(xArgXmm1), + /*7009*/ uint16(xArgXmm2M128), + /*7010*/ uint16(xArgImm8u), + /*7011*/ uint16(xMatch), + /*7012*/ uint16(xSetOp), uint16(SHUFPD), + /*7014*/ uint16(xReadSlashR), + /*7015*/ uint16(xReadIb), + /*7016*/ uint16(xArgXmm1), + /*7017*/ uint16(xArgXmm2M128), + /*7018*/ uint16(xArgImm8u), + /*7019*/ uint16(xMatch), + /*7020*/ uint16(xCondSlashR), + 0, // 0 + 7029, // 1 + 0, // 2 + 7052, // 3 + 7075, // 4 + 7098, // 5 + 7121, // 6 + 0, // 7 + /*7029*/ uint16(xCondIs64), 7032, 7044, + /*7032*/ uint16(xCondDataSize), 7036, 7040, 0, + /*7036*/ uint16(xSetOp), uint16(CMPXCHG8B), + /*7038*/ uint16(xArgM64), + /*7039*/ uint16(xMatch), + /*7040*/ uint16(xSetOp), uint16(CMPXCHG8B), + /*7042*/ uint16(xArgM64), + /*7043*/ uint16(xMatch), + /*7044*/ uint16(xCondDataSize), 7036, 7040, 7048, + /*7048*/ uint16(xSetOp), uint16(CMPXCHG16B), + /*7050*/ uint16(xArgM128), + /*7051*/ uint16(xMatch), + /*7052*/ uint16(xCondIs64), 7055, 7067, + /*7055*/ uint16(xCondDataSize), 7059, 7063, 0, + /*7059*/ uint16(xSetOp), uint16(XRSTORS), + /*7061*/ uint16(xArgMem), + /*7062*/ uint16(xMatch), + /*7063*/ uint16(xSetOp), uint16(XRSTORS), + /*7065*/ uint16(xArgMem), + /*7066*/ uint16(xMatch), + /*7067*/ uint16(xCondDataSize), 7059, 7063, 7071, + /*7071*/ uint16(xSetOp), uint16(XRSTORS64), + /*7073*/ uint16(xArgMem), + /*7074*/ uint16(xMatch), + /*7075*/ uint16(xCondIs64), 7078, 7090, + /*7078*/ uint16(xCondDataSize), 7082, 7086, 0, + /*7082*/ uint16(xSetOp), uint16(XSAVEC), + /*7084*/ uint16(xArgMem), + /*7085*/ uint16(xMatch), + /*7086*/ uint16(xSetOp), uint16(XSAVEC), + /*7088*/ uint16(xArgMem), + /*7089*/ uint16(xMatch), + /*7090*/ uint16(xCondDataSize), 7082, 7086, 7094, + /*7094*/ uint16(xSetOp), uint16(XSAVEC64), + /*7096*/ uint16(xArgMem), + /*7097*/ uint16(xMatch), + /*7098*/ uint16(xCondIs64), 7101, 7113, + /*7101*/ uint16(xCondDataSize), 7105, 7109, 0, + /*7105*/ uint16(xSetOp), uint16(XSAVES), + /*7107*/ uint16(xArgMem), + /*7108*/ uint16(xMatch), + /*7109*/ uint16(xSetOp), uint16(XSAVES), + /*7111*/ uint16(xArgMem), + /*7112*/ uint16(xMatch), + /*7113*/ uint16(xCondDataSize), 7105, 7109, 7117, + /*7117*/ uint16(xSetOp), uint16(XSAVES64), + /*7119*/ uint16(xArgMem), + /*7120*/ uint16(xMatch), + /*7121*/ uint16(xCondIs64), 7124, 7142, + /*7124*/ uint16(xCondDataSize), 7128, 7135, 0, + /*7128*/ uint16(xCondIsMem), 7131, 0, + /*7131*/ uint16(xSetOp), uint16(RDRAND), + /*7133*/ uint16(xArgRmf16), + /*7134*/ uint16(xMatch), + /*7135*/ uint16(xCondIsMem), 7138, 0, + /*7138*/ uint16(xSetOp), uint16(RDRAND), + /*7140*/ uint16(xArgRmf32), + /*7141*/ uint16(xMatch), + /*7142*/ uint16(xCondDataSize), 7128, 7135, 7146, + /*7146*/ uint16(xSetOp), uint16(RDRAND), + /*7148*/ uint16(xMatch), + /*7149*/ uint16(xCondIs64), 7152, 7164, + /*7152*/ uint16(xCondDataSize), 7156, 7160, 0, + /*7156*/ uint16(xSetOp), uint16(BSWAP), + /*7158*/ uint16(xArgR16op), + /*7159*/ uint16(xMatch), + /*7160*/ uint16(xSetOp), uint16(BSWAP), + /*7162*/ uint16(xArgR32op), + /*7163*/ uint16(xMatch), + /*7164*/ uint16(xCondDataSize), 7156, 7160, 7168, + /*7168*/ uint16(xSetOp), uint16(BSWAP), + /*7170*/ uint16(xArgR64op), + /*7171*/ uint16(xMatch), + /*7172*/ uint16(xCondPrefix), 2, + 0xF2, 7184, + 0x66, 7178, + /*7178*/ uint16(xSetOp), uint16(ADDSUBPD), + /*7180*/ uint16(xReadSlashR), + /*7181*/ uint16(xArgXmm1), + /*7182*/ uint16(xArgXmm2M128), + /*7183*/ uint16(xMatch), + /*7184*/ uint16(xSetOp), uint16(ADDSUBPS), + /*7186*/ uint16(xReadSlashR), + /*7187*/ uint16(xArgXmm1), + /*7188*/ uint16(xArgXmm2M128), + /*7189*/ uint16(xMatch), + /*7190*/ uint16(xCondPrefix), 2, + 0x66, 7202, + 0x0, 7196, + /*7196*/ uint16(xSetOp), uint16(PSRLW), + /*7198*/ uint16(xReadSlashR), + /*7199*/ uint16(xArgMm), + /*7200*/ uint16(xArgMmM64), + /*7201*/ uint16(xMatch), + /*7202*/ uint16(xSetOp), uint16(PSRLW), + /*7204*/ uint16(xReadSlashR), + /*7205*/ uint16(xArgXmm1), + /*7206*/ uint16(xArgXmm2M128), + /*7207*/ uint16(xMatch), + /*7208*/ uint16(xCondPrefix), 2, + 0x66, 7220, + 0x0, 7214, + /*7214*/ uint16(xSetOp), uint16(PSRLD), + /*7216*/ uint16(xReadSlashR), + /*7217*/ uint16(xArgMm), + /*7218*/ uint16(xArgMmM64), + /*7219*/ uint16(xMatch), + /*7220*/ uint16(xSetOp), uint16(PSRLD), + /*7222*/ uint16(xReadSlashR), + /*7223*/ uint16(xArgXmm1), + /*7224*/ uint16(xArgXmm2M128), + /*7225*/ uint16(xMatch), + /*7226*/ uint16(xCondPrefix), 2, + 0x66, 7238, + 0x0, 7232, + /*7232*/ uint16(xSetOp), uint16(PSRLQ), + /*7234*/ uint16(xReadSlashR), + /*7235*/ uint16(xArgMm), + /*7236*/ uint16(xArgMmM64), + /*7237*/ uint16(xMatch), + /*7238*/ uint16(xSetOp), uint16(PSRLQ), + /*7240*/ uint16(xReadSlashR), + /*7241*/ uint16(xArgXmm1), + /*7242*/ uint16(xArgXmm2M128), + /*7243*/ uint16(xMatch), + /*7244*/ uint16(xCondPrefix), 2, + 0x66, 7256, + 0x0, 7250, + /*7250*/ uint16(xSetOp), uint16(PADDQ), + /*7252*/ uint16(xReadSlashR), + /*7253*/ uint16(xArgMm1), + /*7254*/ uint16(xArgMm2M64), + /*7255*/ uint16(xMatch), + /*7256*/ uint16(xSetOp), uint16(PADDQ), + /*7258*/ uint16(xReadSlashR), + /*7259*/ uint16(xArgXmm1), + /*7260*/ uint16(xArgXmm2M128), + /*7261*/ uint16(xMatch), + /*7262*/ uint16(xCondPrefix), 2, + 0x66, 7274, + 0x0, 7268, + /*7268*/ uint16(xSetOp), uint16(PMULLW), + /*7270*/ uint16(xReadSlashR), + /*7271*/ uint16(xArgMm), + /*7272*/ uint16(xArgMmM64), + /*7273*/ uint16(xMatch), + /*7274*/ uint16(xSetOp), uint16(PMULLW), + /*7276*/ uint16(xReadSlashR), + /*7277*/ uint16(xArgXmm1), + /*7278*/ uint16(xArgXmm2M128), + /*7279*/ uint16(xMatch), + /*7280*/ uint16(xCondPrefix), 3, + 0xF3, 7300, + 0xF2, 7294, + 0x66, 7288, + /*7288*/ uint16(xSetOp), uint16(MOVQ), + /*7290*/ uint16(xReadSlashR), + /*7291*/ uint16(xArgXmm2M64), + /*7292*/ uint16(xArgXmm1), + /*7293*/ uint16(xMatch), + /*7294*/ uint16(xSetOp), uint16(MOVDQ2Q), + /*7296*/ uint16(xReadSlashR), + /*7297*/ uint16(xArgMm), + /*7298*/ uint16(xArgXmm2), + /*7299*/ uint16(xMatch), + /*7300*/ uint16(xSetOp), uint16(MOVQ2DQ), + /*7302*/ uint16(xReadSlashR), + /*7303*/ uint16(xArgXmm1), + /*7304*/ uint16(xArgMm2), + /*7305*/ uint16(xMatch), + /*7306*/ uint16(xCondPrefix), 2, + 0x66, 7318, + 0x0, 7312, + /*7312*/ uint16(xSetOp), uint16(PMOVMSKB), + /*7314*/ uint16(xReadSlashR), + /*7315*/ uint16(xArgR32), + /*7316*/ uint16(xArgMm2), + /*7317*/ uint16(xMatch), + /*7318*/ uint16(xSetOp), uint16(PMOVMSKB), + /*7320*/ uint16(xReadSlashR), + /*7321*/ uint16(xArgR32), + /*7322*/ uint16(xArgXmm2), + /*7323*/ uint16(xMatch), + /*7324*/ uint16(xCondPrefix), 2, + 0x66, 7336, + 0x0, 7330, + /*7330*/ uint16(xSetOp), uint16(PSUBUSB), + /*7332*/ uint16(xReadSlashR), + /*7333*/ uint16(xArgMm), + /*7334*/ uint16(xArgMmM64), + /*7335*/ uint16(xMatch), + /*7336*/ uint16(xSetOp), uint16(PSUBUSB), + /*7338*/ uint16(xReadSlashR), + /*7339*/ uint16(xArgXmm1), + /*7340*/ uint16(xArgXmm2M128), + /*7341*/ uint16(xMatch), + /*7342*/ uint16(xCondPrefix), 2, + 0x66, 7354, + 0x0, 7348, + /*7348*/ uint16(xSetOp), uint16(PSUBUSW), + /*7350*/ uint16(xReadSlashR), + /*7351*/ uint16(xArgMm), + /*7352*/ uint16(xArgMmM64), + /*7353*/ uint16(xMatch), + /*7354*/ uint16(xSetOp), uint16(PSUBUSW), + /*7356*/ uint16(xReadSlashR), + /*7357*/ uint16(xArgXmm1), + /*7358*/ uint16(xArgXmm2M128), + /*7359*/ uint16(xMatch), + /*7360*/ uint16(xCondPrefix), 2, + 0x66, 7372, + 0x0, 7366, + /*7366*/ uint16(xSetOp), uint16(PMINUB), + /*7368*/ uint16(xReadSlashR), + /*7369*/ uint16(xArgMm1), + /*7370*/ uint16(xArgMm2M64), + /*7371*/ uint16(xMatch), + /*7372*/ uint16(xSetOp), uint16(PMINUB), + /*7374*/ uint16(xReadSlashR), + /*7375*/ uint16(xArgXmm1), + /*7376*/ uint16(xArgXmm2M128), + /*7377*/ uint16(xMatch), + /*7378*/ uint16(xCondPrefix), 2, + 0x66, 7390, + 0x0, 7384, + /*7384*/ uint16(xSetOp), uint16(PAND), + /*7386*/ uint16(xReadSlashR), + /*7387*/ uint16(xArgMm), + /*7388*/ uint16(xArgMmM64), + /*7389*/ uint16(xMatch), + /*7390*/ uint16(xSetOp), uint16(PAND), + /*7392*/ uint16(xReadSlashR), + /*7393*/ uint16(xArgXmm1), + /*7394*/ uint16(xArgXmm2M128), + /*7395*/ uint16(xMatch), + /*7396*/ uint16(xCondPrefix), 2, + 0x66, 7408, + 0x0, 7402, + /*7402*/ uint16(xSetOp), uint16(PADDUSB), + /*7404*/ uint16(xReadSlashR), + /*7405*/ uint16(xArgMm), + /*7406*/ uint16(xArgMmM64), + /*7407*/ uint16(xMatch), + /*7408*/ uint16(xSetOp), uint16(PADDUSB), + /*7410*/ uint16(xReadSlashR), + /*7411*/ uint16(xArgXmm1), + /*7412*/ uint16(xArgXmm2M128), + /*7413*/ uint16(xMatch), + /*7414*/ uint16(xCondPrefix), 2, + 0x66, 7426, + 0x0, 7420, + /*7420*/ uint16(xSetOp), uint16(PADDUSW), + /*7422*/ uint16(xReadSlashR), + /*7423*/ uint16(xArgMm), + /*7424*/ uint16(xArgMmM64), + /*7425*/ uint16(xMatch), + /*7426*/ uint16(xSetOp), uint16(PADDUSW), + /*7428*/ uint16(xReadSlashR), + /*7429*/ uint16(xArgXmm1), + /*7430*/ uint16(xArgXmm2M128), + /*7431*/ uint16(xMatch), + /*7432*/ uint16(xCondPrefix), 2, + 0x66, 7444, + 0x0, 7438, + /*7438*/ uint16(xSetOp), uint16(PMAXUB), + /*7440*/ uint16(xReadSlashR), + /*7441*/ uint16(xArgMm1), + /*7442*/ uint16(xArgMm2M64), + /*7443*/ uint16(xMatch), + /*7444*/ uint16(xSetOp), uint16(PMAXUB), + /*7446*/ uint16(xReadSlashR), + /*7447*/ uint16(xArgXmm1), + /*7448*/ uint16(xArgXmm2M128), + /*7449*/ uint16(xMatch), + /*7450*/ uint16(xCondPrefix), 2, + 0x66, 7462, + 0x0, 7456, + /*7456*/ uint16(xSetOp), uint16(PANDN), + /*7458*/ uint16(xReadSlashR), + /*7459*/ uint16(xArgMm), + /*7460*/ uint16(xArgMmM64), + /*7461*/ uint16(xMatch), + /*7462*/ uint16(xSetOp), uint16(PANDN), + /*7464*/ uint16(xReadSlashR), + /*7465*/ uint16(xArgXmm1), + /*7466*/ uint16(xArgXmm2M128), + /*7467*/ uint16(xMatch), + /*7468*/ uint16(xCondPrefix), 2, + 0x66, 7480, + 0x0, 7474, + /*7474*/ uint16(xSetOp), uint16(PAVGB), + /*7476*/ uint16(xReadSlashR), + /*7477*/ uint16(xArgMm1), + /*7478*/ uint16(xArgMm2M64), + /*7479*/ uint16(xMatch), + /*7480*/ uint16(xSetOp), uint16(PAVGB), + /*7482*/ uint16(xReadSlashR), + /*7483*/ uint16(xArgXmm1), + /*7484*/ uint16(xArgXmm2M128), + /*7485*/ uint16(xMatch), + /*7486*/ uint16(xCondPrefix), 2, + 0x66, 7498, + 0x0, 7492, + /*7492*/ uint16(xSetOp), uint16(PSRAW), + /*7494*/ uint16(xReadSlashR), + /*7495*/ uint16(xArgMm), + /*7496*/ uint16(xArgMmM64), + /*7497*/ uint16(xMatch), + /*7498*/ uint16(xSetOp), uint16(PSRAW), + /*7500*/ uint16(xReadSlashR), + /*7501*/ uint16(xArgXmm1), + /*7502*/ uint16(xArgXmm2M128), + /*7503*/ uint16(xMatch), + /*7504*/ uint16(xCondPrefix), 2, + 0x66, 7516, + 0x0, 7510, + /*7510*/ uint16(xSetOp), uint16(PSRAD), + /*7512*/ uint16(xReadSlashR), + /*7513*/ uint16(xArgMm), + /*7514*/ uint16(xArgMmM64), + /*7515*/ uint16(xMatch), + /*7516*/ uint16(xSetOp), uint16(PSRAD), + /*7518*/ uint16(xReadSlashR), + /*7519*/ uint16(xArgXmm1), + /*7520*/ uint16(xArgXmm2M128), + /*7521*/ uint16(xMatch), + /*7522*/ uint16(xCondPrefix), 2, + 0x66, 7534, + 0x0, 7528, + /*7528*/ uint16(xSetOp), uint16(PAVGW), + /*7530*/ uint16(xReadSlashR), + /*7531*/ uint16(xArgMm1), + /*7532*/ uint16(xArgMm2M64), + /*7533*/ uint16(xMatch), + /*7534*/ uint16(xSetOp), uint16(PAVGW), + /*7536*/ uint16(xReadSlashR), + /*7537*/ uint16(xArgXmm1), + /*7538*/ uint16(xArgXmm2M128), + /*7539*/ uint16(xMatch), + /*7540*/ uint16(xCondPrefix), 2, + 0x66, 7552, + 0x0, 7546, + /*7546*/ uint16(xSetOp), uint16(PMULHUW), + /*7548*/ uint16(xReadSlashR), + /*7549*/ uint16(xArgMm1), + /*7550*/ uint16(xArgMm2M64), + /*7551*/ uint16(xMatch), + /*7552*/ uint16(xSetOp), uint16(PMULHUW), + /*7554*/ uint16(xReadSlashR), + /*7555*/ uint16(xArgXmm1), + /*7556*/ uint16(xArgXmm2M128), + /*7557*/ uint16(xMatch), + /*7558*/ uint16(xCondPrefix), 2, + 0x66, 7570, + 0x0, 7564, + /*7564*/ uint16(xSetOp), uint16(PMULHW), + /*7566*/ uint16(xReadSlashR), + /*7567*/ uint16(xArgMm), + /*7568*/ uint16(xArgMmM64), + /*7569*/ uint16(xMatch), + /*7570*/ uint16(xSetOp), uint16(PMULHW), + /*7572*/ uint16(xReadSlashR), + /*7573*/ uint16(xArgXmm1), + /*7574*/ uint16(xArgXmm2M128), + /*7575*/ uint16(xMatch), + /*7576*/ uint16(xCondPrefix), 3, + 0xF3, 7596, + 0xF2, 7590, + 0x66, 7584, + /*7584*/ uint16(xSetOp), uint16(CVTTPD2DQ), + /*7586*/ uint16(xReadSlashR), + /*7587*/ uint16(xArgXmm1), + /*7588*/ uint16(xArgXmm2M128), + /*7589*/ uint16(xMatch), + /*7590*/ uint16(xSetOp), uint16(CVTPD2DQ), + /*7592*/ uint16(xReadSlashR), + /*7593*/ uint16(xArgXmm1), + /*7594*/ uint16(xArgXmm2M128), + /*7595*/ uint16(xMatch), + /*7596*/ uint16(xSetOp), uint16(CVTDQ2PD), + /*7598*/ uint16(xReadSlashR), + /*7599*/ uint16(xArgXmm1), + /*7600*/ uint16(xArgXmm2M64), + /*7601*/ uint16(xMatch), + /*7602*/ uint16(xCondPrefix), 2, + 0x66, 7614, + 0x0, 7608, + /*7608*/ uint16(xSetOp), uint16(MOVNTQ), + /*7610*/ uint16(xReadSlashR), + /*7611*/ uint16(xArgM64), + /*7612*/ uint16(xArgMm), + /*7613*/ uint16(xMatch), + /*7614*/ uint16(xSetOp), uint16(MOVNTDQ), + /*7616*/ uint16(xReadSlashR), + /*7617*/ uint16(xArgM128), + /*7618*/ uint16(xArgXmm), + /*7619*/ uint16(xMatch), + /*7620*/ uint16(xCondPrefix), 2, + 0x66, 7632, + 0x0, 7626, + /*7626*/ uint16(xSetOp), uint16(PSUBSB), + /*7628*/ uint16(xReadSlashR), + /*7629*/ uint16(xArgMm), + /*7630*/ uint16(xArgMmM64), + /*7631*/ uint16(xMatch), + /*7632*/ uint16(xSetOp), uint16(PSUBSB), + /*7634*/ uint16(xReadSlashR), + /*7635*/ uint16(xArgXmm1), + /*7636*/ uint16(xArgXmm2M128), + /*7637*/ uint16(xMatch), + /*7638*/ uint16(xCondPrefix), 2, + 0x66, 7650, + 0x0, 7644, + /*7644*/ uint16(xSetOp), uint16(PSUBSW), + /*7646*/ uint16(xReadSlashR), + /*7647*/ uint16(xArgMm), + /*7648*/ uint16(xArgMmM64), + /*7649*/ uint16(xMatch), + /*7650*/ uint16(xSetOp), uint16(PSUBSW), + /*7652*/ uint16(xReadSlashR), + /*7653*/ uint16(xArgXmm1), + /*7654*/ uint16(xArgXmm2M128), + /*7655*/ uint16(xMatch), + /*7656*/ uint16(xCondPrefix), 2, + 0x66, 7668, + 0x0, 7662, + /*7662*/ uint16(xSetOp), uint16(PMINSW), + /*7664*/ uint16(xReadSlashR), + /*7665*/ uint16(xArgMm1), + /*7666*/ uint16(xArgMm2M64), + /*7667*/ uint16(xMatch), + /*7668*/ uint16(xSetOp), uint16(PMINSW), + /*7670*/ uint16(xReadSlashR), + /*7671*/ uint16(xArgXmm1), + /*7672*/ uint16(xArgXmm2M128), + /*7673*/ uint16(xMatch), + /*7674*/ uint16(xCondPrefix), 2, + 0x66, 7686, + 0x0, 7680, + /*7680*/ uint16(xSetOp), uint16(POR), + /*7682*/ uint16(xReadSlashR), + /*7683*/ uint16(xArgMm), + /*7684*/ uint16(xArgMmM64), + /*7685*/ uint16(xMatch), + /*7686*/ uint16(xSetOp), uint16(POR), + /*7688*/ uint16(xReadSlashR), + /*7689*/ uint16(xArgXmm1), + /*7690*/ uint16(xArgXmm2M128), + /*7691*/ uint16(xMatch), + /*7692*/ uint16(xCondPrefix), 2, + 0x66, 7704, + 0x0, 7698, + /*7698*/ uint16(xSetOp), uint16(PADDSB), + /*7700*/ uint16(xReadSlashR), + /*7701*/ uint16(xArgMm), + /*7702*/ uint16(xArgMmM64), + /*7703*/ uint16(xMatch), + /*7704*/ uint16(xSetOp), uint16(PADDSB), + /*7706*/ uint16(xReadSlashR), + /*7707*/ uint16(xArgXmm1), + /*7708*/ uint16(xArgXmm2M128), + /*7709*/ uint16(xMatch), + /*7710*/ uint16(xCondPrefix), 2, + 0x66, 7722, + 0x0, 7716, + /*7716*/ uint16(xSetOp), uint16(PADDSW), + /*7718*/ uint16(xReadSlashR), + /*7719*/ uint16(xArgMm), + /*7720*/ uint16(xArgMmM64), + /*7721*/ uint16(xMatch), + /*7722*/ uint16(xSetOp), uint16(PADDSW), + /*7724*/ uint16(xReadSlashR), + /*7725*/ uint16(xArgXmm1), + /*7726*/ uint16(xArgXmm2M128), + /*7727*/ uint16(xMatch), + /*7728*/ uint16(xCondPrefix), 2, + 0x66, 7740, + 0x0, 7734, + /*7734*/ uint16(xSetOp), uint16(PMAXSW), + /*7736*/ uint16(xReadSlashR), + /*7737*/ uint16(xArgMm1), + /*7738*/ uint16(xArgMm2M64), + /*7739*/ uint16(xMatch), + /*7740*/ uint16(xSetOp), uint16(PMAXSW), + /*7742*/ uint16(xReadSlashR), + /*7743*/ uint16(xArgXmm1), + /*7744*/ uint16(xArgXmm2M128), + /*7745*/ uint16(xMatch), + /*7746*/ uint16(xCondPrefix), 2, + 0x66, 7758, + 0x0, 7752, + /*7752*/ uint16(xSetOp), uint16(PXOR), + /*7754*/ uint16(xReadSlashR), + /*7755*/ uint16(xArgMm), + /*7756*/ uint16(xArgMmM64), + /*7757*/ uint16(xMatch), + /*7758*/ uint16(xSetOp), uint16(PXOR), + /*7760*/ uint16(xReadSlashR), + /*7761*/ uint16(xArgXmm1), + /*7762*/ uint16(xArgXmm2M128), + /*7763*/ uint16(xMatch), + /*7764*/ uint16(xCondPrefix), 1, + 0xF2, 7768, + /*7768*/ uint16(xSetOp), uint16(LDDQU), + /*7770*/ uint16(xReadSlashR), + /*7771*/ uint16(xArgXmm1), + /*7772*/ uint16(xArgM128), + /*7773*/ uint16(xMatch), + /*7774*/ uint16(xCondPrefix), 2, + 0x66, 7786, + 0x0, 7780, + /*7780*/ uint16(xSetOp), uint16(PSLLW), + /*7782*/ uint16(xReadSlashR), + /*7783*/ uint16(xArgMm), + /*7784*/ uint16(xArgMmM64), + /*7785*/ uint16(xMatch), + /*7786*/ uint16(xSetOp), uint16(PSLLW), + /*7788*/ uint16(xReadSlashR), + /*7789*/ uint16(xArgXmm1), + /*7790*/ uint16(xArgXmm2M128), + /*7791*/ uint16(xMatch), + /*7792*/ uint16(xCondPrefix), 2, + 0x66, 7804, + 0x0, 7798, + /*7798*/ uint16(xSetOp), uint16(PSLLD), + /*7800*/ uint16(xReadSlashR), + /*7801*/ uint16(xArgMm), + /*7802*/ uint16(xArgMmM64), + /*7803*/ uint16(xMatch), + /*7804*/ uint16(xSetOp), uint16(PSLLD), + /*7806*/ uint16(xReadSlashR), + /*7807*/ uint16(xArgXmm1), + /*7808*/ uint16(xArgXmm2M128), + /*7809*/ uint16(xMatch), + /*7810*/ uint16(xCondPrefix), 2, + 0x66, 7822, + 0x0, 7816, + /*7816*/ uint16(xSetOp), uint16(PSLLQ), + /*7818*/ uint16(xReadSlashR), + /*7819*/ uint16(xArgMm), + /*7820*/ uint16(xArgMmM64), + /*7821*/ uint16(xMatch), + /*7822*/ uint16(xSetOp), uint16(PSLLQ), + /*7824*/ uint16(xReadSlashR), + /*7825*/ uint16(xArgXmm1), + /*7826*/ uint16(xArgXmm2M128), + /*7827*/ uint16(xMatch), + /*7828*/ uint16(xCondPrefix), 2, + 0x66, 7840, + 0x0, 7834, + /*7834*/ uint16(xSetOp), uint16(PMULUDQ), + /*7836*/ uint16(xReadSlashR), + /*7837*/ uint16(xArgMm1), + /*7838*/ uint16(xArgMm2M64), + /*7839*/ uint16(xMatch), + /*7840*/ uint16(xSetOp), uint16(PMULUDQ), + /*7842*/ uint16(xReadSlashR), + /*7843*/ uint16(xArgXmm1), + /*7844*/ uint16(xArgXmm2M128), + /*7845*/ uint16(xMatch), + /*7846*/ uint16(xCondPrefix), 2, + 0x66, 7858, + 0x0, 7852, + /*7852*/ uint16(xSetOp), uint16(PMADDWD), + /*7854*/ uint16(xReadSlashR), + /*7855*/ uint16(xArgMm), + /*7856*/ uint16(xArgMmM64), + /*7857*/ uint16(xMatch), + /*7858*/ uint16(xSetOp), uint16(PMADDWD), + /*7860*/ uint16(xReadSlashR), + /*7861*/ uint16(xArgXmm1), + /*7862*/ uint16(xArgXmm2M128), + /*7863*/ uint16(xMatch), + /*7864*/ uint16(xCondPrefix), 2, + 0x66, 7876, + 0x0, 7870, + /*7870*/ uint16(xSetOp), uint16(PSADBW), + /*7872*/ uint16(xReadSlashR), + /*7873*/ uint16(xArgMm1), + /*7874*/ uint16(xArgMm2M64), + /*7875*/ uint16(xMatch), + /*7876*/ uint16(xSetOp), uint16(PSADBW), + /*7878*/ uint16(xReadSlashR), + /*7879*/ uint16(xArgXmm1), + /*7880*/ uint16(xArgXmm2M128), + /*7881*/ uint16(xMatch), + /*7882*/ uint16(xCondPrefix), 2, + 0x66, 7894, + 0x0, 7888, + /*7888*/ uint16(xSetOp), uint16(MASKMOVQ), + /*7890*/ uint16(xReadSlashR), + /*7891*/ uint16(xArgMm1), + /*7892*/ uint16(xArgMm2), + /*7893*/ uint16(xMatch), + /*7894*/ uint16(xSetOp), uint16(MASKMOVDQU), + /*7896*/ uint16(xReadSlashR), + /*7897*/ uint16(xArgXmm1), + /*7898*/ uint16(xArgXmm2), + /*7899*/ uint16(xMatch), + /*7900*/ uint16(xCondPrefix), 2, + 0x66, 7912, + 0x0, 7906, + /*7906*/ uint16(xSetOp), uint16(PSUBB), + /*7908*/ uint16(xReadSlashR), + /*7909*/ uint16(xArgMm), + /*7910*/ uint16(xArgMmM64), + /*7911*/ uint16(xMatch), + /*7912*/ uint16(xSetOp), uint16(PSUBB), + /*7914*/ uint16(xReadSlashR), + /*7915*/ uint16(xArgXmm1), + /*7916*/ uint16(xArgXmm2M128), + /*7917*/ uint16(xMatch), + /*7918*/ uint16(xCondPrefix), 2, + 0x66, 7930, + 0x0, 7924, + /*7924*/ uint16(xSetOp), uint16(PSUBW), + /*7926*/ uint16(xReadSlashR), + /*7927*/ uint16(xArgMm), + /*7928*/ uint16(xArgMmM64), + /*7929*/ uint16(xMatch), + /*7930*/ uint16(xSetOp), uint16(PSUBW), + /*7932*/ uint16(xReadSlashR), + /*7933*/ uint16(xArgXmm1), + /*7934*/ uint16(xArgXmm2M128), + /*7935*/ uint16(xMatch), + /*7936*/ uint16(xCondPrefix), 2, + 0x66, 7948, + 0x0, 7942, + /*7942*/ uint16(xSetOp), uint16(PSUBD), + /*7944*/ uint16(xReadSlashR), + /*7945*/ uint16(xArgMm), + /*7946*/ uint16(xArgMmM64), + /*7947*/ uint16(xMatch), + /*7948*/ uint16(xSetOp), uint16(PSUBD), + /*7950*/ uint16(xReadSlashR), + /*7951*/ uint16(xArgXmm1), + /*7952*/ uint16(xArgXmm2M128), + /*7953*/ uint16(xMatch), + /*7954*/ uint16(xCondPrefix), 2, + 0x66, 7966, + 0x0, 7960, + /*7960*/ uint16(xSetOp), uint16(PSUBQ), + /*7962*/ uint16(xReadSlashR), + /*7963*/ uint16(xArgMm1), + /*7964*/ uint16(xArgMm2M64), + /*7965*/ uint16(xMatch), + /*7966*/ uint16(xSetOp), uint16(PSUBQ), + /*7968*/ uint16(xReadSlashR), + /*7969*/ uint16(xArgXmm1), + /*7970*/ uint16(xArgXmm2M128), + /*7971*/ uint16(xMatch), + /*7972*/ uint16(xCondPrefix), 2, + 0x66, 7984, + 0x0, 7978, + /*7978*/ uint16(xSetOp), uint16(PADDB), + /*7980*/ uint16(xReadSlashR), + /*7981*/ uint16(xArgMm), + /*7982*/ uint16(xArgMmM64), + /*7983*/ uint16(xMatch), + /*7984*/ uint16(xSetOp), uint16(PADDB), + /*7986*/ uint16(xReadSlashR), + /*7987*/ uint16(xArgXmm1), + /*7988*/ uint16(xArgXmm2M128), + /*7989*/ uint16(xMatch), + /*7990*/ uint16(xCondPrefix), 2, + 0x66, 8002, + 0x0, 7996, + /*7996*/ uint16(xSetOp), uint16(PADDW), + /*7998*/ uint16(xReadSlashR), + /*7999*/ uint16(xArgMm), + /*8000*/ uint16(xArgMmM64), + /*8001*/ uint16(xMatch), + /*8002*/ uint16(xSetOp), uint16(PADDW), + /*8004*/ uint16(xReadSlashR), + /*8005*/ uint16(xArgXmm1), + /*8006*/ uint16(xArgXmm2M128), + /*8007*/ uint16(xMatch), + /*8008*/ uint16(xCondPrefix), 2, + 0x66, 8020, + 0x0, 8014, + /*8014*/ uint16(xSetOp), uint16(PADDD), + /*8016*/ uint16(xReadSlashR), + /*8017*/ uint16(xArgMm), + /*8018*/ uint16(xArgMmM64), + /*8019*/ uint16(xMatch), + /*8020*/ uint16(xSetOp), uint16(PADDD), + /*8022*/ uint16(xReadSlashR), + /*8023*/ uint16(xArgXmm1), + /*8024*/ uint16(xArgXmm2M128), + /*8025*/ uint16(xMatch), + /*8026*/ uint16(xSetOp), uint16(ADC), + /*8028*/ uint16(xReadSlashR), + /*8029*/ uint16(xArgRM8), + /*8030*/ uint16(xArgR8), + /*8031*/ uint16(xMatch), + /*8032*/ uint16(xCondIs64), 8035, 8051, + /*8035*/ uint16(xCondDataSize), 8039, 8045, 0, + /*8039*/ uint16(xSetOp), uint16(ADC), + /*8041*/ uint16(xReadSlashR), + /*8042*/ uint16(xArgRM16), + /*8043*/ uint16(xArgR16), + /*8044*/ uint16(xMatch), + /*8045*/ uint16(xSetOp), uint16(ADC), + /*8047*/ uint16(xReadSlashR), + /*8048*/ uint16(xArgRM32), + /*8049*/ uint16(xArgR32), + /*8050*/ uint16(xMatch), + /*8051*/ uint16(xCondDataSize), 8039, 8045, 8055, + /*8055*/ uint16(xSetOp), uint16(ADC), + /*8057*/ uint16(xReadSlashR), + /*8058*/ uint16(xArgRM64), + /*8059*/ uint16(xArgR64), + /*8060*/ uint16(xMatch), + /*8061*/ uint16(xSetOp), uint16(ADC), + /*8063*/ uint16(xReadSlashR), + /*8064*/ uint16(xArgR8), + /*8065*/ uint16(xArgRM8), + /*8066*/ uint16(xMatch), + /*8067*/ uint16(xCondIs64), 8070, 8086, + /*8070*/ uint16(xCondDataSize), 8074, 8080, 0, + /*8074*/ uint16(xSetOp), uint16(ADC), + /*8076*/ uint16(xReadSlashR), + /*8077*/ uint16(xArgR16), + /*8078*/ uint16(xArgRM16), + /*8079*/ uint16(xMatch), + /*8080*/ uint16(xSetOp), uint16(ADC), + /*8082*/ uint16(xReadSlashR), + /*8083*/ uint16(xArgR32), + /*8084*/ uint16(xArgRM32), + /*8085*/ uint16(xMatch), + /*8086*/ uint16(xCondDataSize), 8074, 8080, 8090, + /*8090*/ uint16(xSetOp), uint16(ADC), + /*8092*/ uint16(xReadSlashR), + /*8093*/ uint16(xArgR64), + /*8094*/ uint16(xArgRM64), + /*8095*/ uint16(xMatch), + /*8096*/ uint16(xSetOp), uint16(ADC), + /*8098*/ uint16(xReadIb), + /*8099*/ uint16(xArgAL), + /*8100*/ uint16(xArgImm8u), + /*8101*/ uint16(xMatch), + /*8102*/ uint16(xCondIs64), 8105, 8121, + /*8105*/ uint16(xCondDataSize), 8109, 8115, 0, + /*8109*/ uint16(xSetOp), uint16(ADC), + /*8111*/ uint16(xReadIw), + /*8112*/ uint16(xArgAX), + /*8113*/ uint16(xArgImm16), + /*8114*/ uint16(xMatch), + /*8115*/ uint16(xSetOp), uint16(ADC), + /*8117*/ uint16(xReadId), + /*8118*/ uint16(xArgEAX), + /*8119*/ uint16(xArgImm32), + /*8120*/ uint16(xMatch), + /*8121*/ uint16(xCondDataSize), 8109, 8115, 8125, + /*8125*/ uint16(xSetOp), uint16(ADC), + /*8127*/ uint16(xReadId), + /*8128*/ uint16(xArgRAX), + /*8129*/ uint16(xArgImm32), + /*8130*/ uint16(xMatch), + /*8131*/ uint16(xCondIs64), 8134, 0, + /*8134*/ uint16(xSetOp), uint16(PUSH), + /*8136*/ uint16(xArgSS), + /*8137*/ uint16(xMatch), + /*8138*/ uint16(xCondIs64), 8141, 0, + /*8141*/ uint16(xSetOp), uint16(POP), + /*8143*/ uint16(xArgSS), + /*8144*/ uint16(xMatch), + /*8145*/ uint16(xSetOp), uint16(SBB), + /*8147*/ uint16(xReadSlashR), + /*8148*/ uint16(xArgRM8), + /*8149*/ uint16(xArgR8), + /*8150*/ uint16(xMatch), + /*8151*/ uint16(xCondIs64), 8154, 8170, + /*8154*/ uint16(xCondDataSize), 8158, 8164, 0, + /*8158*/ uint16(xSetOp), uint16(SBB), + /*8160*/ uint16(xReadSlashR), + /*8161*/ uint16(xArgRM16), + /*8162*/ uint16(xArgR16), + /*8163*/ uint16(xMatch), + /*8164*/ uint16(xSetOp), uint16(SBB), + /*8166*/ uint16(xReadSlashR), + /*8167*/ uint16(xArgRM32), + /*8168*/ uint16(xArgR32), + /*8169*/ uint16(xMatch), + /*8170*/ uint16(xCondDataSize), 8158, 8164, 8174, + /*8174*/ uint16(xSetOp), uint16(SBB), + /*8176*/ uint16(xReadSlashR), + /*8177*/ uint16(xArgRM64), + /*8178*/ uint16(xArgR64), + /*8179*/ uint16(xMatch), + /*8180*/ uint16(xSetOp), uint16(SBB), + /*8182*/ uint16(xReadSlashR), + /*8183*/ uint16(xArgR8), + /*8184*/ uint16(xArgRM8), + /*8185*/ uint16(xMatch), + /*8186*/ uint16(xCondIs64), 8189, 8205, + /*8189*/ uint16(xCondDataSize), 8193, 8199, 0, + /*8193*/ uint16(xSetOp), uint16(SBB), + /*8195*/ uint16(xReadSlashR), + /*8196*/ uint16(xArgR16), + /*8197*/ uint16(xArgRM16), + /*8198*/ uint16(xMatch), + /*8199*/ uint16(xSetOp), uint16(SBB), + /*8201*/ uint16(xReadSlashR), + /*8202*/ uint16(xArgR32), + /*8203*/ uint16(xArgRM32), + /*8204*/ uint16(xMatch), + /*8205*/ uint16(xCondDataSize), 8193, 8199, 8209, + /*8209*/ uint16(xSetOp), uint16(SBB), + /*8211*/ uint16(xReadSlashR), + /*8212*/ uint16(xArgR64), + /*8213*/ uint16(xArgRM64), + /*8214*/ uint16(xMatch), + /*8215*/ uint16(xSetOp), uint16(SBB), + /*8217*/ uint16(xReadIb), + /*8218*/ uint16(xArgAL), + /*8219*/ uint16(xArgImm8u), + /*8220*/ uint16(xMatch), + /*8221*/ uint16(xCondIs64), 8224, 8240, + /*8224*/ uint16(xCondDataSize), 8228, 8234, 0, + /*8228*/ uint16(xSetOp), uint16(SBB), + /*8230*/ uint16(xReadIw), + /*8231*/ uint16(xArgAX), + /*8232*/ uint16(xArgImm16), + /*8233*/ uint16(xMatch), + /*8234*/ uint16(xSetOp), uint16(SBB), + /*8236*/ uint16(xReadId), + /*8237*/ uint16(xArgEAX), + /*8238*/ uint16(xArgImm32), + /*8239*/ uint16(xMatch), + /*8240*/ uint16(xCondDataSize), 8228, 8234, 8244, + /*8244*/ uint16(xSetOp), uint16(SBB), + /*8246*/ uint16(xReadId), + /*8247*/ uint16(xArgRAX), + /*8248*/ uint16(xArgImm32), + /*8249*/ uint16(xMatch), + /*8250*/ uint16(xCondIs64), 8253, 0, + /*8253*/ uint16(xSetOp), uint16(PUSH), + /*8255*/ uint16(xArgDS), + /*8256*/ uint16(xMatch), + /*8257*/ uint16(xCondIs64), 8260, 0, + /*8260*/ uint16(xSetOp), uint16(POP), + /*8262*/ uint16(xArgDS), + /*8263*/ uint16(xMatch), + /*8264*/ uint16(xSetOp), uint16(AND), + /*8266*/ uint16(xReadSlashR), + /*8267*/ uint16(xArgRM8), + /*8268*/ uint16(xArgR8), + /*8269*/ uint16(xMatch), + /*8270*/ uint16(xCondIs64), 8273, 8289, + /*8273*/ uint16(xCondDataSize), 8277, 8283, 0, + /*8277*/ uint16(xSetOp), uint16(AND), + /*8279*/ uint16(xReadSlashR), + /*8280*/ uint16(xArgRM16), + /*8281*/ uint16(xArgR16), + /*8282*/ uint16(xMatch), + /*8283*/ uint16(xSetOp), uint16(AND), + /*8285*/ uint16(xReadSlashR), + /*8286*/ uint16(xArgRM32), + /*8287*/ uint16(xArgR32), + /*8288*/ uint16(xMatch), + /*8289*/ uint16(xCondDataSize), 8277, 8283, 8293, + /*8293*/ uint16(xSetOp), uint16(AND), + /*8295*/ uint16(xReadSlashR), + /*8296*/ uint16(xArgRM64), + /*8297*/ uint16(xArgR64), + /*8298*/ uint16(xMatch), + /*8299*/ uint16(xSetOp), uint16(AND), + /*8301*/ uint16(xReadSlashR), + /*8302*/ uint16(xArgR8), + /*8303*/ uint16(xArgRM8), + /*8304*/ uint16(xMatch), + /*8305*/ uint16(xCondIs64), 8308, 8324, + /*8308*/ uint16(xCondDataSize), 8312, 8318, 0, + /*8312*/ uint16(xSetOp), uint16(AND), + /*8314*/ uint16(xReadSlashR), + /*8315*/ uint16(xArgR16), + /*8316*/ uint16(xArgRM16), + /*8317*/ uint16(xMatch), + /*8318*/ uint16(xSetOp), uint16(AND), + /*8320*/ uint16(xReadSlashR), + /*8321*/ uint16(xArgR32), + /*8322*/ uint16(xArgRM32), + /*8323*/ uint16(xMatch), + /*8324*/ uint16(xCondDataSize), 8312, 8318, 8328, + /*8328*/ uint16(xSetOp), uint16(AND), + /*8330*/ uint16(xReadSlashR), + /*8331*/ uint16(xArgR64), + /*8332*/ uint16(xArgRM64), + /*8333*/ uint16(xMatch), + /*8334*/ uint16(xSetOp), uint16(AND), + /*8336*/ uint16(xReadIb), + /*8337*/ uint16(xArgAL), + /*8338*/ uint16(xArgImm8u), + /*8339*/ uint16(xMatch), + /*8340*/ uint16(xCondIs64), 8343, 8359, + /*8343*/ uint16(xCondDataSize), 8347, 8353, 0, + /*8347*/ uint16(xSetOp), uint16(AND), + /*8349*/ uint16(xReadIw), + /*8350*/ uint16(xArgAX), + /*8351*/ uint16(xArgImm16), + /*8352*/ uint16(xMatch), + /*8353*/ uint16(xSetOp), uint16(AND), + /*8355*/ uint16(xReadId), + /*8356*/ uint16(xArgEAX), + /*8357*/ uint16(xArgImm32), + /*8358*/ uint16(xMatch), + /*8359*/ uint16(xCondDataSize), 8347, 8353, 8363, + /*8363*/ uint16(xSetOp), uint16(AND), + /*8365*/ uint16(xReadId), + /*8366*/ uint16(xArgRAX), + /*8367*/ uint16(xArgImm32), + /*8368*/ uint16(xMatch), + /*8369*/ uint16(xCondIs64), 8372, 0, + /*8372*/ uint16(xSetOp), uint16(DAA), + /*8374*/ uint16(xMatch), + /*8375*/ uint16(xSetOp), uint16(SUB), + /*8377*/ uint16(xReadSlashR), + /*8378*/ uint16(xArgRM8), + /*8379*/ uint16(xArgR8), + /*8380*/ uint16(xMatch), + /*8381*/ uint16(xCondIs64), 8384, 8400, + /*8384*/ uint16(xCondDataSize), 8388, 8394, 0, + /*8388*/ uint16(xSetOp), uint16(SUB), + /*8390*/ uint16(xReadSlashR), + /*8391*/ uint16(xArgRM16), + /*8392*/ uint16(xArgR16), + /*8393*/ uint16(xMatch), + /*8394*/ uint16(xSetOp), uint16(SUB), + /*8396*/ uint16(xReadSlashR), + /*8397*/ uint16(xArgRM32), + /*8398*/ uint16(xArgR32), + /*8399*/ uint16(xMatch), + /*8400*/ uint16(xCondDataSize), 8388, 8394, 8404, + /*8404*/ uint16(xSetOp), uint16(SUB), + /*8406*/ uint16(xReadSlashR), + /*8407*/ uint16(xArgRM64), + /*8408*/ uint16(xArgR64), + /*8409*/ uint16(xMatch), + /*8410*/ uint16(xCondPrefix), 3, + 0xC5, 8438, + 0xC4, 8424, + 0x0, 8418, + /*8418*/ uint16(xSetOp), uint16(SUB), + /*8420*/ uint16(xReadSlashR), + /*8421*/ uint16(xArgR8), + /*8422*/ uint16(xArgRM8), + /*8423*/ uint16(xMatch), + /*8424*/ uint16(xCondPrefix), 1, + 0x66, 8428, + /*8428*/ uint16(xCondPrefix), 1, + 0x0F38, 8432, + /*8432*/ uint16(xSetOp), uint16(VMOVNTDQA), + /*8434*/ uint16(xReadSlashR), + /*8435*/ uint16(xArgYmm1), + /*8436*/ uint16(xArgM256), + /*8437*/ uint16(xMatch), + /*8438*/ uint16(xCondPrefix), 1, + 0x66, 8442, + /*8442*/ uint16(xCondPrefix), 1, + 0x0F38, 8446, + /*8446*/ uint16(xSetOp), uint16(VMOVNTDQA), + /*8448*/ uint16(xReadSlashR), + /*8449*/ uint16(xArgYmm1), + /*8450*/ uint16(xArgM256), + /*8451*/ uint16(xMatch), + /*8452*/ uint16(xCondIs64), 8455, 8471, + /*8455*/ uint16(xCondDataSize), 8459, 8465, 0, + /*8459*/ uint16(xSetOp), uint16(SUB), + /*8461*/ uint16(xReadSlashR), + /*8462*/ uint16(xArgR16), + /*8463*/ uint16(xArgRM16), + /*8464*/ uint16(xMatch), + /*8465*/ uint16(xSetOp), uint16(SUB), + /*8467*/ uint16(xReadSlashR), + /*8468*/ uint16(xArgR32), + /*8469*/ uint16(xArgRM32), + /*8470*/ uint16(xMatch), + /*8471*/ uint16(xCondDataSize), 8459, 8465, 8475, + /*8475*/ uint16(xSetOp), uint16(SUB), + /*8477*/ uint16(xReadSlashR), + /*8478*/ uint16(xArgR64), + /*8479*/ uint16(xArgRM64), + /*8480*/ uint16(xMatch), + /*8481*/ uint16(xSetOp), uint16(SUB), + /*8483*/ uint16(xReadIb), + /*8484*/ uint16(xArgAL), + /*8485*/ uint16(xArgImm8u), + /*8486*/ uint16(xMatch), + /*8487*/ uint16(xCondIs64), 8490, 8506, + /*8490*/ uint16(xCondDataSize), 8494, 8500, 0, + /*8494*/ uint16(xSetOp), uint16(SUB), + /*8496*/ uint16(xReadIw), + /*8497*/ uint16(xArgAX), + /*8498*/ uint16(xArgImm16), + /*8499*/ uint16(xMatch), + /*8500*/ uint16(xSetOp), uint16(SUB), + /*8502*/ uint16(xReadId), + /*8503*/ uint16(xArgEAX), + /*8504*/ uint16(xArgImm32), + /*8505*/ uint16(xMatch), + /*8506*/ uint16(xCondDataSize), 8494, 8500, 8510, + /*8510*/ uint16(xSetOp), uint16(SUB), + /*8512*/ uint16(xReadId), + /*8513*/ uint16(xArgRAX), + /*8514*/ uint16(xArgImm32), + /*8515*/ uint16(xMatch), + /*8516*/ uint16(xCondIs64), 8519, 0, + /*8519*/ uint16(xSetOp), uint16(DAS), + /*8521*/ uint16(xMatch), + /*8522*/ uint16(xSetOp), uint16(XOR), + /*8524*/ uint16(xReadSlashR), + /*8525*/ uint16(xArgRM8), + /*8526*/ uint16(xArgR8), + /*8527*/ uint16(xMatch), + /*8528*/ uint16(xCondIs64), 8531, 8547, + /*8531*/ uint16(xCondDataSize), 8535, 8541, 0, + /*8535*/ uint16(xSetOp), uint16(XOR), + /*8537*/ uint16(xReadSlashR), + /*8538*/ uint16(xArgRM16), + /*8539*/ uint16(xArgR16), + /*8540*/ uint16(xMatch), + /*8541*/ uint16(xSetOp), uint16(XOR), + /*8543*/ uint16(xReadSlashR), + /*8544*/ uint16(xArgRM32), + /*8545*/ uint16(xArgR32), + /*8546*/ uint16(xMatch), + /*8547*/ uint16(xCondDataSize), 8535, 8541, 8551, + /*8551*/ uint16(xSetOp), uint16(XOR), + /*8553*/ uint16(xReadSlashR), + /*8554*/ uint16(xArgRM64), + /*8555*/ uint16(xArgR64), + /*8556*/ uint16(xMatch), + /*8557*/ uint16(xSetOp), uint16(XOR), + /*8559*/ uint16(xReadSlashR), + /*8560*/ uint16(xArgR8), + /*8561*/ uint16(xArgRM8), + /*8562*/ uint16(xMatch), + /*8563*/ uint16(xCondIs64), 8566, 8582, + /*8566*/ uint16(xCondDataSize), 8570, 8576, 0, + /*8570*/ uint16(xSetOp), uint16(XOR), + /*8572*/ uint16(xReadSlashR), + /*8573*/ uint16(xArgR16), + /*8574*/ uint16(xArgRM16), + /*8575*/ uint16(xMatch), + /*8576*/ uint16(xSetOp), uint16(XOR), + /*8578*/ uint16(xReadSlashR), + /*8579*/ uint16(xArgR32), + /*8580*/ uint16(xArgRM32), + /*8581*/ uint16(xMatch), + /*8582*/ uint16(xCondDataSize), 8570, 8576, 8586, + /*8586*/ uint16(xSetOp), uint16(XOR), + /*8588*/ uint16(xReadSlashR), + /*8589*/ uint16(xArgR64), + /*8590*/ uint16(xArgRM64), + /*8591*/ uint16(xMatch), + /*8592*/ uint16(xSetOp), uint16(XOR), + /*8594*/ uint16(xReadIb), + /*8595*/ uint16(xArgAL), + /*8596*/ uint16(xArgImm8u), + /*8597*/ uint16(xMatch), + /*8598*/ uint16(xCondIs64), 8601, 8617, + /*8601*/ uint16(xCondDataSize), 8605, 8611, 0, + /*8605*/ uint16(xSetOp), uint16(XOR), + /*8607*/ uint16(xReadIw), + /*8608*/ uint16(xArgAX), + /*8609*/ uint16(xArgImm16), + /*8610*/ uint16(xMatch), + /*8611*/ uint16(xSetOp), uint16(XOR), + /*8613*/ uint16(xReadId), + /*8614*/ uint16(xArgEAX), + /*8615*/ uint16(xArgImm32), + /*8616*/ uint16(xMatch), + /*8617*/ uint16(xCondDataSize), 8605, 8611, 8621, + /*8621*/ uint16(xSetOp), uint16(XOR), + /*8623*/ uint16(xReadId), + /*8624*/ uint16(xArgRAX), + /*8625*/ uint16(xArgImm32), + /*8626*/ uint16(xMatch), + /*8627*/ uint16(xCondIs64), 8630, 0, + /*8630*/ uint16(xSetOp), uint16(AAA), + /*8632*/ uint16(xMatch), + /*8633*/ uint16(xSetOp), uint16(CMP), + /*8635*/ uint16(xReadSlashR), + /*8636*/ uint16(xArgRM8), + /*8637*/ uint16(xArgR8), + /*8638*/ uint16(xMatch), + /*8639*/ uint16(xCondIs64), 8642, 8658, + /*8642*/ uint16(xCondDataSize), 8646, 8652, 0, + /*8646*/ uint16(xSetOp), uint16(CMP), + /*8648*/ uint16(xReadSlashR), + /*8649*/ uint16(xArgRM16), + /*8650*/ uint16(xArgR16), + /*8651*/ uint16(xMatch), + /*8652*/ uint16(xSetOp), uint16(CMP), + /*8654*/ uint16(xReadSlashR), + /*8655*/ uint16(xArgRM32), + /*8656*/ uint16(xArgR32), + /*8657*/ uint16(xMatch), + /*8658*/ uint16(xCondDataSize), 8646, 8652, 8662, + /*8662*/ uint16(xSetOp), uint16(CMP), + /*8664*/ uint16(xReadSlashR), + /*8665*/ uint16(xArgRM64), + /*8666*/ uint16(xArgR64), + /*8667*/ uint16(xMatch), + /*8668*/ uint16(xSetOp), uint16(CMP), + /*8670*/ uint16(xReadSlashR), + /*8671*/ uint16(xArgR8), + /*8672*/ uint16(xArgRM8), + /*8673*/ uint16(xMatch), + /*8674*/ uint16(xCondIs64), 8677, 8693, + /*8677*/ uint16(xCondDataSize), 8681, 8687, 0, + /*8681*/ uint16(xSetOp), uint16(CMP), + /*8683*/ uint16(xReadSlashR), + /*8684*/ uint16(xArgR16), + /*8685*/ uint16(xArgRM16), + /*8686*/ uint16(xMatch), + /*8687*/ uint16(xSetOp), uint16(CMP), + /*8689*/ uint16(xReadSlashR), + /*8690*/ uint16(xArgR32), + /*8691*/ uint16(xArgRM32), + /*8692*/ uint16(xMatch), + /*8693*/ uint16(xCondDataSize), 8681, 8687, 8697, + /*8697*/ uint16(xSetOp), uint16(CMP), + /*8699*/ uint16(xReadSlashR), + /*8700*/ uint16(xArgR64), + /*8701*/ uint16(xArgRM64), + /*8702*/ uint16(xMatch), + /*8703*/ uint16(xSetOp), uint16(CMP), + /*8705*/ uint16(xReadIb), + /*8706*/ uint16(xArgAL), + /*8707*/ uint16(xArgImm8u), + /*8708*/ uint16(xMatch), + /*8709*/ uint16(xCondIs64), 8712, 8728, + /*8712*/ uint16(xCondDataSize), 8716, 8722, 0, + /*8716*/ uint16(xSetOp), uint16(CMP), + /*8718*/ uint16(xReadIw), + /*8719*/ uint16(xArgAX), + /*8720*/ uint16(xArgImm16), + /*8721*/ uint16(xMatch), + /*8722*/ uint16(xSetOp), uint16(CMP), + /*8724*/ uint16(xReadId), + /*8725*/ uint16(xArgEAX), + /*8726*/ uint16(xArgImm32), + /*8727*/ uint16(xMatch), + /*8728*/ uint16(xCondDataSize), 8716, 8722, 8732, + /*8732*/ uint16(xSetOp), uint16(CMP), + /*8734*/ uint16(xReadId), + /*8735*/ uint16(xArgRAX), + /*8736*/ uint16(xArgImm32), + /*8737*/ uint16(xMatch), + /*8738*/ uint16(xCondIs64), 8741, 0, + /*8741*/ uint16(xSetOp), uint16(AAS), + /*8743*/ uint16(xMatch), + /*8744*/ uint16(xCondIs64), 8747, 0, + /*8747*/ uint16(xCondDataSize), 8751, 8755, 0, + /*8751*/ uint16(xSetOp), uint16(INC), + /*8753*/ uint16(xArgR16op), + /*8754*/ uint16(xMatch), + /*8755*/ uint16(xSetOp), uint16(INC), + /*8757*/ uint16(xArgR32op), + /*8758*/ uint16(xMatch), + /*8759*/ uint16(xCondIs64), 8762, 0, + /*8762*/ uint16(xCondDataSize), 8766, 8770, 0, + /*8766*/ uint16(xSetOp), uint16(DEC), + /*8768*/ uint16(xArgR16op), + /*8769*/ uint16(xMatch), + /*8770*/ uint16(xSetOp), uint16(DEC), + /*8772*/ uint16(xArgR32op), + /*8773*/ uint16(xMatch), + /*8774*/ uint16(xCondIs64), 8777, 8789, + /*8777*/ uint16(xCondDataSize), 8781, 8785, 0, + /*8781*/ uint16(xSetOp), uint16(PUSH), + /*8783*/ uint16(xArgR16op), + /*8784*/ uint16(xMatch), + /*8785*/ uint16(xSetOp), uint16(PUSH), + /*8787*/ uint16(xArgR32op), + /*8788*/ uint16(xMatch), + /*8789*/ uint16(xCondDataSize), 8781, 8793, 8797, + /*8793*/ uint16(xSetOp), uint16(PUSH), + /*8795*/ uint16(xArgR64op), + /*8796*/ uint16(xMatch), + /*8797*/ uint16(xSetOp), uint16(PUSH), + /*8799*/ uint16(xArgR64op), + /*8800*/ uint16(xMatch), + /*8801*/ uint16(xCondIs64), 8804, 8816, + /*8804*/ uint16(xCondDataSize), 8808, 8812, 0, + /*8808*/ uint16(xSetOp), uint16(POP), + /*8810*/ uint16(xArgR16op), + /*8811*/ uint16(xMatch), + /*8812*/ uint16(xSetOp), uint16(POP), + /*8814*/ uint16(xArgR32op), + /*8815*/ uint16(xMatch), + /*8816*/ uint16(xCondDataSize), 8808, 8820, 8824, + /*8820*/ uint16(xSetOp), uint16(POP), + /*8822*/ uint16(xArgR64op), + /*8823*/ uint16(xMatch), + /*8824*/ uint16(xSetOp), uint16(POP), + /*8826*/ uint16(xArgR64op), + /*8827*/ uint16(xMatch), + /*8828*/ uint16(xCondIs64), 8831, 0, + /*8831*/ uint16(xCondDataSize), 8835, 8838, 0, + /*8835*/ uint16(xSetOp), uint16(PUSHA), + /*8837*/ uint16(xMatch), + /*8838*/ uint16(xSetOp), uint16(PUSHAD), + /*8840*/ uint16(xMatch), + /*8841*/ uint16(xCondIs64), 8844, 0, + /*8844*/ uint16(xCondDataSize), 8848, 8851, 0, + /*8848*/ uint16(xSetOp), uint16(POPA), + /*8850*/ uint16(xMatch), + /*8851*/ uint16(xSetOp), uint16(POPAD), + /*8853*/ uint16(xMatch), + /*8854*/ uint16(xCondIs64), 8857, 0, + /*8857*/ uint16(xCondDataSize), 8861, 8867, 0, + /*8861*/ uint16(xSetOp), uint16(BOUND), + /*8863*/ uint16(xReadSlashR), + /*8864*/ uint16(xArgR16), + /*8865*/ uint16(xArgM16and16), + /*8866*/ uint16(xMatch), + /*8867*/ uint16(xSetOp), uint16(BOUND), + /*8869*/ uint16(xReadSlashR), + /*8870*/ uint16(xArgR32), + /*8871*/ uint16(xArgM32and32), + /*8872*/ uint16(xMatch), + /*8873*/ uint16(xCondIs64), 8876, 8882, + /*8876*/ uint16(xSetOp), uint16(ARPL), + /*8878*/ uint16(xReadSlashR), + /*8879*/ uint16(xArgRM16), + /*8880*/ uint16(xArgR16), + /*8881*/ uint16(xMatch), + /*8882*/ uint16(xCondDataSize), 8886, 8892, 8898, + /*8886*/ uint16(xSetOp), uint16(MOVSXD), + /*8888*/ uint16(xReadSlashR), + /*8889*/ uint16(xArgR16), + /*8890*/ uint16(xArgRM32), + /*8891*/ uint16(xMatch), + /*8892*/ uint16(xSetOp), uint16(MOVSXD), + /*8894*/ uint16(xReadSlashR), + /*8895*/ uint16(xArgR32), + /*8896*/ uint16(xArgRM32), + /*8897*/ uint16(xMatch), + /*8898*/ uint16(xSetOp), uint16(MOVSXD), + /*8900*/ uint16(xReadSlashR), + /*8901*/ uint16(xArgR64), + /*8902*/ uint16(xArgRM32), + /*8903*/ uint16(xMatch), + /*8904*/ uint16(xCondDataSize), 8908, 8913, 8918, + /*8908*/ uint16(xSetOp), uint16(PUSH), + /*8910*/ uint16(xReadIw), + /*8911*/ uint16(xArgImm16), + /*8912*/ uint16(xMatch), + /*8913*/ uint16(xSetOp), uint16(PUSH), + /*8915*/ uint16(xReadId), + /*8916*/ uint16(xArgImm32), + /*8917*/ uint16(xMatch), + /*8918*/ uint16(xSetOp), uint16(PUSH), + /*8920*/ uint16(xReadId), + /*8921*/ uint16(xArgImm32), + /*8922*/ uint16(xMatch), + /*8923*/ uint16(xCondIs64), 8926, 8946, + /*8926*/ uint16(xCondDataSize), 8930, 8938, 0, + /*8930*/ uint16(xSetOp), uint16(IMUL), + /*8932*/ uint16(xReadSlashR), + /*8933*/ uint16(xReadIw), + /*8934*/ uint16(xArgR16), + /*8935*/ uint16(xArgRM16), + /*8936*/ uint16(xArgImm16), + /*8937*/ uint16(xMatch), + /*8938*/ uint16(xSetOp), uint16(IMUL), + /*8940*/ uint16(xReadSlashR), + /*8941*/ uint16(xReadId), + /*8942*/ uint16(xArgR32), + /*8943*/ uint16(xArgRM32), + /*8944*/ uint16(xArgImm32), + /*8945*/ uint16(xMatch), + /*8946*/ uint16(xCondDataSize), 8930, 8938, 8950, + /*8950*/ uint16(xSetOp), uint16(IMUL), + /*8952*/ uint16(xReadSlashR), + /*8953*/ uint16(xReadId), + /*8954*/ uint16(xArgR64), + /*8955*/ uint16(xArgRM64), + /*8956*/ uint16(xArgImm32), + /*8957*/ uint16(xMatch), + /*8958*/ uint16(xSetOp), uint16(PUSH), + /*8960*/ uint16(xReadIb), + /*8961*/ uint16(xArgImm8), + /*8962*/ uint16(xMatch), + /*8963*/ uint16(xCondIs64), 8966, 8986, + /*8966*/ uint16(xCondDataSize), 8970, 8978, 0, + /*8970*/ uint16(xSetOp), uint16(IMUL), + /*8972*/ uint16(xReadSlashR), + /*8973*/ uint16(xReadIb), + /*8974*/ uint16(xArgR16), + /*8975*/ uint16(xArgRM16), + /*8976*/ uint16(xArgImm8), + /*8977*/ uint16(xMatch), + /*8978*/ uint16(xSetOp), uint16(IMUL), + /*8980*/ uint16(xReadSlashR), + /*8981*/ uint16(xReadIb), + /*8982*/ uint16(xArgR32), + /*8983*/ uint16(xArgRM32), + /*8984*/ uint16(xArgImm8), + /*8985*/ uint16(xMatch), + /*8986*/ uint16(xCondDataSize), 8970, 8978, 8990, + /*8990*/ uint16(xSetOp), uint16(IMUL), + /*8992*/ uint16(xReadSlashR), + /*8993*/ uint16(xReadIb), + /*8994*/ uint16(xArgR64), + /*8995*/ uint16(xArgRM64), + /*8996*/ uint16(xArgImm8), + /*8997*/ uint16(xMatch), + /*8998*/ uint16(xSetOp), uint16(INSB), + /*9000*/ uint16(xMatch), + /*9001*/ uint16(xCondDataSize), 9005, 9008, 9011, + /*9005*/ uint16(xSetOp), uint16(INSW), + /*9007*/ uint16(xMatch), + /*9008*/ uint16(xSetOp), uint16(INSD), + /*9010*/ uint16(xMatch), + /*9011*/ uint16(xSetOp), uint16(INSD), + /*9013*/ uint16(xMatch), + /*9014*/ uint16(xSetOp), uint16(OUTSB), + /*9016*/ uint16(xMatch), + /*9017*/ uint16(xCondPrefix), 3, + 0xC5, 9064, + 0xC4, 9038, + 0x0, 9025, + /*9025*/ uint16(xCondDataSize), 9029, 9032, 9035, + /*9029*/ uint16(xSetOp), uint16(OUTSW), + /*9031*/ uint16(xMatch), + /*9032*/ uint16(xSetOp), uint16(OUTSD), + /*9034*/ uint16(xMatch), + /*9035*/ uint16(xSetOp), uint16(OUTSD), + /*9037*/ uint16(xMatch), + /*9038*/ uint16(xCondPrefix), 2, + 0xF3, 9054, + 0x66, 9044, + /*9044*/ uint16(xCondPrefix), 1, + 0x0F, 9048, + /*9048*/ uint16(xSetOp), uint16(VMOVDQA), + /*9050*/ uint16(xReadSlashR), + /*9051*/ uint16(xArgYmm1), + /*9052*/ uint16(xArgYmm2M256), + /*9053*/ uint16(xMatch), + /*9054*/ uint16(xCondPrefix), 1, + 0x0F, 9058, + /*9058*/ uint16(xSetOp), uint16(VMOVDQU), + /*9060*/ uint16(xReadSlashR), + /*9061*/ uint16(xArgYmm1), + /*9062*/ uint16(xArgYmm2M256), + /*9063*/ uint16(xMatch), + /*9064*/ uint16(xCondPrefix), 2, + 0xF3, 9080, + 0x66, 9070, + /*9070*/ uint16(xCondPrefix), 1, + 0x0F, 9074, + /*9074*/ uint16(xSetOp), uint16(VMOVDQA), + /*9076*/ uint16(xReadSlashR), + /*9077*/ uint16(xArgYmm1), + /*9078*/ uint16(xArgYmm2M256), + /*9079*/ uint16(xMatch), + /*9080*/ uint16(xCondPrefix), 1, + 0x0F, 9084, + /*9084*/ uint16(xSetOp), uint16(VMOVDQU), + /*9086*/ uint16(xReadSlashR), + /*9087*/ uint16(xArgYmm1), + /*9088*/ uint16(xArgYmm2M256), + /*9089*/ uint16(xMatch), + /*9090*/ uint16(xSetOp), uint16(JO), + /*9092*/ uint16(xReadCb), + /*9093*/ uint16(xArgRel8), + /*9094*/ uint16(xMatch), + /*9095*/ uint16(xSetOp), uint16(JNO), + /*9097*/ uint16(xReadCb), + /*9098*/ uint16(xArgRel8), + /*9099*/ uint16(xMatch), + /*9100*/ uint16(xSetOp), uint16(JB), + /*9102*/ uint16(xReadCb), + /*9103*/ uint16(xArgRel8), + /*9104*/ uint16(xMatch), + /*9105*/ uint16(xSetOp), uint16(JAE), + /*9107*/ uint16(xReadCb), + /*9108*/ uint16(xArgRel8), + /*9109*/ uint16(xMatch), + /*9110*/ uint16(xSetOp), uint16(JE), + /*9112*/ uint16(xReadCb), + /*9113*/ uint16(xArgRel8), + /*9114*/ uint16(xMatch), + /*9115*/ uint16(xSetOp), uint16(JNE), + /*9117*/ uint16(xReadCb), + /*9118*/ uint16(xArgRel8), + /*9119*/ uint16(xMatch), + /*9120*/ uint16(xSetOp), uint16(JBE), + /*9122*/ uint16(xReadCb), + /*9123*/ uint16(xArgRel8), + /*9124*/ uint16(xMatch), + /*9125*/ uint16(xCondPrefix), 3, + 0xC5, 9145, + 0xC4, 9138, + 0x0, 9133, + /*9133*/ uint16(xSetOp), uint16(JA), + /*9135*/ uint16(xReadCb), + /*9136*/ uint16(xArgRel8), + /*9137*/ uint16(xMatch), + /*9138*/ uint16(xCondPrefix), 1, + 0x0F, 9142, + /*9142*/ uint16(xSetOp), uint16(VZEROUPPER), + /*9144*/ uint16(xMatch), + /*9145*/ uint16(xCondPrefix), 1, + 0x0F, 9149, + /*9149*/ uint16(xSetOp), uint16(VZEROUPPER), + /*9151*/ uint16(xMatch), + /*9152*/ uint16(xSetOp), uint16(JS), + /*9154*/ uint16(xReadCb), + /*9155*/ uint16(xArgRel8), + /*9156*/ uint16(xMatch), + /*9157*/ uint16(xSetOp), uint16(JNS), + /*9159*/ uint16(xReadCb), + /*9160*/ uint16(xArgRel8), + /*9161*/ uint16(xMatch), + /*9162*/ uint16(xSetOp), uint16(JP), + /*9164*/ uint16(xReadCb), + /*9165*/ uint16(xArgRel8), + /*9166*/ uint16(xMatch), + /*9167*/ uint16(xSetOp), uint16(JNP), + /*9169*/ uint16(xReadCb), + /*9170*/ uint16(xArgRel8), + /*9171*/ uint16(xMatch), + /*9172*/ uint16(xSetOp), uint16(JL), + /*9174*/ uint16(xReadCb), + /*9175*/ uint16(xArgRel8), + /*9176*/ uint16(xMatch), + /*9177*/ uint16(xSetOp), uint16(JGE), + /*9179*/ uint16(xReadCb), + /*9180*/ uint16(xArgRel8), + /*9181*/ uint16(xMatch), + /*9182*/ uint16(xSetOp), uint16(JLE), + /*9184*/ uint16(xReadCb), + /*9185*/ uint16(xArgRel8), + /*9186*/ uint16(xMatch), + /*9187*/ uint16(xCondPrefix), 3, + 0xC5, 9226, + 0xC4, 9200, + 0x0, 9195, + /*9195*/ uint16(xSetOp), uint16(JG), + /*9197*/ uint16(xReadCb), + /*9198*/ uint16(xArgRel8), + /*9199*/ uint16(xMatch), + /*9200*/ uint16(xCondPrefix), 2, + 0xF3, 9216, + 0x66, 9206, + /*9206*/ uint16(xCondPrefix), 1, + 0x0F, 9210, + /*9210*/ uint16(xSetOp), uint16(VMOVDQA), + /*9212*/ uint16(xReadSlashR), + /*9213*/ uint16(xArgYmm2M256), + /*9214*/ uint16(xArgYmm1), + /*9215*/ uint16(xMatch), + /*9216*/ uint16(xCondPrefix), 1, + 0x0F, 9220, + /*9220*/ uint16(xSetOp), uint16(VMOVDQU), + /*9222*/ uint16(xReadSlashR), + /*9223*/ uint16(xArgYmm2M256), + /*9224*/ uint16(xArgYmm1), + /*9225*/ uint16(xMatch), + /*9226*/ uint16(xCondPrefix), 2, + 0xF3, 9242, + 0x66, 9232, + /*9232*/ uint16(xCondPrefix), 1, + 0x0F, 9236, + /*9236*/ uint16(xSetOp), uint16(VMOVDQA), + /*9238*/ uint16(xReadSlashR), + /*9239*/ uint16(xArgYmm2M256), + /*9240*/ uint16(xArgYmm1), + /*9241*/ uint16(xMatch), + /*9242*/ uint16(xCondPrefix), 1, + 0x0F, 9246, + /*9246*/ uint16(xSetOp), uint16(VMOVDQU), + /*9248*/ uint16(xReadSlashR), + /*9249*/ uint16(xArgYmm2M256), + /*9250*/ uint16(xArgYmm1), + /*9251*/ uint16(xMatch), + /*9252*/ uint16(xCondSlashR), + 9261, // 0 + 9267, // 1 + 9273, // 2 + 9279, // 3 + 9285, // 4 + 9291, // 5 + 9297, // 6 + 9303, // 7 + /*9261*/ uint16(xSetOp), uint16(ADD), + /*9263*/ uint16(xReadIb), + /*9264*/ uint16(xArgRM8), + /*9265*/ uint16(xArgImm8u), + /*9266*/ uint16(xMatch), + /*9267*/ uint16(xSetOp), uint16(OR), + /*9269*/ uint16(xReadIb), + /*9270*/ uint16(xArgRM8), + /*9271*/ uint16(xArgImm8u), + /*9272*/ uint16(xMatch), + /*9273*/ uint16(xSetOp), uint16(ADC), + /*9275*/ uint16(xReadIb), + /*9276*/ uint16(xArgRM8), + /*9277*/ uint16(xArgImm8u), + /*9278*/ uint16(xMatch), + /*9279*/ uint16(xSetOp), uint16(SBB), + /*9281*/ uint16(xReadIb), + /*9282*/ uint16(xArgRM8), + /*9283*/ uint16(xArgImm8u), + /*9284*/ uint16(xMatch), + /*9285*/ uint16(xSetOp), uint16(AND), + /*9287*/ uint16(xReadIb), + /*9288*/ uint16(xArgRM8), + /*9289*/ uint16(xArgImm8u), + /*9290*/ uint16(xMatch), + /*9291*/ uint16(xSetOp), uint16(SUB), + /*9293*/ uint16(xReadIb), + /*9294*/ uint16(xArgRM8), + /*9295*/ uint16(xArgImm8u), + /*9296*/ uint16(xMatch), + /*9297*/ uint16(xSetOp), uint16(XOR), + /*9299*/ uint16(xReadIb), + /*9300*/ uint16(xArgRM8), + /*9301*/ uint16(xArgImm8u), + /*9302*/ uint16(xMatch), + /*9303*/ uint16(xSetOp), uint16(CMP), + /*9305*/ uint16(xReadIb), + /*9306*/ uint16(xArgRM8), + /*9307*/ uint16(xArgImm8u), + /*9308*/ uint16(xMatch), + /*9309*/ uint16(xCondSlashR), + 9318, // 0 + 9347, // 1 + 9376, // 2 + 9405, // 3 + 9434, // 4 + 9463, // 5 + 9492, // 6 + 9521, // 7 + /*9318*/ uint16(xCondIs64), 9321, 9337, + /*9321*/ uint16(xCondDataSize), 9325, 9331, 0, + /*9325*/ uint16(xSetOp), uint16(ADD), + /*9327*/ uint16(xReadIw), + /*9328*/ uint16(xArgRM16), + /*9329*/ uint16(xArgImm16), + /*9330*/ uint16(xMatch), + /*9331*/ uint16(xSetOp), uint16(ADD), + /*9333*/ uint16(xReadId), + /*9334*/ uint16(xArgRM32), + /*9335*/ uint16(xArgImm32), + /*9336*/ uint16(xMatch), + /*9337*/ uint16(xCondDataSize), 9325, 9331, 9341, + /*9341*/ uint16(xSetOp), uint16(ADD), + /*9343*/ uint16(xReadId), + /*9344*/ uint16(xArgRM64), + /*9345*/ uint16(xArgImm32), + /*9346*/ uint16(xMatch), + /*9347*/ uint16(xCondIs64), 9350, 9366, + /*9350*/ uint16(xCondDataSize), 9354, 9360, 0, + /*9354*/ uint16(xSetOp), uint16(OR), + /*9356*/ uint16(xReadIw), + /*9357*/ uint16(xArgRM16), + /*9358*/ uint16(xArgImm16), + /*9359*/ uint16(xMatch), + /*9360*/ uint16(xSetOp), uint16(OR), + /*9362*/ uint16(xReadId), + /*9363*/ uint16(xArgRM32), + /*9364*/ uint16(xArgImm32), + /*9365*/ uint16(xMatch), + /*9366*/ uint16(xCondDataSize), 9354, 9360, 9370, + /*9370*/ uint16(xSetOp), uint16(OR), + /*9372*/ uint16(xReadId), + /*9373*/ uint16(xArgRM64), + /*9374*/ uint16(xArgImm32), + /*9375*/ uint16(xMatch), + /*9376*/ uint16(xCondIs64), 9379, 9395, + /*9379*/ uint16(xCondDataSize), 9383, 9389, 0, + /*9383*/ uint16(xSetOp), uint16(ADC), + /*9385*/ uint16(xReadIw), + /*9386*/ uint16(xArgRM16), + /*9387*/ uint16(xArgImm16), + /*9388*/ uint16(xMatch), + /*9389*/ uint16(xSetOp), uint16(ADC), + /*9391*/ uint16(xReadId), + /*9392*/ uint16(xArgRM32), + /*9393*/ uint16(xArgImm32), + /*9394*/ uint16(xMatch), + /*9395*/ uint16(xCondDataSize), 9383, 9389, 9399, + /*9399*/ uint16(xSetOp), uint16(ADC), + /*9401*/ uint16(xReadId), + /*9402*/ uint16(xArgRM64), + /*9403*/ uint16(xArgImm32), + /*9404*/ uint16(xMatch), + /*9405*/ uint16(xCondIs64), 9408, 9424, + /*9408*/ uint16(xCondDataSize), 9412, 9418, 0, + /*9412*/ uint16(xSetOp), uint16(SBB), + /*9414*/ uint16(xReadIw), + /*9415*/ uint16(xArgRM16), + /*9416*/ uint16(xArgImm16), + /*9417*/ uint16(xMatch), + /*9418*/ uint16(xSetOp), uint16(SBB), + /*9420*/ uint16(xReadId), + /*9421*/ uint16(xArgRM32), + /*9422*/ uint16(xArgImm32), + /*9423*/ uint16(xMatch), + /*9424*/ uint16(xCondDataSize), 9412, 9418, 9428, + /*9428*/ uint16(xSetOp), uint16(SBB), + /*9430*/ uint16(xReadId), + /*9431*/ uint16(xArgRM64), + /*9432*/ uint16(xArgImm32), + /*9433*/ uint16(xMatch), + /*9434*/ uint16(xCondIs64), 9437, 9453, + /*9437*/ uint16(xCondDataSize), 9441, 9447, 0, + /*9441*/ uint16(xSetOp), uint16(AND), + /*9443*/ uint16(xReadIw), + /*9444*/ uint16(xArgRM16), + /*9445*/ uint16(xArgImm16), + /*9446*/ uint16(xMatch), + /*9447*/ uint16(xSetOp), uint16(AND), + /*9449*/ uint16(xReadId), + /*9450*/ uint16(xArgRM32), + /*9451*/ uint16(xArgImm32), + /*9452*/ uint16(xMatch), + /*9453*/ uint16(xCondDataSize), 9441, 9447, 9457, + /*9457*/ uint16(xSetOp), uint16(AND), + /*9459*/ uint16(xReadId), + /*9460*/ uint16(xArgRM64), + /*9461*/ uint16(xArgImm32), + /*9462*/ uint16(xMatch), + /*9463*/ uint16(xCondIs64), 9466, 9482, + /*9466*/ uint16(xCondDataSize), 9470, 9476, 0, + /*9470*/ uint16(xSetOp), uint16(SUB), + /*9472*/ uint16(xReadIw), + /*9473*/ uint16(xArgRM16), + /*9474*/ uint16(xArgImm16), + /*9475*/ uint16(xMatch), + /*9476*/ uint16(xSetOp), uint16(SUB), + /*9478*/ uint16(xReadId), + /*9479*/ uint16(xArgRM32), + /*9480*/ uint16(xArgImm32), + /*9481*/ uint16(xMatch), + /*9482*/ uint16(xCondDataSize), 9470, 9476, 9486, + /*9486*/ uint16(xSetOp), uint16(SUB), + /*9488*/ uint16(xReadId), + /*9489*/ uint16(xArgRM64), + /*9490*/ uint16(xArgImm32), + /*9491*/ uint16(xMatch), + /*9492*/ uint16(xCondIs64), 9495, 9511, + /*9495*/ uint16(xCondDataSize), 9499, 9505, 0, + /*9499*/ uint16(xSetOp), uint16(XOR), + /*9501*/ uint16(xReadIw), + /*9502*/ uint16(xArgRM16), + /*9503*/ uint16(xArgImm16), + /*9504*/ uint16(xMatch), + /*9505*/ uint16(xSetOp), uint16(XOR), + /*9507*/ uint16(xReadId), + /*9508*/ uint16(xArgRM32), + /*9509*/ uint16(xArgImm32), + /*9510*/ uint16(xMatch), + /*9511*/ uint16(xCondDataSize), 9499, 9505, 9515, + /*9515*/ uint16(xSetOp), uint16(XOR), + /*9517*/ uint16(xReadId), + /*9518*/ uint16(xArgRM64), + /*9519*/ uint16(xArgImm32), + /*9520*/ uint16(xMatch), + /*9521*/ uint16(xCondIs64), 9524, 9540, + /*9524*/ uint16(xCondDataSize), 9528, 9534, 0, + /*9528*/ uint16(xSetOp), uint16(CMP), + /*9530*/ uint16(xReadIw), + /*9531*/ uint16(xArgRM16), + /*9532*/ uint16(xArgImm16), + /*9533*/ uint16(xMatch), + /*9534*/ uint16(xSetOp), uint16(CMP), + /*9536*/ uint16(xReadId), + /*9537*/ uint16(xArgRM32), + /*9538*/ uint16(xArgImm32), + /*9539*/ uint16(xMatch), + /*9540*/ uint16(xCondDataSize), 9528, 9534, 9544, + /*9544*/ uint16(xSetOp), uint16(CMP), + /*9546*/ uint16(xReadId), + /*9547*/ uint16(xArgRM64), + /*9548*/ uint16(xArgImm32), + /*9549*/ uint16(xMatch), + /*9550*/ uint16(xCondSlashR), + 9559, // 0 + 9588, // 1 + 9617, // 2 + 9646, // 3 + 9675, // 4 + 9704, // 5 + 9733, // 6 + 9762, // 7 + /*9559*/ uint16(xCondIs64), 9562, 9578, + /*9562*/ uint16(xCondDataSize), 9566, 9572, 0, + /*9566*/ uint16(xSetOp), uint16(ADD), + /*9568*/ uint16(xReadIb), + /*9569*/ uint16(xArgRM16), + /*9570*/ uint16(xArgImm8), + /*9571*/ uint16(xMatch), + /*9572*/ uint16(xSetOp), uint16(ADD), + /*9574*/ uint16(xReadIb), + /*9575*/ uint16(xArgRM32), + /*9576*/ uint16(xArgImm8), + /*9577*/ uint16(xMatch), + /*9578*/ uint16(xCondDataSize), 9566, 9572, 9582, + /*9582*/ uint16(xSetOp), uint16(ADD), + /*9584*/ uint16(xReadIb), + /*9585*/ uint16(xArgRM64), + /*9586*/ uint16(xArgImm8), + /*9587*/ uint16(xMatch), + /*9588*/ uint16(xCondIs64), 9591, 9607, + /*9591*/ uint16(xCondDataSize), 9595, 9601, 0, + /*9595*/ uint16(xSetOp), uint16(OR), + /*9597*/ uint16(xReadIb), + /*9598*/ uint16(xArgRM16), + /*9599*/ uint16(xArgImm8), + /*9600*/ uint16(xMatch), + /*9601*/ uint16(xSetOp), uint16(OR), + /*9603*/ uint16(xReadIb), + /*9604*/ uint16(xArgRM32), + /*9605*/ uint16(xArgImm8), + /*9606*/ uint16(xMatch), + /*9607*/ uint16(xCondDataSize), 9595, 9601, 9611, + /*9611*/ uint16(xSetOp), uint16(OR), + /*9613*/ uint16(xReadIb), + /*9614*/ uint16(xArgRM64), + /*9615*/ uint16(xArgImm8), + /*9616*/ uint16(xMatch), + /*9617*/ uint16(xCondIs64), 9620, 9636, + /*9620*/ uint16(xCondDataSize), 9624, 9630, 0, + /*9624*/ uint16(xSetOp), uint16(ADC), + /*9626*/ uint16(xReadIb), + /*9627*/ uint16(xArgRM16), + /*9628*/ uint16(xArgImm8), + /*9629*/ uint16(xMatch), + /*9630*/ uint16(xSetOp), uint16(ADC), + /*9632*/ uint16(xReadIb), + /*9633*/ uint16(xArgRM32), + /*9634*/ uint16(xArgImm8), + /*9635*/ uint16(xMatch), + /*9636*/ uint16(xCondDataSize), 9624, 9630, 9640, + /*9640*/ uint16(xSetOp), uint16(ADC), + /*9642*/ uint16(xReadIb), + /*9643*/ uint16(xArgRM64), + /*9644*/ uint16(xArgImm8), + /*9645*/ uint16(xMatch), + /*9646*/ uint16(xCondIs64), 9649, 9665, + /*9649*/ uint16(xCondDataSize), 9653, 9659, 0, + /*9653*/ uint16(xSetOp), uint16(SBB), + /*9655*/ uint16(xReadIb), + /*9656*/ uint16(xArgRM16), + /*9657*/ uint16(xArgImm8), + /*9658*/ uint16(xMatch), + /*9659*/ uint16(xSetOp), uint16(SBB), + /*9661*/ uint16(xReadIb), + /*9662*/ uint16(xArgRM32), + /*9663*/ uint16(xArgImm8), + /*9664*/ uint16(xMatch), + /*9665*/ uint16(xCondDataSize), 9653, 9659, 9669, + /*9669*/ uint16(xSetOp), uint16(SBB), + /*9671*/ uint16(xReadIb), + /*9672*/ uint16(xArgRM64), + /*9673*/ uint16(xArgImm8), + /*9674*/ uint16(xMatch), + /*9675*/ uint16(xCondIs64), 9678, 9694, + /*9678*/ uint16(xCondDataSize), 9682, 9688, 0, + /*9682*/ uint16(xSetOp), uint16(AND), + /*9684*/ uint16(xReadIb), + /*9685*/ uint16(xArgRM16), + /*9686*/ uint16(xArgImm8), + /*9687*/ uint16(xMatch), + /*9688*/ uint16(xSetOp), uint16(AND), + /*9690*/ uint16(xReadIb), + /*9691*/ uint16(xArgRM32), + /*9692*/ uint16(xArgImm8), + /*9693*/ uint16(xMatch), + /*9694*/ uint16(xCondDataSize), 9682, 9688, 9698, + /*9698*/ uint16(xSetOp), uint16(AND), + /*9700*/ uint16(xReadIb), + /*9701*/ uint16(xArgRM64), + /*9702*/ uint16(xArgImm8), + /*9703*/ uint16(xMatch), + /*9704*/ uint16(xCondIs64), 9707, 9723, + /*9707*/ uint16(xCondDataSize), 9711, 9717, 0, + /*9711*/ uint16(xSetOp), uint16(SUB), + /*9713*/ uint16(xReadIb), + /*9714*/ uint16(xArgRM16), + /*9715*/ uint16(xArgImm8), + /*9716*/ uint16(xMatch), + /*9717*/ uint16(xSetOp), uint16(SUB), + /*9719*/ uint16(xReadIb), + /*9720*/ uint16(xArgRM32), + /*9721*/ uint16(xArgImm8), + /*9722*/ uint16(xMatch), + /*9723*/ uint16(xCondDataSize), 9711, 9717, 9727, + /*9727*/ uint16(xSetOp), uint16(SUB), + /*9729*/ uint16(xReadIb), + /*9730*/ uint16(xArgRM64), + /*9731*/ uint16(xArgImm8), + /*9732*/ uint16(xMatch), + /*9733*/ uint16(xCondIs64), 9736, 9752, + /*9736*/ uint16(xCondDataSize), 9740, 9746, 0, + /*9740*/ uint16(xSetOp), uint16(XOR), + /*9742*/ uint16(xReadIb), + /*9743*/ uint16(xArgRM16), + /*9744*/ uint16(xArgImm8), + /*9745*/ uint16(xMatch), + /*9746*/ uint16(xSetOp), uint16(XOR), + /*9748*/ uint16(xReadIb), + /*9749*/ uint16(xArgRM32), + /*9750*/ uint16(xArgImm8), + /*9751*/ uint16(xMatch), + /*9752*/ uint16(xCondDataSize), 9740, 9746, 9756, + /*9756*/ uint16(xSetOp), uint16(XOR), + /*9758*/ uint16(xReadIb), + /*9759*/ uint16(xArgRM64), + /*9760*/ uint16(xArgImm8), + /*9761*/ uint16(xMatch), + /*9762*/ uint16(xCondIs64), 9765, 9781, + /*9765*/ uint16(xCondDataSize), 9769, 9775, 0, + /*9769*/ uint16(xSetOp), uint16(CMP), + /*9771*/ uint16(xReadIb), + /*9772*/ uint16(xArgRM16), + /*9773*/ uint16(xArgImm8), + /*9774*/ uint16(xMatch), + /*9775*/ uint16(xSetOp), uint16(CMP), + /*9777*/ uint16(xReadIb), + /*9778*/ uint16(xArgRM32), + /*9779*/ uint16(xArgImm8), + /*9780*/ uint16(xMatch), + /*9781*/ uint16(xCondDataSize), 9769, 9775, 9785, + /*9785*/ uint16(xSetOp), uint16(CMP), + /*9787*/ uint16(xReadIb), + /*9788*/ uint16(xArgRM64), + /*9789*/ uint16(xArgImm8), + /*9790*/ uint16(xMatch), + /*9791*/ uint16(xSetOp), uint16(TEST), + /*9793*/ uint16(xReadSlashR), + /*9794*/ uint16(xArgRM8), + /*9795*/ uint16(xArgR8), + /*9796*/ uint16(xMatch), + /*9797*/ uint16(xCondIs64), 9800, 9816, + /*9800*/ uint16(xCondDataSize), 9804, 9810, 0, + /*9804*/ uint16(xSetOp), uint16(TEST), + /*9806*/ uint16(xReadSlashR), + /*9807*/ uint16(xArgRM16), + /*9808*/ uint16(xArgR16), + /*9809*/ uint16(xMatch), + /*9810*/ uint16(xSetOp), uint16(TEST), + /*9812*/ uint16(xReadSlashR), + /*9813*/ uint16(xArgRM32), + /*9814*/ uint16(xArgR32), + /*9815*/ uint16(xMatch), + /*9816*/ uint16(xCondDataSize), 9804, 9810, 9820, + /*9820*/ uint16(xSetOp), uint16(TEST), + /*9822*/ uint16(xReadSlashR), + /*9823*/ uint16(xArgRM64), + /*9824*/ uint16(xArgR64), + /*9825*/ uint16(xMatch), + /*9826*/ uint16(xSetOp), uint16(XCHG), + /*9828*/ uint16(xReadSlashR), + /*9829*/ uint16(xArgRM8), + /*9830*/ uint16(xArgR8), + /*9831*/ uint16(xMatch), + /*9832*/ uint16(xCondIs64), 9835, 9851, + /*9835*/ uint16(xCondDataSize), 9839, 9845, 0, + /*9839*/ uint16(xSetOp), uint16(XCHG), + /*9841*/ uint16(xReadSlashR), + /*9842*/ uint16(xArgRM16), + /*9843*/ uint16(xArgR16), + /*9844*/ uint16(xMatch), + /*9845*/ uint16(xSetOp), uint16(XCHG), + /*9847*/ uint16(xReadSlashR), + /*9848*/ uint16(xArgRM32), + /*9849*/ uint16(xArgR32), + /*9850*/ uint16(xMatch), + /*9851*/ uint16(xCondDataSize), 9839, 9845, 9855, + /*9855*/ uint16(xSetOp), uint16(XCHG), + /*9857*/ uint16(xReadSlashR), + /*9858*/ uint16(xArgRM64), + /*9859*/ uint16(xArgR64), + /*9860*/ uint16(xMatch), + /*9861*/ uint16(xSetOp), uint16(MOV), + /*9863*/ uint16(xReadSlashR), + /*9864*/ uint16(xArgRM8), + /*9865*/ uint16(xArgR8), + /*9866*/ uint16(xMatch), + /*9867*/ uint16(xCondDataSize), 9871, 9877, 9883, + /*9871*/ uint16(xSetOp), uint16(MOV), + /*9873*/ uint16(xReadSlashR), + /*9874*/ uint16(xArgRM16), + /*9875*/ uint16(xArgR16), + /*9876*/ uint16(xMatch), + /*9877*/ uint16(xSetOp), uint16(MOV), + /*9879*/ uint16(xReadSlashR), + /*9880*/ uint16(xArgRM32), + /*9881*/ uint16(xArgR32), + /*9882*/ uint16(xMatch), + /*9883*/ uint16(xSetOp), uint16(MOV), + /*9885*/ uint16(xReadSlashR), + /*9886*/ uint16(xArgRM64), + /*9887*/ uint16(xArgR64), + /*9888*/ uint16(xMatch), + /*9889*/ uint16(xSetOp), uint16(MOV), + /*9891*/ uint16(xReadSlashR), + /*9892*/ uint16(xArgR8), + /*9893*/ uint16(xArgRM8), + /*9894*/ uint16(xMatch), + /*9895*/ uint16(xCondDataSize), 9899, 9905, 9911, + /*9899*/ uint16(xSetOp), uint16(MOV), + /*9901*/ uint16(xReadSlashR), + /*9902*/ uint16(xArgR16), + /*9903*/ uint16(xArgRM16), + /*9904*/ uint16(xMatch), + /*9905*/ uint16(xSetOp), uint16(MOV), + /*9907*/ uint16(xReadSlashR), + /*9908*/ uint16(xArgR32), + /*9909*/ uint16(xArgRM32), + /*9910*/ uint16(xMatch), + /*9911*/ uint16(xSetOp), uint16(MOV), + /*9913*/ uint16(xReadSlashR), + /*9914*/ uint16(xArgR64), + /*9915*/ uint16(xArgRM64), + /*9916*/ uint16(xMatch), + /*9917*/ uint16(xCondIs64), 9920, 9936, + /*9920*/ uint16(xCondDataSize), 9924, 9930, 0, + /*9924*/ uint16(xSetOp), uint16(MOV), + /*9926*/ uint16(xReadSlashR), + /*9927*/ uint16(xArgRM16), + /*9928*/ uint16(xArgSreg), + /*9929*/ uint16(xMatch), + /*9930*/ uint16(xSetOp), uint16(MOV), + /*9932*/ uint16(xReadSlashR), + /*9933*/ uint16(xArgR32M16), + /*9934*/ uint16(xArgSreg), + /*9935*/ uint16(xMatch), + /*9936*/ uint16(xCondDataSize), 9924, 9930, 9940, + /*9940*/ uint16(xSetOp), uint16(MOV), + /*9942*/ uint16(xReadSlashR), + /*9943*/ uint16(xArgR64M16), + /*9944*/ uint16(xArgSreg), + /*9945*/ uint16(xMatch), + /*9946*/ uint16(xCondIs64), 9949, 9965, + /*9949*/ uint16(xCondDataSize), 9953, 9959, 0, + /*9953*/ uint16(xSetOp), uint16(LEA), + /*9955*/ uint16(xReadSlashR), + /*9956*/ uint16(xArgR16), + /*9957*/ uint16(xArgM), + /*9958*/ uint16(xMatch), + /*9959*/ uint16(xSetOp), uint16(LEA), + /*9961*/ uint16(xReadSlashR), + /*9962*/ uint16(xArgR32), + /*9963*/ uint16(xArgM), + /*9964*/ uint16(xMatch), + /*9965*/ uint16(xCondDataSize), 9953, 9959, 9969, + /*9969*/ uint16(xSetOp), uint16(LEA), + /*9971*/ uint16(xReadSlashR), + /*9972*/ uint16(xArgR64), + /*9973*/ uint16(xArgM), + /*9974*/ uint16(xMatch), + /*9975*/ uint16(xCondIs64), 9978, 9994, + /*9978*/ uint16(xCondDataSize), 9982, 9988, 0, + /*9982*/ uint16(xSetOp), uint16(MOV), + /*9984*/ uint16(xReadSlashR), + /*9985*/ uint16(xArgSreg), + /*9986*/ uint16(xArgRM16), + /*9987*/ uint16(xMatch), + /*9988*/ uint16(xSetOp), uint16(MOV), + /*9990*/ uint16(xReadSlashR), + /*9991*/ uint16(xArgSreg), + /*9992*/ uint16(xArgR32M16), + /*9993*/ uint16(xMatch), + /*9994*/ uint16(xCondDataSize), 9982, 9988, 9998, + /*9998*/ uint16(xSetOp), uint16(MOV), + /*10000*/ uint16(xReadSlashR), + /*10001*/ uint16(xArgSreg), + /*10002*/ uint16(xArgR64M16), + /*10003*/ uint16(xMatch), + /*10004*/ uint16(xCondSlashR), + 10013, // 0 + 0, // 1 + 0, // 2 + 0, // 3 + 0, // 4 + 0, // 5 + 0, // 6 + 0, // 7 + /*10013*/ uint16(xCondIs64), 10016, 10028, + /*10016*/ uint16(xCondDataSize), 10020, 10024, 0, + /*10020*/ uint16(xSetOp), uint16(POP), + /*10022*/ uint16(xArgRM16), + /*10023*/ uint16(xMatch), + /*10024*/ uint16(xSetOp), uint16(POP), + /*10026*/ uint16(xArgRM32), + /*10027*/ uint16(xMatch), + /*10028*/ uint16(xCondDataSize), 10020, 10032, 10036, + /*10032*/ uint16(xSetOp), uint16(POP), + /*10034*/ uint16(xArgRM64), + /*10035*/ uint16(xMatch), + /*10036*/ uint16(xSetOp), uint16(POP), + /*10038*/ uint16(xArgRM64), + /*10039*/ uint16(xMatch), + /*10040*/ uint16(xCondIs64), 10043, 10057, + /*10043*/ uint16(xCondDataSize), 10047, 10052, 0, + /*10047*/ uint16(xSetOp), uint16(XCHG), + /*10049*/ uint16(xArgR16op), + /*10050*/ uint16(xArgAX), + /*10051*/ uint16(xMatch), + /*10052*/ uint16(xSetOp), uint16(XCHG), + /*10054*/ uint16(xArgR32op), + /*10055*/ uint16(xArgEAX), + /*10056*/ uint16(xMatch), + /*10057*/ uint16(xCondDataSize), 10047, 10052, 10061, + /*10061*/ uint16(xSetOp), uint16(XCHG), + /*10063*/ uint16(xArgR64op), + /*10064*/ uint16(xArgRAX), + /*10065*/ uint16(xMatch), + /*10066*/ uint16(xCondIs64), 10069, 10079, + /*10069*/ uint16(xCondDataSize), 10073, 10076, 0, + /*10073*/ uint16(xSetOp), uint16(CBW), + /*10075*/ uint16(xMatch), + /*10076*/ uint16(xSetOp), uint16(CWDE), + /*10078*/ uint16(xMatch), + /*10079*/ uint16(xCondDataSize), 10073, 10076, 10083, + /*10083*/ uint16(xSetOp), uint16(CDQE), + /*10085*/ uint16(xMatch), + /*10086*/ uint16(xCondIs64), 10089, 10099, + /*10089*/ uint16(xCondDataSize), 10093, 10096, 0, + /*10093*/ uint16(xSetOp), uint16(CWD), + /*10095*/ uint16(xMatch), + /*10096*/ uint16(xSetOp), uint16(CDQ), + /*10098*/ uint16(xMatch), + /*10099*/ uint16(xCondDataSize), 10093, 10096, 10103, + /*10103*/ uint16(xSetOp), uint16(CQO), + /*10105*/ uint16(xMatch), + /*10106*/ uint16(xCondIs64), 10109, 0, + /*10109*/ uint16(xCondDataSize), 10113, 10118, 0, + /*10113*/ uint16(xSetOp), uint16(LCALL), + /*10115*/ uint16(xReadCd), + /*10116*/ uint16(xArgPtr16colon16), + /*10117*/ uint16(xMatch), + /*10118*/ uint16(xSetOp), uint16(LCALL), + /*10120*/ uint16(xReadCp), + /*10121*/ uint16(xArgPtr16colon32), + /*10122*/ uint16(xMatch), + /*10123*/ uint16(xSetOp), uint16(FWAIT), + /*10125*/ uint16(xMatch), + /*10126*/ uint16(xCondIs64), 10129, 10139, + /*10129*/ uint16(xCondDataSize), 10133, 10136, 0, + /*10133*/ uint16(xSetOp), uint16(PUSHF), + /*10135*/ uint16(xMatch), + /*10136*/ uint16(xSetOp), uint16(PUSHFD), + /*10138*/ uint16(xMatch), + /*10139*/ uint16(xCondDataSize), 10133, 10143, 10146, + /*10143*/ uint16(xSetOp), uint16(PUSHFQ), + /*10145*/ uint16(xMatch), + /*10146*/ uint16(xSetOp), uint16(PUSHFQ), + /*10148*/ uint16(xMatch), + /*10149*/ uint16(xCondIs64), 10152, 10162, + /*10152*/ uint16(xCondDataSize), 10156, 10159, 0, + /*10156*/ uint16(xSetOp), uint16(POPF), + /*10158*/ uint16(xMatch), + /*10159*/ uint16(xSetOp), uint16(POPFD), + /*10161*/ uint16(xMatch), + /*10162*/ uint16(xCondDataSize), 10156, 10166, 10169, + /*10166*/ uint16(xSetOp), uint16(POPFQ), + /*10168*/ uint16(xMatch), + /*10169*/ uint16(xSetOp), uint16(POPFQ), + /*10171*/ uint16(xMatch), + /*10172*/ uint16(xSetOp), uint16(SAHF), + /*10174*/ uint16(xMatch), + /*10175*/ uint16(xSetOp), uint16(LAHF), + /*10177*/ uint16(xMatch), + /*10178*/ uint16(xCondIs64), 10181, 10187, + /*10181*/ uint16(xSetOp), uint16(MOV), + /*10183*/ uint16(xReadCm), + /*10184*/ uint16(xArgAL), + /*10185*/ uint16(xArgMoffs8), + /*10186*/ uint16(xMatch), + /*10187*/ uint16(xCondDataSize), 10181, 10181, 10191, + /*10191*/ uint16(xSetOp), uint16(MOV), + /*10193*/ uint16(xReadCm), + /*10194*/ uint16(xArgAL), + /*10195*/ uint16(xArgMoffs8), + /*10196*/ uint16(xMatch), + /*10197*/ uint16(xCondDataSize), 10201, 10207, 10213, + /*10201*/ uint16(xSetOp), uint16(MOV), + /*10203*/ uint16(xReadCm), + /*10204*/ uint16(xArgAX), + /*10205*/ uint16(xArgMoffs16), + /*10206*/ uint16(xMatch), + /*10207*/ uint16(xSetOp), uint16(MOV), + /*10209*/ uint16(xReadCm), + /*10210*/ uint16(xArgEAX), + /*10211*/ uint16(xArgMoffs32), + /*10212*/ uint16(xMatch), + /*10213*/ uint16(xSetOp), uint16(MOV), + /*10215*/ uint16(xReadCm), + /*10216*/ uint16(xArgRAX), + /*10217*/ uint16(xArgMoffs64), + /*10218*/ uint16(xMatch), + /*10219*/ uint16(xCondIs64), 10222, 10228, + /*10222*/ uint16(xSetOp), uint16(MOV), + /*10224*/ uint16(xReadCm), + /*10225*/ uint16(xArgMoffs8), + /*10226*/ uint16(xArgAL), + /*10227*/ uint16(xMatch), + /*10228*/ uint16(xCondDataSize), 10222, 10222, 10232, + /*10232*/ uint16(xSetOp), uint16(MOV), + /*10234*/ uint16(xReadCm), + /*10235*/ uint16(xArgMoffs8), + /*10236*/ uint16(xArgAL), + /*10237*/ uint16(xMatch), + /*10238*/ uint16(xCondDataSize), 10242, 10248, 10254, + /*10242*/ uint16(xSetOp), uint16(MOV), + /*10244*/ uint16(xReadCm), + /*10245*/ uint16(xArgMoffs16), + /*10246*/ uint16(xArgAX), + /*10247*/ uint16(xMatch), + /*10248*/ uint16(xSetOp), uint16(MOV), + /*10250*/ uint16(xReadCm), + /*10251*/ uint16(xArgMoffs32), + /*10252*/ uint16(xArgEAX), + /*10253*/ uint16(xMatch), + /*10254*/ uint16(xSetOp), uint16(MOV), + /*10256*/ uint16(xReadCm), + /*10257*/ uint16(xArgMoffs64), + /*10258*/ uint16(xArgRAX), + /*10259*/ uint16(xMatch), + /*10260*/ uint16(xSetOp), uint16(MOVSB), + /*10262*/ uint16(xMatch), + /*10263*/ uint16(xCondIs64), 10266, 10276, + /*10266*/ uint16(xCondDataSize), 10270, 10273, 0, + /*10270*/ uint16(xSetOp), uint16(MOVSW), + /*10272*/ uint16(xMatch), + /*10273*/ uint16(xSetOp), uint16(MOVSD), + /*10275*/ uint16(xMatch), + /*10276*/ uint16(xCondDataSize), 10270, 10273, 10280, + /*10280*/ uint16(xSetOp), uint16(MOVSQ), + /*10282*/ uint16(xMatch), + /*10283*/ uint16(xSetOp), uint16(CMPSB), + /*10285*/ uint16(xMatch), + /*10286*/ uint16(xCondIs64), 10289, 10299, + /*10289*/ uint16(xCondDataSize), 10293, 10296, 0, + /*10293*/ uint16(xSetOp), uint16(CMPSW), + /*10295*/ uint16(xMatch), + /*10296*/ uint16(xSetOp), uint16(CMPSD), + /*10298*/ uint16(xMatch), + /*10299*/ uint16(xCondDataSize), 10293, 10296, 10303, + /*10303*/ uint16(xSetOp), uint16(CMPSQ), + /*10305*/ uint16(xMatch), + /*10306*/ uint16(xSetOp), uint16(TEST), + /*10308*/ uint16(xReadIb), + /*10309*/ uint16(xArgAL), + /*10310*/ uint16(xArgImm8u), + /*10311*/ uint16(xMatch), + /*10312*/ uint16(xCondIs64), 10315, 10331, + /*10315*/ uint16(xCondDataSize), 10319, 10325, 0, + /*10319*/ uint16(xSetOp), uint16(TEST), + /*10321*/ uint16(xReadIw), + /*10322*/ uint16(xArgAX), + /*10323*/ uint16(xArgImm16), + /*10324*/ uint16(xMatch), + /*10325*/ uint16(xSetOp), uint16(TEST), + /*10327*/ uint16(xReadId), + /*10328*/ uint16(xArgEAX), + /*10329*/ uint16(xArgImm32), + /*10330*/ uint16(xMatch), + /*10331*/ uint16(xCondDataSize), 10319, 10325, 10335, + /*10335*/ uint16(xSetOp), uint16(TEST), + /*10337*/ uint16(xReadId), + /*10338*/ uint16(xArgRAX), + /*10339*/ uint16(xArgImm32), + /*10340*/ uint16(xMatch), + /*10341*/ uint16(xSetOp), uint16(STOSB), + /*10343*/ uint16(xMatch), + /*10344*/ uint16(xCondIs64), 10347, 10357, + /*10347*/ uint16(xCondDataSize), 10351, 10354, 0, + /*10351*/ uint16(xSetOp), uint16(STOSW), + /*10353*/ uint16(xMatch), + /*10354*/ uint16(xSetOp), uint16(STOSD), + /*10356*/ uint16(xMatch), + /*10357*/ uint16(xCondDataSize), 10351, 10354, 10361, + /*10361*/ uint16(xSetOp), uint16(STOSQ), + /*10363*/ uint16(xMatch), + /*10364*/ uint16(xSetOp), uint16(LODSB), + /*10366*/ uint16(xMatch), + /*10367*/ uint16(xCondIs64), 10370, 10380, + /*10370*/ uint16(xCondDataSize), 10374, 10377, 0, + /*10374*/ uint16(xSetOp), uint16(LODSW), + /*10376*/ uint16(xMatch), + /*10377*/ uint16(xSetOp), uint16(LODSD), + /*10379*/ uint16(xMatch), + /*10380*/ uint16(xCondDataSize), 10374, 10377, 10384, + /*10384*/ uint16(xSetOp), uint16(LODSQ), + /*10386*/ uint16(xMatch), + /*10387*/ uint16(xSetOp), uint16(SCASB), + /*10389*/ uint16(xMatch), + /*10390*/ uint16(xCondIs64), 10393, 10403, + /*10393*/ uint16(xCondDataSize), 10397, 10400, 0, + /*10397*/ uint16(xSetOp), uint16(SCASW), + /*10399*/ uint16(xMatch), + /*10400*/ uint16(xSetOp), uint16(SCASD), + /*10402*/ uint16(xMatch), + /*10403*/ uint16(xCondDataSize), 10397, 10400, 10407, + /*10407*/ uint16(xSetOp), uint16(SCASQ), + /*10409*/ uint16(xMatch), + /*10410*/ uint16(xSetOp), uint16(MOV), + /*10412*/ uint16(xReadIb), + /*10413*/ uint16(xArgR8op), + /*10414*/ uint16(xArgImm8u), + /*10415*/ uint16(xMatch), + /*10416*/ uint16(xCondIs64), 10419, 10435, + /*10419*/ uint16(xCondDataSize), 10423, 10429, 0, + /*10423*/ uint16(xSetOp), uint16(MOV), + /*10425*/ uint16(xReadIw), + /*10426*/ uint16(xArgR16op), + /*10427*/ uint16(xArgImm16), + /*10428*/ uint16(xMatch), + /*10429*/ uint16(xSetOp), uint16(MOV), + /*10431*/ uint16(xReadId), + /*10432*/ uint16(xArgR32op), + /*10433*/ uint16(xArgImm32), + /*10434*/ uint16(xMatch), + /*10435*/ uint16(xCondDataSize), 10423, 10429, 10439, + /*10439*/ uint16(xSetOp), uint16(MOV), + /*10441*/ uint16(xReadIo), + /*10442*/ uint16(xArgR64op), + /*10443*/ uint16(xArgImm64), + /*10444*/ uint16(xMatch), + /*10445*/ uint16(xCondSlashR), + 10454, // 0 + 10460, // 1 + 10466, // 2 + 10472, // 3 + 10478, // 4 + 10484, // 5 + 0, // 6 + 10490, // 7 + /*10454*/ uint16(xSetOp), uint16(ROL), + /*10456*/ uint16(xReadIb), + /*10457*/ uint16(xArgRM8), + /*10458*/ uint16(xArgImm8u), + /*10459*/ uint16(xMatch), + /*10460*/ uint16(xSetOp), uint16(ROR), + /*10462*/ uint16(xReadIb), + /*10463*/ uint16(xArgRM8), + /*10464*/ uint16(xArgImm8u), + /*10465*/ uint16(xMatch), + /*10466*/ uint16(xSetOp), uint16(RCL), + /*10468*/ uint16(xReadIb), + /*10469*/ uint16(xArgRM8), + /*10470*/ uint16(xArgImm8u), + /*10471*/ uint16(xMatch), + /*10472*/ uint16(xSetOp), uint16(RCR), + /*10474*/ uint16(xReadIb), + /*10475*/ uint16(xArgRM8), + /*10476*/ uint16(xArgImm8u), + /*10477*/ uint16(xMatch), + /*10478*/ uint16(xSetOp), uint16(SHL), + /*10480*/ uint16(xReadIb), + /*10481*/ uint16(xArgRM8), + /*10482*/ uint16(xArgImm8u), + /*10483*/ uint16(xMatch), + /*10484*/ uint16(xSetOp), uint16(SHR), + /*10486*/ uint16(xReadIb), + /*10487*/ uint16(xArgRM8), + /*10488*/ uint16(xArgImm8u), + /*10489*/ uint16(xMatch), + /*10490*/ uint16(xSetOp), uint16(SAR), + /*10492*/ uint16(xReadIb), + /*10493*/ uint16(xArgRM8), + /*10494*/ uint16(xArgImm8u), + /*10495*/ uint16(xMatch), + /*10496*/ uint16(xCondSlashR), + 10505, // 0 + 10527, // 1 + 10549, // 2 + 10578, // 3 + 10607, // 4 + 10636, // 5 + 0, // 6 + 10665, // 7 + /*10505*/ uint16(xCondDataSize), 10509, 10515, 10521, + /*10509*/ uint16(xSetOp), uint16(ROL), + /*10511*/ uint16(xReadIb), + /*10512*/ uint16(xArgRM16), + /*10513*/ uint16(xArgImm8u), + /*10514*/ uint16(xMatch), + /*10515*/ uint16(xSetOp), uint16(ROL), + /*10517*/ uint16(xReadIb), + /*10518*/ uint16(xArgRM32), + /*10519*/ uint16(xArgImm8u), + /*10520*/ uint16(xMatch), + /*10521*/ uint16(xSetOp), uint16(ROL), + /*10523*/ uint16(xReadIb), + /*10524*/ uint16(xArgRM64), + /*10525*/ uint16(xArgImm8u), + /*10526*/ uint16(xMatch), + /*10527*/ uint16(xCondDataSize), 10531, 10537, 10543, + /*10531*/ uint16(xSetOp), uint16(ROR), + /*10533*/ uint16(xReadIb), + /*10534*/ uint16(xArgRM16), + /*10535*/ uint16(xArgImm8u), + /*10536*/ uint16(xMatch), + /*10537*/ uint16(xSetOp), uint16(ROR), + /*10539*/ uint16(xReadIb), + /*10540*/ uint16(xArgRM32), + /*10541*/ uint16(xArgImm8u), + /*10542*/ uint16(xMatch), + /*10543*/ uint16(xSetOp), uint16(ROR), + /*10545*/ uint16(xReadIb), + /*10546*/ uint16(xArgRM64), + /*10547*/ uint16(xArgImm8u), + /*10548*/ uint16(xMatch), + /*10549*/ uint16(xCondIs64), 10552, 10568, + /*10552*/ uint16(xCondDataSize), 10556, 10562, 0, + /*10556*/ uint16(xSetOp), uint16(RCL), + /*10558*/ uint16(xReadIb), + /*10559*/ uint16(xArgRM16), + /*10560*/ uint16(xArgImm8u), + /*10561*/ uint16(xMatch), + /*10562*/ uint16(xSetOp), uint16(RCL), + /*10564*/ uint16(xReadIb), + /*10565*/ uint16(xArgRM32), + /*10566*/ uint16(xArgImm8u), + /*10567*/ uint16(xMatch), + /*10568*/ uint16(xCondDataSize), 10556, 10562, 10572, + /*10572*/ uint16(xSetOp), uint16(RCL), + /*10574*/ uint16(xReadIb), + /*10575*/ uint16(xArgRM64), + /*10576*/ uint16(xArgImm8u), + /*10577*/ uint16(xMatch), + /*10578*/ uint16(xCondIs64), 10581, 10597, + /*10581*/ uint16(xCondDataSize), 10585, 10591, 0, + /*10585*/ uint16(xSetOp), uint16(RCR), + /*10587*/ uint16(xReadIb), + /*10588*/ uint16(xArgRM16), + /*10589*/ uint16(xArgImm8u), + /*10590*/ uint16(xMatch), + /*10591*/ uint16(xSetOp), uint16(RCR), + /*10593*/ uint16(xReadIb), + /*10594*/ uint16(xArgRM32), + /*10595*/ uint16(xArgImm8u), + /*10596*/ uint16(xMatch), + /*10597*/ uint16(xCondDataSize), 10585, 10591, 10601, + /*10601*/ uint16(xSetOp), uint16(RCR), + /*10603*/ uint16(xReadIb), + /*10604*/ uint16(xArgRM64), + /*10605*/ uint16(xArgImm8u), + /*10606*/ uint16(xMatch), + /*10607*/ uint16(xCondIs64), 10610, 10626, + /*10610*/ uint16(xCondDataSize), 10614, 10620, 0, + /*10614*/ uint16(xSetOp), uint16(SHL), + /*10616*/ uint16(xReadIb), + /*10617*/ uint16(xArgRM16), + /*10618*/ uint16(xArgImm8u), + /*10619*/ uint16(xMatch), + /*10620*/ uint16(xSetOp), uint16(SHL), + /*10622*/ uint16(xReadIb), + /*10623*/ uint16(xArgRM32), + /*10624*/ uint16(xArgImm8u), + /*10625*/ uint16(xMatch), + /*10626*/ uint16(xCondDataSize), 10614, 10620, 10630, + /*10630*/ uint16(xSetOp), uint16(SHL), + /*10632*/ uint16(xReadIb), + /*10633*/ uint16(xArgRM64), + /*10634*/ uint16(xArgImm8u), + /*10635*/ uint16(xMatch), + /*10636*/ uint16(xCondIs64), 10639, 10655, + /*10639*/ uint16(xCondDataSize), 10643, 10649, 0, + /*10643*/ uint16(xSetOp), uint16(SHR), + /*10645*/ uint16(xReadIb), + /*10646*/ uint16(xArgRM16), + /*10647*/ uint16(xArgImm8u), + /*10648*/ uint16(xMatch), + /*10649*/ uint16(xSetOp), uint16(SHR), + /*10651*/ uint16(xReadIb), + /*10652*/ uint16(xArgRM32), + /*10653*/ uint16(xArgImm8u), + /*10654*/ uint16(xMatch), + /*10655*/ uint16(xCondDataSize), 10643, 10649, 10659, + /*10659*/ uint16(xSetOp), uint16(SHR), + /*10661*/ uint16(xReadIb), + /*10662*/ uint16(xArgRM64), + /*10663*/ uint16(xArgImm8u), + /*10664*/ uint16(xMatch), + /*10665*/ uint16(xCondIs64), 10668, 10684, + /*10668*/ uint16(xCondDataSize), 10672, 10678, 0, + /*10672*/ uint16(xSetOp), uint16(SAR), + /*10674*/ uint16(xReadIb), + /*10675*/ uint16(xArgRM16), + /*10676*/ uint16(xArgImm8u), + /*10677*/ uint16(xMatch), + /*10678*/ uint16(xSetOp), uint16(SAR), + /*10680*/ uint16(xReadIb), + /*10681*/ uint16(xArgRM32), + /*10682*/ uint16(xArgImm8u), + /*10683*/ uint16(xMatch), + /*10684*/ uint16(xCondDataSize), 10672, 10678, 10688, + /*10688*/ uint16(xSetOp), uint16(SAR), + /*10690*/ uint16(xReadIb), + /*10691*/ uint16(xArgRM64), + /*10692*/ uint16(xArgImm8u), + /*10693*/ uint16(xMatch), + /*10694*/ uint16(xSetOp), uint16(RET), + /*10696*/ uint16(xReadIw), + /*10697*/ uint16(xArgImm16u), + /*10698*/ uint16(xMatch), + /*10699*/ uint16(xSetOp), uint16(RET), + /*10701*/ uint16(xMatch), + /*10702*/ uint16(xCondIs64), 10705, 0, + /*10705*/ uint16(xCondDataSize), 10709, 10715, 0, + /*10709*/ uint16(xSetOp), uint16(LES), + /*10711*/ uint16(xReadSlashR), + /*10712*/ uint16(xArgR16), + /*10713*/ uint16(xArgM16colon16), + /*10714*/ uint16(xMatch), + /*10715*/ uint16(xSetOp), uint16(LES), + /*10717*/ uint16(xReadSlashR), + /*10718*/ uint16(xArgR32), + /*10719*/ uint16(xArgM16colon32), + /*10720*/ uint16(xMatch), + /*10721*/ uint16(xCondIs64), 10724, 0, + /*10724*/ uint16(xCondDataSize), 10728, 10734, 0, + /*10728*/ uint16(xSetOp), uint16(LDS), + /*10730*/ uint16(xReadSlashR), + /*10731*/ uint16(xArgR16), + /*10732*/ uint16(xArgM16colon16), + /*10733*/ uint16(xMatch), + /*10734*/ uint16(xSetOp), uint16(LDS), + /*10736*/ uint16(xReadSlashR), + /*10737*/ uint16(xArgR32), + /*10738*/ uint16(xArgM16colon32), + /*10739*/ uint16(xMatch), + /*10740*/ uint16(xCondByte), 1, + 0xF8, 10759, + /*10744*/ uint16(xCondSlashR), + 10753, // 0 + 0, // 1 + 0, // 2 + 0, // 3 + 0, // 4 + 0, // 5 + 0, // 6 + 0, // 7 + /*10753*/ uint16(xSetOp), uint16(MOV), + /*10755*/ uint16(xReadIb), + /*10756*/ uint16(xArgRM8), + /*10757*/ uint16(xArgImm8u), + /*10758*/ uint16(xMatch), + /*10759*/ uint16(xSetOp), uint16(XABORT), + /*10761*/ uint16(xReadIb), + /*10762*/ uint16(xArgImm8u), + /*10763*/ uint16(xMatch), + /*10764*/ uint16(xCondByte), 1, + 0xF8, 10806, + /*10768*/ uint16(xCondSlashR), + 10777, // 0 + 0, // 1 + 0, // 2 + 0, // 3 + 0, // 4 + 0, // 5 + 0, // 6 + 0, // 7 + /*10777*/ uint16(xCondIs64), 10780, 10796, + /*10780*/ uint16(xCondDataSize), 10784, 10790, 0, + /*10784*/ uint16(xSetOp), uint16(MOV), + /*10786*/ uint16(xReadIw), + /*10787*/ uint16(xArgRM16), + /*10788*/ uint16(xArgImm16), + /*10789*/ uint16(xMatch), + /*10790*/ uint16(xSetOp), uint16(MOV), + /*10792*/ uint16(xReadId), + /*10793*/ uint16(xArgRM32), + /*10794*/ uint16(xArgImm32), + /*10795*/ uint16(xMatch), + /*10796*/ uint16(xCondDataSize), 10784, 10790, 10800, + /*10800*/ uint16(xSetOp), uint16(MOV), + /*10802*/ uint16(xReadId), + /*10803*/ uint16(xArgRM64), + /*10804*/ uint16(xArgImm32), + /*10805*/ uint16(xMatch), + /*10806*/ uint16(xCondDataSize), 10810, 10815, 10820, + /*10810*/ uint16(xSetOp), uint16(XBEGIN), + /*10812*/ uint16(xReadCw), + /*10813*/ uint16(xArgRel16), + /*10814*/ uint16(xMatch), + /*10815*/ uint16(xSetOp), uint16(XBEGIN), + /*10817*/ uint16(xReadCd), + /*10818*/ uint16(xArgRel32), + /*10819*/ uint16(xMatch), + /*10820*/ uint16(xSetOp), uint16(XBEGIN), + /*10822*/ uint16(xReadCd), + /*10823*/ uint16(xArgRel32), + /*10824*/ uint16(xMatch), + /*10825*/ uint16(xSetOp), uint16(ENTER), + /*10827*/ uint16(xReadIw), + /*10828*/ uint16(xReadIb), + /*10829*/ uint16(xArgImm16u), + /*10830*/ uint16(xArgImm8u), + /*10831*/ uint16(xMatch), + /*10832*/ uint16(xCondIs64), 10835, 10845, + /*10835*/ uint16(xCondDataSize), 10839, 10842, 0, + /*10839*/ uint16(xSetOp), uint16(LEAVE), + /*10841*/ uint16(xMatch), + /*10842*/ uint16(xSetOp), uint16(LEAVE), + /*10844*/ uint16(xMatch), + /*10845*/ uint16(xCondDataSize), 10839, 10849, 10852, + /*10849*/ uint16(xSetOp), uint16(LEAVE), + /*10851*/ uint16(xMatch), + /*10852*/ uint16(xSetOp), uint16(LEAVE), + /*10854*/ uint16(xMatch), + /*10855*/ uint16(xSetOp), uint16(LRET), + /*10857*/ uint16(xReadIw), + /*10858*/ uint16(xArgImm16u), + /*10859*/ uint16(xMatch), + /*10860*/ uint16(xSetOp), uint16(LRET), + /*10862*/ uint16(xMatch), + /*10863*/ uint16(xSetOp), uint16(INT), + /*10865*/ uint16(xArg3), + /*10866*/ uint16(xMatch), + /*10867*/ uint16(xSetOp), uint16(INT), + /*10869*/ uint16(xReadIb), + /*10870*/ uint16(xArgImm8u), + /*10871*/ uint16(xMatch), + /*10872*/ uint16(xCondIs64), 10875, 0, + /*10875*/ uint16(xSetOp), uint16(INTO), + /*10877*/ uint16(xMatch), + /*10878*/ uint16(xCondIs64), 10881, 10891, + /*10881*/ uint16(xCondDataSize), 10885, 10888, 0, + /*10885*/ uint16(xSetOp), uint16(IRET), + /*10887*/ uint16(xMatch), + /*10888*/ uint16(xSetOp), uint16(IRETD), + /*10890*/ uint16(xMatch), + /*10891*/ uint16(xCondDataSize), 10885, 10888, 10895, + /*10895*/ uint16(xSetOp), uint16(IRETQ), + /*10897*/ uint16(xMatch), + /*10898*/ uint16(xCondSlashR), + 10907, // 0 + 10912, // 1 + 10917, // 2 + 10922, // 3 + 10927, // 4 + 10932, // 5 + 0, // 6 + 10937, // 7 + /*10907*/ uint16(xSetOp), uint16(ROL), + /*10909*/ uint16(xArgRM8), + /*10910*/ uint16(xArg1), + /*10911*/ uint16(xMatch), + /*10912*/ uint16(xSetOp), uint16(ROR), + /*10914*/ uint16(xArgRM8), + /*10915*/ uint16(xArg1), + /*10916*/ uint16(xMatch), + /*10917*/ uint16(xSetOp), uint16(RCL), + /*10919*/ uint16(xArgRM8), + /*10920*/ uint16(xArg1), + /*10921*/ uint16(xMatch), + /*10922*/ uint16(xSetOp), uint16(RCR), + /*10924*/ uint16(xArgRM8), + /*10925*/ uint16(xArg1), + /*10926*/ uint16(xMatch), + /*10927*/ uint16(xSetOp), uint16(SHL), + /*10929*/ uint16(xArgRM8), + /*10930*/ uint16(xArg1), + /*10931*/ uint16(xMatch), + /*10932*/ uint16(xSetOp), uint16(SHR), + /*10934*/ uint16(xArgRM8), + /*10935*/ uint16(xArg1), + /*10936*/ uint16(xMatch), + /*10937*/ uint16(xSetOp), uint16(SAR), + /*10939*/ uint16(xArgRM8), + /*10940*/ uint16(xArg1), + /*10941*/ uint16(xMatch), + /*10942*/ uint16(xCondSlashR), + 10951, // 0 + 10977, // 1 + 11003, // 2 + 11029, // 3 + 11055, // 4 + 11081, // 5 + 0, // 6 + 11107, // 7 + /*10951*/ uint16(xCondIs64), 10954, 10968, + /*10954*/ uint16(xCondDataSize), 10958, 10963, 0, + /*10958*/ uint16(xSetOp), uint16(ROL), + /*10960*/ uint16(xArgRM16), + /*10961*/ uint16(xArg1), + /*10962*/ uint16(xMatch), + /*10963*/ uint16(xSetOp), uint16(ROL), + /*10965*/ uint16(xArgRM32), + /*10966*/ uint16(xArg1), + /*10967*/ uint16(xMatch), + /*10968*/ uint16(xCondDataSize), 10958, 10963, 10972, + /*10972*/ uint16(xSetOp), uint16(ROL), + /*10974*/ uint16(xArgRM64), + /*10975*/ uint16(xArg1), + /*10976*/ uint16(xMatch), + /*10977*/ uint16(xCondIs64), 10980, 10994, + /*10980*/ uint16(xCondDataSize), 10984, 10989, 0, + /*10984*/ uint16(xSetOp), uint16(ROR), + /*10986*/ uint16(xArgRM16), + /*10987*/ uint16(xArg1), + /*10988*/ uint16(xMatch), + /*10989*/ uint16(xSetOp), uint16(ROR), + /*10991*/ uint16(xArgRM32), + /*10992*/ uint16(xArg1), + /*10993*/ uint16(xMatch), + /*10994*/ uint16(xCondDataSize), 10984, 10989, 10998, + /*10998*/ uint16(xSetOp), uint16(ROR), + /*11000*/ uint16(xArgRM64), + /*11001*/ uint16(xArg1), + /*11002*/ uint16(xMatch), + /*11003*/ uint16(xCondIs64), 11006, 11020, + /*11006*/ uint16(xCondDataSize), 11010, 11015, 0, + /*11010*/ uint16(xSetOp), uint16(RCL), + /*11012*/ uint16(xArgRM16), + /*11013*/ uint16(xArg1), + /*11014*/ uint16(xMatch), + /*11015*/ uint16(xSetOp), uint16(RCL), + /*11017*/ uint16(xArgRM32), + /*11018*/ uint16(xArg1), + /*11019*/ uint16(xMatch), + /*11020*/ uint16(xCondDataSize), 11010, 11015, 11024, + /*11024*/ uint16(xSetOp), uint16(RCL), + /*11026*/ uint16(xArgRM64), + /*11027*/ uint16(xArg1), + /*11028*/ uint16(xMatch), + /*11029*/ uint16(xCondIs64), 11032, 11046, + /*11032*/ uint16(xCondDataSize), 11036, 11041, 0, + /*11036*/ uint16(xSetOp), uint16(RCR), + /*11038*/ uint16(xArgRM16), + /*11039*/ uint16(xArg1), + /*11040*/ uint16(xMatch), + /*11041*/ uint16(xSetOp), uint16(RCR), + /*11043*/ uint16(xArgRM32), + /*11044*/ uint16(xArg1), + /*11045*/ uint16(xMatch), + /*11046*/ uint16(xCondDataSize), 11036, 11041, 11050, + /*11050*/ uint16(xSetOp), uint16(RCR), + /*11052*/ uint16(xArgRM64), + /*11053*/ uint16(xArg1), + /*11054*/ uint16(xMatch), + /*11055*/ uint16(xCondIs64), 11058, 11072, + /*11058*/ uint16(xCondDataSize), 11062, 11067, 0, + /*11062*/ uint16(xSetOp), uint16(SHL), + /*11064*/ uint16(xArgRM16), + /*11065*/ uint16(xArg1), + /*11066*/ uint16(xMatch), + /*11067*/ uint16(xSetOp), uint16(SHL), + /*11069*/ uint16(xArgRM32), + /*11070*/ uint16(xArg1), + /*11071*/ uint16(xMatch), + /*11072*/ uint16(xCondDataSize), 11062, 11067, 11076, + /*11076*/ uint16(xSetOp), uint16(SHL), + /*11078*/ uint16(xArgRM64), + /*11079*/ uint16(xArg1), + /*11080*/ uint16(xMatch), + /*11081*/ uint16(xCondIs64), 11084, 11098, + /*11084*/ uint16(xCondDataSize), 11088, 11093, 0, + /*11088*/ uint16(xSetOp), uint16(SHR), + /*11090*/ uint16(xArgRM16), + /*11091*/ uint16(xArg1), + /*11092*/ uint16(xMatch), + /*11093*/ uint16(xSetOp), uint16(SHR), + /*11095*/ uint16(xArgRM32), + /*11096*/ uint16(xArg1), + /*11097*/ uint16(xMatch), + /*11098*/ uint16(xCondDataSize), 11088, 11093, 11102, + /*11102*/ uint16(xSetOp), uint16(SHR), + /*11104*/ uint16(xArgRM64), + /*11105*/ uint16(xArg1), + /*11106*/ uint16(xMatch), + /*11107*/ uint16(xCondIs64), 11110, 11124, + /*11110*/ uint16(xCondDataSize), 11114, 11119, 0, + /*11114*/ uint16(xSetOp), uint16(SAR), + /*11116*/ uint16(xArgRM16), + /*11117*/ uint16(xArg1), + /*11118*/ uint16(xMatch), + /*11119*/ uint16(xSetOp), uint16(SAR), + /*11121*/ uint16(xArgRM32), + /*11122*/ uint16(xArg1), + /*11123*/ uint16(xMatch), + /*11124*/ uint16(xCondDataSize), 11114, 11119, 11128, + /*11128*/ uint16(xSetOp), uint16(SAR), + /*11130*/ uint16(xArgRM64), + /*11131*/ uint16(xArg1), + /*11132*/ uint16(xMatch), + /*11133*/ uint16(xCondSlashR), + 11142, // 0 + 11147, // 1 + 11152, // 2 + 11157, // 3 + 11162, // 4 + 11167, // 5 + 0, // 6 + 11172, // 7 + /*11142*/ uint16(xSetOp), uint16(ROL), + /*11144*/ uint16(xArgRM8), + /*11145*/ uint16(xArgCL), + /*11146*/ uint16(xMatch), + /*11147*/ uint16(xSetOp), uint16(ROR), + /*11149*/ uint16(xArgRM8), + /*11150*/ uint16(xArgCL), + /*11151*/ uint16(xMatch), + /*11152*/ uint16(xSetOp), uint16(RCL), + /*11154*/ uint16(xArgRM8), + /*11155*/ uint16(xArgCL), + /*11156*/ uint16(xMatch), + /*11157*/ uint16(xSetOp), uint16(RCR), + /*11159*/ uint16(xArgRM8), + /*11160*/ uint16(xArgCL), + /*11161*/ uint16(xMatch), + /*11162*/ uint16(xSetOp), uint16(SHL), + /*11164*/ uint16(xArgRM8), + /*11165*/ uint16(xArgCL), + /*11166*/ uint16(xMatch), + /*11167*/ uint16(xSetOp), uint16(SHR), + /*11169*/ uint16(xArgRM8), + /*11170*/ uint16(xArgCL), + /*11171*/ uint16(xMatch), + /*11172*/ uint16(xSetOp), uint16(SAR), + /*11174*/ uint16(xArgRM8), + /*11175*/ uint16(xArgCL), + /*11176*/ uint16(xMatch), + /*11177*/ uint16(xCondSlashR), + 11186, // 0 + 11212, // 1 + 11238, // 2 + 11264, // 3 + 11290, // 4 + 11316, // 5 + 0, // 6 + 11342, // 7 + /*11186*/ uint16(xCondIs64), 11189, 11203, + /*11189*/ uint16(xCondDataSize), 11193, 11198, 0, + /*11193*/ uint16(xSetOp), uint16(ROL), + /*11195*/ uint16(xArgRM16), + /*11196*/ uint16(xArgCL), + /*11197*/ uint16(xMatch), + /*11198*/ uint16(xSetOp), uint16(ROL), + /*11200*/ uint16(xArgRM32), + /*11201*/ uint16(xArgCL), + /*11202*/ uint16(xMatch), + /*11203*/ uint16(xCondDataSize), 11193, 11198, 11207, + /*11207*/ uint16(xSetOp), uint16(ROL), + /*11209*/ uint16(xArgRM64), + /*11210*/ uint16(xArgCL), + /*11211*/ uint16(xMatch), + /*11212*/ uint16(xCondIs64), 11215, 11229, + /*11215*/ uint16(xCondDataSize), 11219, 11224, 0, + /*11219*/ uint16(xSetOp), uint16(ROR), + /*11221*/ uint16(xArgRM16), + /*11222*/ uint16(xArgCL), + /*11223*/ uint16(xMatch), + /*11224*/ uint16(xSetOp), uint16(ROR), + /*11226*/ uint16(xArgRM32), + /*11227*/ uint16(xArgCL), + /*11228*/ uint16(xMatch), + /*11229*/ uint16(xCondDataSize), 11219, 11224, 11233, + /*11233*/ uint16(xSetOp), uint16(ROR), + /*11235*/ uint16(xArgRM64), + /*11236*/ uint16(xArgCL), + /*11237*/ uint16(xMatch), + /*11238*/ uint16(xCondIs64), 11241, 11255, + /*11241*/ uint16(xCondDataSize), 11245, 11250, 0, + /*11245*/ uint16(xSetOp), uint16(RCL), + /*11247*/ uint16(xArgRM16), + /*11248*/ uint16(xArgCL), + /*11249*/ uint16(xMatch), + /*11250*/ uint16(xSetOp), uint16(RCL), + /*11252*/ uint16(xArgRM32), + /*11253*/ uint16(xArgCL), + /*11254*/ uint16(xMatch), + /*11255*/ uint16(xCondDataSize), 11245, 11250, 11259, + /*11259*/ uint16(xSetOp), uint16(RCL), + /*11261*/ uint16(xArgRM64), + /*11262*/ uint16(xArgCL), + /*11263*/ uint16(xMatch), + /*11264*/ uint16(xCondIs64), 11267, 11281, + /*11267*/ uint16(xCondDataSize), 11271, 11276, 0, + /*11271*/ uint16(xSetOp), uint16(RCR), + /*11273*/ uint16(xArgRM16), + /*11274*/ uint16(xArgCL), + /*11275*/ uint16(xMatch), + /*11276*/ uint16(xSetOp), uint16(RCR), + /*11278*/ uint16(xArgRM32), + /*11279*/ uint16(xArgCL), + /*11280*/ uint16(xMatch), + /*11281*/ uint16(xCondDataSize), 11271, 11276, 11285, + /*11285*/ uint16(xSetOp), uint16(RCR), + /*11287*/ uint16(xArgRM64), + /*11288*/ uint16(xArgCL), + /*11289*/ uint16(xMatch), + /*11290*/ uint16(xCondIs64), 11293, 11307, + /*11293*/ uint16(xCondDataSize), 11297, 11302, 0, + /*11297*/ uint16(xSetOp), uint16(SHL), + /*11299*/ uint16(xArgRM16), + /*11300*/ uint16(xArgCL), + /*11301*/ uint16(xMatch), + /*11302*/ uint16(xSetOp), uint16(SHL), + /*11304*/ uint16(xArgRM32), + /*11305*/ uint16(xArgCL), + /*11306*/ uint16(xMatch), + /*11307*/ uint16(xCondDataSize), 11297, 11302, 11311, + /*11311*/ uint16(xSetOp), uint16(SHL), + /*11313*/ uint16(xArgRM64), + /*11314*/ uint16(xArgCL), + /*11315*/ uint16(xMatch), + /*11316*/ uint16(xCondIs64), 11319, 11333, + /*11319*/ uint16(xCondDataSize), 11323, 11328, 0, + /*11323*/ uint16(xSetOp), uint16(SHR), + /*11325*/ uint16(xArgRM16), + /*11326*/ uint16(xArgCL), + /*11327*/ uint16(xMatch), + /*11328*/ uint16(xSetOp), uint16(SHR), + /*11330*/ uint16(xArgRM32), + /*11331*/ uint16(xArgCL), + /*11332*/ uint16(xMatch), + /*11333*/ uint16(xCondDataSize), 11323, 11328, 11337, + /*11337*/ uint16(xSetOp), uint16(SHR), + /*11339*/ uint16(xArgRM64), + /*11340*/ uint16(xArgCL), + /*11341*/ uint16(xMatch), + /*11342*/ uint16(xCondIs64), 11345, 11359, + /*11345*/ uint16(xCondDataSize), 11349, 11354, 0, + /*11349*/ uint16(xSetOp), uint16(SAR), + /*11351*/ uint16(xArgRM16), + /*11352*/ uint16(xArgCL), + /*11353*/ uint16(xMatch), + /*11354*/ uint16(xSetOp), uint16(SAR), + /*11356*/ uint16(xArgRM32), + /*11357*/ uint16(xArgCL), + /*11358*/ uint16(xMatch), + /*11359*/ uint16(xCondDataSize), 11349, 11354, 11363, + /*11363*/ uint16(xSetOp), uint16(SAR), + /*11365*/ uint16(xArgRM64), + /*11366*/ uint16(xArgCL), + /*11367*/ uint16(xMatch), + /*11368*/ uint16(xCondIs64), 11371, 0, + /*11371*/ uint16(xSetOp), uint16(AAM), + /*11373*/ uint16(xReadIb), + /*11374*/ uint16(xArgImm8u), + /*11375*/ uint16(xMatch), + /*11376*/ uint16(xCondIs64), 11379, 0, + /*11379*/ uint16(xSetOp), uint16(AAD), + /*11381*/ uint16(xReadIb), + /*11382*/ uint16(xArgImm8u), + /*11383*/ uint16(xMatch), + /*11384*/ uint16(xCondIs64), 11387, 11390, + /*11387*/ uint16(xSetOp), uint16(XLATB), + /*11389*/ uint16(xMatch), + /*11390*/ uint16(xCondDataSize), 11387, 11387, 11394, + /*11394*/ uint16(xSetOp), uint16(XLATB), + /*11396*/ uint16(xMatch), + /*11397*/ uint16(xCondByte), 64, + 0xc0, 11568, + 0xc1, 11568, + 0xc2, 11568, + 0xc3, 11568, + 0xc4, 11568, + 0xc5, 11568, + 0xc6, 11568, + 0xc7, 11568, + 0xc8, 11573, + 0xc9, 11573, + 0xca, 11573, + 0xcb, 11573, + 0xcc, 11573, + 0xcd, 11573, + 0xce, 11573, + 0xcf, 11573, + 0xd0, 11578, + 0xd1, 11578, + 0xd2, 11578, + 0xd3, 11578, + 0xd4, 11578, + 0xd5, 11578, + 0xd6, 11578, + 0xd7, 11578, + 0xd8, 11582, + 0xd9, 11582, + 0xda, 11582, + 0xdb, 11582, + 0xdc, 11582, + 0xdd, 11582, + 0xde, 11582, + 0xdf, 11582, + 0xe0, 11586, + 0xe1, 11586, + 0xe2, 11586, + 0xe3, 11586, + 0xe4, 11586, + 0xe5, 11586, + 0xe6, 11586, + 0xe7, 11586, + 0xe8, 11591, + 0xe9, 11591, + 0xea, 11591, + 0xeb, 11591, + 0xec, 11591, + 0xed, 11591, + 0xee, 11591, + 0xef, 11591, + 0xf0, 11596, + 0xf1, 11596, + 0xf2, 11596, + 0xf3, 11596, + 0xf4, 11596, + 0xf5, 11596, + 0xf6, 11596, + 0xf7, 11596, + 0xf8, 11601, + 0xf9, 11601, + 0xfa, 11601, + 0xfb, 11601, + 0xfc, 11601, + 0xfd, 11601, + 0xfe, 11601, + 0xff, 11601, + /*11527*/ uint16(xCondSlashR), + 11536, // 0 + 11540, // 1 + 11544, // 2 + 11548, // 3 + 11552, // 4 + 11556, // 5 + 11560, // 6 + 11564, // 7 + /*11536*/ uint16(xSetOp), uint16(FADD), + /*11538*/ uint16(xArgM32fp), + /*11539*/ uint16(xMatch), + /*11540*/ uint16(xSetOp), uint16(FMUL), + /*11542*/ uint16(xArgM32fp), + /*11543*/ uint16(xMatch), + /*11544*/ uint16(xSetOp), uint16(FCOM), + /*11546*/ uint16(xArgM32fp), + /*11547*/ uint16(xMatch), + /*11548*/ uint16(xSetOp), uint16(FCOMP), + /*11550*/ uint16(xArgM32fp), + /*11551*/ uint16(xMatch), + /*11552*/ uint16(xSetOp), uint16(FSUB), + /*11554*/ uint16(xArgM32fp), + /*11555*/ uint16(xMatch), + /*11556*/ uint16(xSetOp), uint16(FSUBR), + /*11558*/ uint16(xArgM32fp), + /*11559*/ uint16(xMatch), + /*11560*/ uint16(xSetOp), uint16(FDIV), + /*11562*/ uint16(xArgM32fp), + /*11563*/ uint16(xMatch), + /*11564*/ uint16(xSetOp), uint16(FDIVR), + /*11566*/ uint16(xArgM32fp), + /*11567*/ uint16(xMatch), + /*11568*/ uint16(xSetOp), uint16(FADD), + /*11570*/ uint16(xArgST), + /*11571*/ uint16(xArgSTi), + /*11572*/ uint16(xMatch), + /*11573*/ uint16(xSetOp), uint16(FMUL), + /*11575*/ uint16(xArgST), + /*11576*/ uint16(xArgSTi), + /*11577*/ uint16(xMatch), + /*11578*/ uint16(xSetOp), uint16(FCOM), + /*11580*/ uint16(xArgSTi), + /*11581*/ uint16(xMatch), + /*11582*/ uint16(xSetOp), uint16(FCOMP), + /*11584*/ uint16(xArgSTi), + /*11585*/ uint16(xMatch), + /*11586*/ uint16(xSetOp), uint16(FSUB), + /*11588*/ uint16(xArgST), + /*11589*/ uint16(xArgSTi), + /*11590*/ uint16(xMatch), + /*11591*/ uint16(xSetOp), uint16(FSUBR), + /*11593*/ uint16(xArgST), + /*11594*/ uint16(xArgSTi), + /*11595*/ uint16(xMatch), + /*11596*/ uint16(xSetOp), uint16(FDIV), + /*11598*/ uint16(xArgST), + /*11599*/ uint16(xArgSTi), + /*11600*/ uint16(xMatch), + /*11601*/ uint16(xSetOp), uint16(FDIVR), + /*11603*/ uint16(xArgST), + /*11604*/ uint16(xArgSTi), + /*11605*/ uint16(xMatch), + /*11606*/ uint16(xCondByte), 42, + 0xc0, 11729, + 0xc1, 11729, + 0xc2, 11729, + 0xc3, 11729, + 0xc4, 11729, + 0xc5, 11729, + 0xc6, 11729, + 0xc7, 11729, + 0xc8, 11733, + 0xc9, 11733, + 0xca, 11733, + 0xcb, 11733, + 0xcc, 11733, + 0xcd, 11733, + 0xce, 11733, + 0xcf, 11733, + 0xD0, 11737, + 0xE0, 11740, + 0xE1, 11743, + 0xE4, 11746, + 0xE5, 11749, + 0xE8, 11752, + 0xE9, 11755, + 0xEA, 11758, + 0xEB, 11761, + 0xEC, 11764, + 0xF0, 11767, + 0xF1, 11770, + 0xF2, 11773, + 0xF3, 11776, + 0xF4, 11779, + 0xF5, 11782, + 0xF6, 11785, + 0xF7, 11788, + 0xF8, 11791, + 0xF9, 11794, + 0xFA, 11797, + 0xFB, 11800, + 0xFC, 11803, + 0xFD, 11806, + 0xFE, 11809, + 0xFF, 11812, + /*11692*/ uint16(xCondSlashR), + 11701, // 0 + 0, // 1 + 11705, // 2 + 11709, // 3 + 11713, // 4 + 11717, // 5 + 11721, // 6 + 11725, // 7 + /*11701*/ uint16(xSetOp), uint16(FLD), + /*11703*/ uint16(xArgM32fp), + /*11704*/ uint16(xMatch), + /*11705*/ uint16(xSetOp), uint16(FST), + /*11707*/ uint16(xArgM32fp), + /*11708*/ uint16(xMatch), + /*11709*/ uint16(xSetOp), uint16(FSTP), + /*11711*/ uint16(xArgM32fp), + /*11712*/ uint16(xMatch), + /*11713*/ uint16(xSetOp), uint16(FLDENV), + /*11715*/ uint16(xArgM1428byte), + /*11716*/ uint16(xMatch), + /*11717*/ uint16(xSetOp), uint16(FLDCW), + /*11719*/ uint16(xArgM2byte), + /*11720*/ uint16(xMatch), + /*11721*/ uint16(xSetOp), uint16(FNSTENV), + /*11723*/ uint16(xArgM1428byte), + /*11724*/ uint16(xMatch), + /*11725*/ uint16(xSetOp), uint16(FNSTCW), + /*11727*/ uint16(xArgM2byte), + /*11728*/ uint16(xMatch), + /*11729*/ uint16(xSetOp), uint16(FLD), + /*11731*/ uint16(xArgSTi), + /*11732*/ uint16(xMatch), + /*11733*/ uint16(xSetOp), uint16(FXCH), + /*11735*/ uint16(xArgSTi), + /*11736*/ uint16(xMatch), + /*11737*/ uint16(xSetOp), uint16(FNOP), + /*11739*/ uint16(xMatch), + /*11740*/ uint16(xSetOp), uint16(FCHS), + /*11742*/ uint16(xMatch), + /*11743*/ uint16(xSetOp), uint16(FABS), + /*11745*/ uint16(xMatch), + /*11746*/ uint16(xSetOp), uint16(FTST), + /*11748*/ uint16(xMatch), + /*11749*/ uint16(xSetOp), uint16(FXAM), + /*11751*/ uint16(xMatch), + /*11752*/ uint16(xSetOp), uint16(FLD1), + /*11754*/ uint16(xMatch), + /*11755*/ uint16(xSetOp), uint16(FLDL2T), + /*11757*/ uint16(xMatch), + /*11758*/ uint16(xSetOp), uint16(FLDL2E), + /*11760*/ uint16(xMatch), + /*11761*/ uint16(xSetOp), uint16(FLDPI), + /*11763*/ uint16(xMatch), + /*11764*/ uint16(xSetOp), uint16(FLDLG2), + /*11766*/ uint16(xMatch), + /*11767*/ uint16(xSetOp), uint16(F2XM1), + /*11769*/ uint16(xMatch), + /*11770*/ uint16(xSetOp), uint16(FYL2X), + /*11772*/ uint16(xMatch), + /*11773*/ uint16(xSetOp), uint16(FPTAN), + /*11775*/ uint16(xMatch), + /*11776*/ uint16(xSetOp), uint16(FPATAN), + /*11778*/ uint16(xMatch), + /*11779*/ uint16(xSetOp), uint16(FXTRACT), + /*11781*/ uint16(xMatch), + /*11782*/ uint16(xSetOp), uint16(FPREM1), + /*11784*/ uint16(xMatch), + /*11785*/ uint16(xSetOp), uint16(FDECSTP), + /*11787*/ uint16(xMatch), + /*11788*/ uint16(xSetOp), uint16(FINCSTP), + /*11790*/ uint16(xMatch), + /*11791*/ uint16(xSetOp), uint16(FPREM), + /*11793*/ uint16(xMatch), + /*11794*/ uint16(xSetOp), uint16(FYL2XP1), + /*11796*/ uint16(xMatch), + /*11797*/ uint16(xSetOp), uint16(FSQRT), + /*11799*/ uint16(xMatch), + /*11800*/ uint16(xSetOp), uint16(FSINCOS), + /*11802*/ uint16(xMatch), + /*11803*/ uint16(xSetOp), uint16(FRNDINT), + /*11805*/ uint16(xMatch), + /*11806*/ uint16(xSetOp), uint16(FSCALE), + /*11808*/ uint16(xMatch), + /*11809*/ uint16(xSetOp), uint16(FSIN), + /*11811*/ uint16(xMatch), + /*11812*/ uint16(xSetOp), uint16(FCOS), + /*11814*/ uint16(xMatch), + /*11815*/ uint16(xCondByte), 33, + 0xc0, 11924, + 0xc1, 11924, + 0xc2, 11924, + 0xc3, 11924, + 0xc4, 11924, + 0xc5, 11924, + 0xc6, 11924, + 0xc7, 11924, + 0xc8, 11929, + 0xc9, 11929, + 0xca, 11929, + 0xcb, 11929, + 0xcc, 11929, + 0xcd, 11929, + 0xce, 11929, + 0xcf, 11929, + 0xd0, 11934, + 0xd1, 11934, + 0xd2, 11934, + 0xd3, 11934, + 0xd4, 11934, + 0xd5, 11934, + 0xd6, 11934, + 0xd7, 11934, + 0xd8, 11939, + 0xd9, 11939, + 0xda, 11939, + 0xdb, 11939, + 0xdc, 11939, + 0xdd, 11939, + 0xde, 11939, + 0xdf, 11939, + 0xE9, 11944, + /*11883*/ uint16(xCondSlashR), + 11892, // 0 + 11896, // 1 + 11900, // 2 + 11904, // 3 + 11908, // 4 + 11912, // 5 + 11916, // 6 + 11920, // 7 + /*11892*/ uint16(xSetOp), uint16(FIADD), + /*11894*/ uint16(xArgM32int), + /*11895*/ uint16(xMatch), + /*11896*/ uint16(xSetOp), uint16(FIMUL), + /*11898*/ uint16(xArgM32int), + /*11899*/ uint16(xMatch), + /*11900*/ uint16(xSetOp), uint16(FICOM), + /*11902*/ uint16(xArgM32int), + /*11903*/ uint16(xMatch), + /*11904*/ uint16(xSetOp), uint16(FICOMP), + /*11906*/ uint16(xArgM32int), + /*11907*/ uint16(xMatch), + /*11908*/ uint16(xSetOp), uint16(FISUB), + /*11910*/ uint16(xArgM32int), + /*11911*/ uint16(xMatch), + /*11912*/ uint16(xSetOp), uint16(FISUBR), + /*11914*/ uint16(xArgM32int), + /*11915*/ uint16(xMatch), + /*11916*/ uint16(xSetOp), uint16(FIDIV), + /*11918*/ uint16(xArgM32int), + /*11919*/ uint16(xMatch), + /*11920*/ uint16(xSetOp), uint16(FIDIVR), + /*11922*/ uint16(xArgM32int), + /*11923*/ uint16(xMatch), + /*11924*/ uint16(xSetOp), uint16(FCMOVB), + /*11926*/ uint16(xArgST), + /*11927*/ uint16(xArgSTi), + /*11928*/ uint16(xMatch), + /*11929*/ uint16(xSetOp), uint16(FCMOVE), + /*11931*/ uint16(xArgST), + /*11932*/ uint16(xArgSTi), + /*11933*/ uint16(xMatch), + /*11934*/ uint16(xSetOp), uint16(FCMOVBE), + /*11936*/ uint16(xArgST), + /*11937*/ uint16(xArgSTi), + /*11938*/ uint16(xMatch), + /*11939*/ uint16(xSetOp), uint16(FCMOVU), + /*11941*/ uint16(xArgST), + /*11942*/ uint16(xArgSTi), + /*11943*/ uint16(xMatch), + /*11944*/ uint16(xSetOp), uint16(FUCOMPP), + /*11946*/ uint16(xMatch), + /*11947*/ uint16(xCondByte), 50, + 0xc0, 12082, + 0xc1, 12082, + 0xc2, 12082, + 0xc3, 12082, + 0xc4, 12082, + 0xc5, 12082, + 0xc6, 12082, + 0xc7, 12082, + 0xc8, 12087, + 0xc9, 12087, + 0xca, 12087, + 0xcb, 12087, + 0xcc, 12087, + 0xcd, 12087, + 0xce, 12087, + 0xcf, 12087, + 0xd0, 12092, + 0xd1, 12092, + 0xd2, 12092, + 0xd3, 12092, + 0xd4, 12092, + 0xd5, 12092, + 0xd6, 12092, + 0xd7, 12092, + 0xd8, 12097, + 0xd9, 12097, + 0xda, 12097, + 0xdb, 12097, + 0xdc, 12097, + 0xdd, 12097, + 0xde, 12097, + 0xdf, 12097, + 0xE2, 12102, + 0xE3, 12105, + 0xe8, 12108, + 0xe9, 12108, + 0xea, 12108, + 0xeb, 12108, + 0xec, 12108, + 0xed, 12108, + 0xee, 12108, + 0xef, 12108, + 0xf0, 12113, + 0xf1, 12113, + 0xf2, 12113, + 0xf3, 12113, + 0xf4, 12113, + 0xf5, 12113, + 0xf6, 12113, + 0xf7, 12113, + /*12049*/ uint16(xCondSlashR), + 12058, // 0 + 12062, // 1 + 12066, // 2 + 12070, // 3 + 0, // 4 + 12074, // 5 + 0, // 6 + 12078, // 7 + /*12058*/ uint16(xSetOp), uint16(FILD), + /*12060*/ uint16(xArgM32int), + /*12061*/ uint16(xMatch), + /*12062*/ uint16(xSetOp), uint16(FISTTP), + /*12064*/ uint16(xArgM32int), + /*12065*/ uint16(xMatch), + /*12066*/ uint16(xSetOp), uint16(FIST), + /*12068*/ uint16(xArgM32int), + /*12069*/ uint16(xMatch), + /*12070*/ uint16(xSetOp), uint16(FISTP), + /*12072*/ uint16(xArgM32int), + /*12073*/ uint16(xMatch), + /*12074*/ uint16(xSetOp), uint16(FLD), + /*12076*/ uint16(xArgM80fp), + /*12077*/ uint16(xMatch), + /*12078*/ uint16(xSetOp), uint16(FSTP), + /*12080*/ uint16(xArgM80fp), + /*12081*/ uint16(xMatch), + /*12082*/ uint16(xSetOp), uint16(FCMOVNB), + /*12084*/ uint16(xArgST), + /*12085*/ uint16(xArgSTi), + /*12086*/ uint16(xMatch), + /*12087*/ uint16(xSetOp), uint16(FCMOVNE), + /*12089*/ uint16(xArgST), + /*12090*/ uint16(xArgSTi), + /*12091*/ uint16(xMatch), + /*12092*/ uint16(xSetOp), uint16(FCMOVNBE), + /*12094*/ uint16(xArgST), + /*12095*/ uint16(xArgSTi), + /*12096*/ uint16(xMatch), + /*12097*/ uint16(xSetOp), uint16(FCMOVNU), + /*12099*/ uint16(xArgST), + /*12100*/ uint16(xArgSTi), + /*12101*/ uint16(xMatch), + /*12102*/ uint16(xSetOp), uint16(FNCLEX), + /*12104*/ uint16(xMatch), + /*12105*/ uint16(xSetOp), uint16(FNINIT), + /*12107*/ uint16(xMatch), + /*12108*/ uint16(xSetOp), uint16(FUCOMI), + /*12110*/ uint16(xArgST), + /*12111*/ uint16(xArgSTi), + /*12112*/ uint16(xMatch), + /*12113*/ uint16(xSetOp), uint16(FCOMI), + /*12115*/ uint16(xArgST), + /*12116*/ uint16(xArgSTi), + /*12117*/ uint16(xMatch), + /*12118*/ uint16(xCondByte), 48, + 0xc0, 12257, + 0xc1, 12257, + 0xc2, 12257, + 0xc3, 12257, + 0xc4, 12257, + 0xc5, 12257, + 0xc6, 12257, + 0xc7, 12257, + 0xc8, 12262, + 0xc9, 12262, + 0xca, 12262, + 0xcb, 12262, + 0xcc, 12262, + 0xcd, 12262, + 0xce, 12262, + 0xcf, 12262, + 0xe0, 12267, + 0xe1, 12267, + 0xe2, 12267, + 0xe3, 12267, + 0xe4, 12267, + 0xe5, 12267, + 0xe6, 12267, + 0xe7, 12267, + 0xe8, 12272, + 0xe9, 12272, + 0xea, 12272, + 0xeb, 12272, + 0xec, 12272, + 0xed, 12272, + 0xee, 12272, + 0xef, 12272, + 0xf0, 12277, + 0xf1, 12277, + 0xf2, 12277, + 0xf3, 12277, + 0xf4, 12277, + 0xf5, 12277, + 0xf6, 12277, + 0xf7, 12277, + 0xf8, 12282, + 0xf9, 12282, + 0xfa, 12282, + 0xfb, 12282, + 0xfc, 12282, + 0xfd, 12282, + 0xfe, 12282, + 0xff, 12282, + /*12216*/ uint16(xCondSlashR), + 12225, // 0 + 12229, // 1 + 12233, // 2 + 12237, // 3 + 12241, // 4 + 12245, // 5 + 12249, // 6 + 12253, // 7 + /*12225*/ uint16(xSetOp), uint16(FADD), + /*12227*/ uint16(xArgM64fp), + /*12228*/ uint16(xMatch), + /*12229*/ uint16(xSetOp), uint16(FMUL), + /*12231*/ uint16(xArgM64fp), + /*12232*/ uint16(xMatch), + /*12233*/ uint16(xSetOp), uint16(FCOM), + /*12235*/ uint16(xArgM64fp), + /*12236*/ uint16(xMatch), + /*12237*/ uint16(xSetOp), uint16(FCOMP), + /*12239*/ uint16(xArgM64fp), + /*12240*/ uint16(xMatch), + /*12241*/ uint16(xSetOp), uint16(FSUB), + /*12243*/ uint16(xArgM64fp), + /*12244*/ uint16(xMatch), + /*12245*/ uint16(xSetOp), uint16(FSUBR), + /*12247*/ uint16(xArgM64fp), + /*12248*/ uint16(xMatch), + /*12249*/ uint16(xSetOp), uint16(FDIV), + /*12251*/ uint16(xArgM64fp), + /*12252*/ uint16(xMatch), + /*12253*/ uint16(xSetOp), uint16(FDIVR), + /*12255*/ uint16(xArgM64fp), + /*12256*/ uint16(xMatch), + /*12257*/ uint16(xSetOp), uint16(FADD), + /*12259*/ uint16(xArgSTi), + /*12260*/ uint16(xArgST), + /*12261*/ uint16(xMatch), + /*12262*/ uint16(xSetOp), uint16(FMUL), + /*12264*/ uint16(xArgSTi), + /*12265*/ uint16(xArgST), + /*12266*/ uint16(xMatch), + /*12267*/ uint16(xSetOp), uint16(FSUBR), + /*12269*/ uint16(xArgSTi), + /*12270*/ uint16(xArgST), + /*12271*/ uint16(xMatch), + /*12272*/ uint16(xSetOp), uint16(FSUB), + /*12274*/ uint16(xArgSTi), + /*12275*/ uint16(xArgST), + /*12276*/ uint16(xMatch), + /*12277*/ uint16(xSetOp), uint16(FDIVR), + /*12279*/ uint16(xArgSTi), + /*12280*/ uint16(xArgST), + /*12281*/ uint16(xMatch), + /*12282*/ uint16(xSetOp), uint16(FDIV), + /*12284*/ uint16(xArgSTi), + /*12285*/ uint16(xArgST), + /*12286*/ uint16(xMatch), + /*12287*/ uint16(xCondByte), 40, + 0xc0, 12406, + 0xc1, 12406, + 0xc2, 12406, + 0xc3, 12406, + 0xc4, 12406, + 0xc5, 12406, + 0xc6, 12406, + 0xc7, 12406, + 0xd0, 12410, + 0xd1, 12410, + 0xd2, 12410, + 0xd3, 12410, + 0xd4, 12410, + 0xd5, 12410, + 0xd6, 12410, + 0xd7, 12410, + 0xd8, 12414, + 0xd9, 12414, + 0xda, 12414, + 0xdb, 12414, + 0xdc, 12414, + 0xdd, 12414, + 0xde, 12414, + 0xdf, 12414, + 0xe0, 12418, + 0xe1, 12418, + 0xe2, 12418, + 0xe3, 12418, + 0xe4, 12418, + 0xe5, 12418, + 0xe6, 12418, + 0xe7, 12418, + 0xe8, 12422, + 0xe9, 12422, + 0xea, 12422, + 0xeb, 12422, + 0xec, 12422, + 0xed, 12422, + 0xee, 12422, + 0xef, 12422, + /*12369*/ uint16(xCondSlashR), + 12378, // 0 + 12382, // 1 + 12386, // 2 + 12390, // 3 + 12394, // 4 + 0, // 5 + 12398, // 6 + 12402, // 7 + /*12378*/ uint16(xSetOp), uint16(FLD), + /*12380*/ uint16(xArgM64fp), + /*12381*/ uint16(xMatch), + /*12382*/ uint16(xSetOp), uint16(FISTTP), + /*12384*/ uint16(xArgM64int), + /*12385*/ uint16(xMatch), + /*12386*/ uint16(xSetOp), uint16(FST), + /*12388*/ uint16(xArgM64fp), + /*12389*/ uint16(xMatch), + /*12390*/ uint16(xSetOp), uint16(FSTP), + /*12392*/ uint16(xArgM64fp), + /*12393*/ uint16(xMatch), + /*12394*/ uint16(xSetOp), uint16(FRSTOR), + /*12396*/ uint16(xArgM94108byte), + /*12397*/ uint16(xMatch), + /*12398*/ uint16(xSetOp), uint16(FNSAVE), + /*12400*/ uint16(xArgM94108byte), + /*12401*/ uint16(xMatch), + /*12402*/ uint16(xSetOp), uint16(FNSTSW), + /*12404*/ uint16(xArgM2byte), + /*12405*/ uint16(xMatch), + /*12406*/ uint16(xSetOp), uint16(FFREE), + /*12408*/ uint16(xArgSTi), + /*12409*/ uint16(xMatch), + /*12410*/ uint16(xSetOp), uint16(FST), + /*12412*/ uint16(xArgSTi), + /*12413*/ uint16(xMatch), + /*12414*/ uint16(xSetOp), uint16(FSTP), + /*12416*/ uint16(xArgSTi), + /*12417*/ uint16(xMatch), + /*12418*/ uint16(xSetOp), uint16(FUCOM), + /*12420*/ uint16(xArgSTi), + /*12421*/ uint16(xMatch), + /*12422*/ uint16(xSetOp), uint16(FUCOMP), + /*12424*/ uint16(xArgSTi), + /*12425*/ uint16(xMatch), + /*12426*/ uint16(xCondByte), 49, + 0xc0, 12567, + 0xc1, 12567, + 0xc2, 12567, + 0xc3, 12567, + 0xc4, 12567, + 0xc5, 12567, + 0xc6, 12567, + 0xc7, 12567, + 0xc8, 12572, + 0xc9, 12572, + 0xca, 12572, + 0xcb, 12572, + 0xcc, 12572, + 0xcd, 12572, + 0xce, 12572, + 0xcf, 12572, + 0xD9, 12577, + 0xe0, 12580, + 0xe1, 12580, + 0xe2, 12580, + 0xe3, 12580, + 0xe4, 12580, + 0xe5, 12580, + 0xe6, 12580, + 0xe7, 12580, + 0xe8, 12585, + 0xe9, 12585, + 0xea, 12585, + 0xeb, 12585, + 0xec, 12585, + 0xed, 12585, + 0xee, 12585, + 0xef, 12585, + 0xf0, 12590, + 0xf1, 12590, + 0xf2, 12590, + 0xf3, 12590, + 0xf4, 12590, + 0xf5, 12590, + 0xf6, 12590, + 0xf7, 12590, + 0xf8, 12595, + 0xf9, 12595, + 0xfa, 12595, + 0xfb, 12595, + 0xfc, 12595, + 0xfd, 12595, + 0xfe, 12595, + 0xff, 12595, + /*12526*/ uint16(xCondSlashR), + 12535, // 0 + 12539, // 1 + 12543, // 2 + 12547, // 3 + 12551, // 4 + 12555, // 5 + 12559, // 6 + 12563, // 7 + /*12535*/ uint16(xSetOp), uint16(FIADD), + /*12537*/ uint16(xArgM16int), + /*12538*/ uint16(xMatch), + /*12539*/ uint16(xSetOp), uint16(FIMUL), + /*12541*/ uint16(xArgM16int), + /*12542*/ uint16(xMatch), + /*12543*/ uint16(xSetOp), uint16(FICOM), + /*12545*/ uint16(xArgM16int), + /*12546*/ uint16(xMatch), + /*12547*/ uint16(xSetOp), uint16(FICOMP), + /*12549*/ uint16(xArgM16int), + /*12550*/ uint16(xMatch), + /*12551*/ uint16(xSetOp), uint16(FISUB), + /*12553*/ uint16(xArgM16int), + /*12554*/ uint16(xMatch), + /*12555*/ uint16(xSetOp), uint16(FISUBR), + /*12557*/ uint16(xArgM16int), + /*12558*/ uint16(xMatch), + /*12559*/ uint16(xSetOp), uint16(FIDIV), + /*12561*/ uint16(xArgM16int), + /*12562*/ uint16(xMatch), + /*12563*/ uint16(xSetOp), uint16(FIDIVR), + /*12565*/ uint16(xArgM16int), + /*12566*/ uint16(xMatch), + /*12567*/ uint16(xSetOp), uint16(FADDP), + /*12569*/ uint16(xArgSTi), + /*12570*/ uint16(xArgST), + /*12571*/ uint16(xMatch), + /*12572*/ uint16(xSetOp), uint16(FMULP), + /*12574*/ uint16(xArgSTi), + /*12575*/ uint16(xArgST), + /*12576*/ uint16(xMatch), + /*12577*/ uint16(xSetOp), uint16(FCOMPP), + /*12579*/ uint16(xMatch), + /*12580*/ uint16(xSetOp), uint16(FSUBRP), + /*12582*/ uint16(xArgSTi), + /*12583*/ uint16(xArgST), + /*12584*/ uint16(xMatch), + /*12585*/ uint16(xSetOp), uint16(FSUBP), + /*12587*/ uint16(xArgSTi), + /*12588*/ uint16(xArgST), + /*12589*/ uint16(xMatch), + /*12590*/ uint16(xSetOp), uint16(FDIVRP), + /*12592*/ uint16(xArgSTi), + /*12593*/ uint16(xArgST), + /*12594*/ uint16(xMatch), + /*12595*/ uint16(xSetOp), uint16(FDIVP), + /*12597*/ uint16(xArgSTi), + /*12598*/ uint16(xArgST), + /*12599*/ uint16(xMatch), + /*12600*/ uint16(xCondByte), 25, + 0xc0, 12693, + 0xc1, 12693, + 0xc2, 12693, + 0xc3, 12693, + 0xc4, 12693, + 0xc5, 12693, + 0xc6, 12693, + 0xc7, 12693, + 0xE0, 12697, + 0xe8, 12701, + 0xe9, 12701, + 0xea, 12701, + 0xeb, 12701, + 0xec, 12701, + 0xed, 12701, + 0xee, 12701, + 0xef, 12701, + 0xf0, 12706, + 0xf1, 12706, + 0xf2, 12706, + 0xf3, 12706, + 0xf4, 12706, + 0xf5, 12706, + 0xf6, 12706, + 0xf7, 12706, + /*12652*/ uint16(xCondSlashR), + 12661, // 0 + 12665, // 1 + 12669, // 2 + 12673, // 3 + 12677, // 4 + 12681, // 5 + 12685, // 6 + 12689, // 7 + /*12661*/ uint16(xSetOp), uint16(FILD), + /*12663*/ uint16(xArgM16int), + /*12664*/ uint16(xMatch), + /*12665*/ uint16(xSetOp), uint16(FISTTP), + /*12667*/ uint16(xArgM16int), + /*12668*/ uint16(xMatch), + /*12669*/ uint16(xSetOp), uint16(FIST), + /*12671*/ uint16(xArgM16int), + /*12672*/ uint16(xMatch), + /*12673*/ uint16(xSetOp), uint16(FISTP), + /*12675*/ uint16(xArgM16int), + /*12676*/ uint16(xMatch), + /*12677*/ uint16(xSetOp), uint16(FBLD), + /*12679*/ uint16(xArgM80dec), + /*12680*/ uint16(xMatch), + /*12681*/ uint16(xSetOp), uint16(FILD), + /*12683*/ uint16(xArgM64int), + /*12684*/ uint16(xMatch), + /*12685*/ uint16(xSetOp), uint16(FBSTP), + /*12687*/ uint16(xArgM80bcd), + /*12688*/ uint16(xMatch), + /*12689*/ uint16(xSetOp), uint16(FISTP), + /*12691*/ uint16(xArgM64int), + /*12692*/ uint16(xMatch), + /*12693*/ uint16(xSetOp), uint16(FFREEP), + /*12695*/ uint16(xArgSTi), + /*12696*/ uint16(xMatch), + /*12697*/ uint16(xSetOp), uint16(FNSTSW), + /*12699*/ uint16(xArgAX), + /*12700*/ uint16(xMatch), + /*12701*/ uint16(xSetOp), uint16(FUCOMIP), + /*12703*/ uint16(xArgST), + /*12704*/ uint16(xArgSTi), + /*12705*/ uint16(xMatch), + /*12706*/ uint16(xSetOp), uint16(FCOMIP), + /*12708*/ uint16(xArgST), + /*12709*/ uint16(xArgSTi), + /*12710*/ uint16(xMatch), + /*12711*/ uint16(xSetOp), uint16(LOOPNE), + /*12713*/ uint16(xReadCb), + /*12714*/ uint16(xArgRel8), + /*12715*/ uint16(xMatch), + /*12716*/ uint16(xSetOp), uint16(LOOPE), + /*12718*/ uint16(xReadCb), + /*12719*/ uint16(xArgRel8), + /*12720*/ uint16(xMatch), + /*12721*/ uint16(xSetOp), uint16(LOOP), + /*12723*/ uint16(xReadCb), + /*12724*/ uint16(xArgRel8), + /*12725*/ uint16(xMatch), + /*12726*/ uint16(xCondIs64), 12729, 12743, + /*12729*/ uint16(xCondAddrSize), 12733, 12738, 0, + /*12733*/ uint16(xSetOp), uint16(JCXZ), + /*12735*/ uint16(xReadCb), + /*12736*/ uint16(xArgRel8), + /*12737*/ uint16(xMatch), + /*12738*/ uint16(xSetOp), uint16(JECXZ), + /*12740*/ uint16(xReadCb), + /*12741*/ uint16(xArgRel8), + /*12742*/ uint16(xMatch), + /*12743*/ uint16(xCondAddrSize), 0, 12738, 12747, + /*12747*/ uint16(xSetOp), uint16(JRCXZ), + /*12749*/ uint16(xReadCb), + /*12750*/ uint16(xArgRel8), + /*12751*/ uint16(xMatch), + /*12752*/ uint16(xSetOp), uint16(IN), + /*12754*/ uint16(xReadIb), + /*12755*/ uint16(xArgAL), + /*12756*/ uint16(xArgImm8u), + /*12757*/ uint16(xMatch), + /*12758*/ uint16(xCondDataSize), 12762, 12768, 12774, + /*12762*/ uint16(xSetOp), uint16(IN), + /*12764*/ uint16(xReadIb), + /*12765*/ uint16(xArgAX), + /*12766*/ uint16(xArgImm8u), + /*12767*/ uint16(xMatch), + /*12768*/ uint16(xSetOp), uint16(IN), + /*12770*/ uint16(xReadIb), + /*12771*/ uint16(xArgEAX), + /*12772*/ uint16(xArgImm8u), + /*12773*/ uint16(xMatch), + /*12774*/ uint16(xSetOp), uint16(IN), + /*12776*/ uint16(xReadIb), + /*12777*/ uint16(xArgEAX), + /*12778*/ uint16(xArgImm8u), + /*12779*/ uint16(xMatch), + /*12780*/ uint16(xSetOp), uint16(OUT), + /*12782*/ uint16(xReadIb), + /*12783*/ uint16(xArgImm8u), + /*12784*/ uint16(xArgAL), + /*12785*/ uint16(xMatch), + /*12786*/ uint16(xCondPrefix), 3, + 0xC5, 12830, + 0xC4, 12816, + 0x0, 12794, + /*12794*/ uint16(xCondDataSize), 12798, 12804, 12810, + /*12798*/ uint16(xSetOp), uint16(OUT), + /*12800*/ uint16(xReadIb), + /*12801*/ uint16(xArgImm8u), + /*12802*/ uint16(xArgAX), + /*12803*/ uint16(xMatch), + /*12804*/ uint16(xSetOp), uint16(OUT), + /*12806*/ uint16(xReadIb), + /*12807*/ uint16(xArgImm8u), + /*12808*/ uint16(xArgEAX), + /*12809*/ uint16(xMatch), + /*12810*/ uint16(xSetOp), uint16(OUT), + /*12812*/ uint16(xReadIb), + /*12813*/ uint16(xArgImm8u), + /*12814*/ uint16(xArgEAX), + /*12815*/ uint16(xMatch), + /*12816*/ uint16(xCondPrefix), 1, + 0x66, 12820, + /*12820*/ uint16(xCondPrefix), 1, + 0x0F, 12824, + /*12824*/ uint16(xSetOp), uint16(VMOVNTDQ), + /*12826*/ uint16(xReadSlashR), + /*12827*/ uint16(xArgM256), + /*12828*/ uint16(xArgYmm1), + /*12829*/ uint16(xMatch), + /*12830*/ uint16(xCondPrefix), 1, + 0x66, 12834, + /*12834*/ uint16(xCondPrefix), 1, + 0x0F, 12838, + /*12838*/ uint16(xSetOp), uint16(VMOVNTDQ), + /*12840*/ uint16(xReadSlashR), + /*12841*/ uint16(xArgM256), + /*12842*/ uint16(xArgYmm1), + /*12843*/ uint16(xMatch), + /*12844*/ uint16(xCondIs64), 12847, 12861, + /*12847*/ uint16(xCondDataSize), 12851, 12856, 0, + /*12851*/ uint16(xSetOp), uint16(CALL), + /*12853*/ uint16(xReadCw), + /*12854*/ uint16(xArgRel16), + /*12855*/ uint16(xMatch), + /*12856*/ uint16(xSetOp), uint16(CALL), + /*12858*/ uint16(xReadCd), + /*12859*/ uint16(xArgRel32), + /*12860*/ uint16(xMatch), + /*12861*/ uint16(xCondDataSize), 12865, 12856, 12870, + /*12865*/ uint16(xSetOp), uint16(CALL), + /*12867*/ uint16(xReadCd), + /*12868*/ uint16(xArgRel32), + /*12869*/ uint16(xMatch), + /*12870*/ uint16(xSetOp), uint16(CALL), + /*12872*/ uint16(xReadCd), + /*12873*/ uint16(xArgRel32), + /*12874*/ uint16(xMatch), + /*12875*/ uint16(xCondIs64), 12878, 12892, + /*12878*/ uint16(xCondDataSize), 12882, 12887, 0, + /*12882*/ uint16(xSetOp), uint16(JMP), + /*12884*/ uint16(xReadCw), + /*12885*/ uint16(xArgRel16), + /*12886*/ uint16(xMatch), + /*12887*/ uint16(xSetOp), uint16(JMP), + /*12889*/ uint16(xReadCd), + /*12890*/ uint16(xArgRel32), + /*12891*/ uint16(xMatch), + /*12892*/ uint16(xCondDataSize), 12896, 12887, 12901, + /*12896*/ uint16(xSetOp), uint16(JMP), + /*12898*/ uint16(xReadCd), + /*12899*/ uint16(xArgRel32), + /*12900*/ uint16(xMatch), + /*12901*/ uint16(xSetOp), uint16(JMP), + /*12903*/ uint16(xReadCd), + /*12904*/ uint16(xArgRel32), + /*12905*/ uint16(xMatch), + /*12906*/ uint16(xCondIs64), 12909, 0, + /*12909*/ uint16(xCondDataSize), 12913, 12918, 0, + /*12913*/ uint16(xSetOp), uint16(LJMP), + /*12915*/ uint16(xReadCd), + /*12916*/ uint16(xArgPtr16colon16), + /*12917*/ uint16(xMatch), + /*12918*/ uint16(xSetOp), uint16(LJMP), + /*12920*/ uint16(xReadCp), + /*12921*/ uint16(xArgPtr16colon32), + /*12922*/ uint16(xMatch), + /*12923*/ uint16(xSetOp), uint16(JMP), + /*12925*/ uint16(xReadCb), + /*12926*/ uint16(xArgRel8), + /*12927*/ uint16(xMatch), + /*12928*/ uint16(xSetOp), uint16(IN), + /*12930*/ uint16(xArgAL), + /*12931*/ uint16(xArgDX), + /*12932*/ uint16(xMatch), + /*12933*/ uint16(xCondDataSize), 12937, 12942, 12947, + /*12937*/ uint16(xSetOp), uint16(IN), + /*12939*/ uint16(xArgAX), + /*12940*/ uint16(xArgDX), + /*12941*/ uint16(xMatch), + /*12942*/ uint16(xSetOp), uint16(IN), + /*12944*/ uint16(xArgEAX), + /*12945*/ uint16(xArgDX), + /*12946*/ uint16(xMatch), + /*12947*/ uint16(xSetOp), uint16(IN), + /*12949*/ uint16(xArgEAX), + /*12950*/ uint16(xArgDX), + /*12951*/ uint16(xMatch), + /*12952*/ uint16(xSetOp), uint16(OUT), + /*12954*/ uint16(xArgDX), + /*12955*/ uint16(xArgAL), + /*12956*/ uint16(xMatch), + /*12957*/ uint16(xCondDataSize), 12961, 12966, 12971, + /*12961*/ uint16(xSetOp), uint16(OUT), + /*12963*/ uint16(xArgDX), + /*12964*/ uint16(xArgAX), + /*12965*/ uint16(xMatch), + /*12966*/ uint16(xSetOp), uint16(OUT), + /*12968*/ uint16(xArgDX), + /*12969*/ uint16(xArgEAX), + /*12970*/ uint16(xMatch), + /*12971*/ uint16(xSetOp), uint16(OUT), + /*12973*/ uint16(xArgDX), + /*12974*/ uint16(xArgEAX), + /*12975*/ uint16(xMatch), + /*12976*/ uint16(xSetOp), uint16(ICEBP), + /*12978*/ uint16(xMatch), + /*12979*/ uint16(xSetOp), uint16(HLT), + /*12981*/ uint16(xMatch), + /*12982*/ uint16(xSetOp), uint16(CMC), + /*12984*/ uint16(xMatch), + /*12985*/ uint16(xCondSlashR), + 12994, // 0 + 0, // 1 + 13000, // 2 + 13004, // 3 + 13008, // 4 + 13012, // 5 + 13016, // 6 + 13020, // 7 + /*12994*/ uint16(xSetOp), uint16(TEST), + /*12996*/ uint16(xReadIb), + /*12997*/ uint16(xArgRM8), + /*12998*/ uint16(xArgImm8u), + /*12999*/ uint16(xMatch), + /*13000*/ uint16(xSetOp), uint16(NOT), + /*13002*/ uint16(xArgRM8), + /*13003*/ uint16(xMatch), + /*13004*/ uint16(xSetOp), uint16(NEG), + /*13006*/ uint16(xArgRM8), + /*13007*/ uint16(xMatch), + /*13008*/ uint16(xSetOp), uint16(MUL), + /*13010*/ uint16(xArgRM8), + /*13011*/ uint16(xMatch), + /*13012*/ uint16(xSetOp), uint16(IMUL), + /*13014*/ uint16(xArgRM8), + /*13015*/ uint16(xMatch), + /*13016*/ uint16(xSetOp), uint16(DIV), + /*13018*/ uint16(xArgRM8), + /*13019*/ uint16(xMatch), + /*13020*/ uint16(xSetOp), uint16(IDIV), + /*13022*/ uint16(xArgRM8), + /*13023*/ uint16(xMatch), + /*13024*/ uint16(xCondSlashR), + 13033, // 0 + 0, // 1 + 13062, // 2 + 13085, // 3 + 13108, // 4 + 13131, // 5 + 13154, // 6 + 13177, // 7 + /*13033*/ uint16(xCondIs64), 13036, 13052, + /*13036*/ uint16(xCondDataSize), 13040, 13046, 0, + /*13040*/ uint16(xSetOp), uint16(TEST), + /*13042*/ uint16(xReadIw), + /*13043*/ uint16(xArgRM16), + /*13044*/ uint16(xArgImm16), + /*13045*/ uint16(xMatch), + /*13046*/ uint16(xSetOp), uint16(TEST), + /*13048*/ uint16(xReadId), + /*13049*/ uint16(xArgRM32), + /*13050*/ uint16(xArgImm32), + /*13051*/ uint16(xMatch), + /*13052*/ uint16(xCondDataSize), 13040, 13046, 13056, + /*13056*/ uint16(xSetOp), uint16(TEST), + /*13058*/ uint16(xReadId), + /*13059*/ uint16(xArgRM64), + /*13060*/ uint16(xArgImm32), + /*13061*/ uint16(xMatch), + /*13062*/ uint16(xCondIs64), 13065, 13077, + /*13065*/ uint16(xCondDataSize), 13069, 13073, 0, + /*13069*/ uint16(xSetOp), uint16(NOT), + /*13071*/ uint16(xArgRM16), + /*13072*/ uint16(xMatch), + /*13073*/ uint16(xSetOp), uint16(NOT), + /*13075*/ uint16(xArgRM32), + /*13076*/ uint16(xMatch), + /*13077*/ uint16(xCondDataSize), 13069, 13073, 13081, + /*13081*/ uint16(xSetOp), uint16(NOT), + /*13083*/ uint16(xArgRM64), + /*13084*/ uint16(xMatch), + /*13085*/ uint16(xCondIs64), 13088, 13100, + /*13088*/ uint16(xCondDataSize), 13092, 13096, 0, + /*13092*/ uint16(xSetOp), uint16(NEG), + /*13094*/ uint16(xArgRM16), + /*13095*/ uint16(xMatch), + /*13096*/ uint16(xSetOp), uint16(NEG), + /*13098*/ uint16(xArgRM32), + /*13099*/ uint16(xMatch), + /*13100*/ uint16(xCondDataSize), 13092, 13096, 13104, + /*13104*/ uint16(xSetOp), uint16(NEG), + /*13106*/ uint16(xArgRM64), + /*13107*/ uint16(xMatch), + /*13108*/ uint16(xCondIs64), 13111, 13123, + /*13111*/ uint16(xCondDataSize), 13115, 13119, 0, + /*13115*/ uint16(xSetOp), uint16(MUL), + /*13117*/ uint16(xArgRM16), + /*13118*/ uint16(xMatch), + /*13119*/ uint16(xSetOp), uint16(MUL), + /*13121*/ uint16(xArgRM32), + /*13122*/ uint16(xMatch), + /*13123*/ uint16(xCondDataSize), 13115, 13119, 13127, + /*13127*/ uint16(xSetOp), uint16(MUL), + /*13129*/ uint16(xArgRM64), + /*13130*/ uint16(xMatch), + /*13131*/ uint16(xCondIs64), 13134, 13146, + /*13134*/ uint16(xCondDataSize), 13138, 13142, 0, + /*13138*/ uint16(xSetOp), uint16(IMUL), + /*13140*/ uint16(xArgRM16), + /*13141*/ uint16(xMatch), + /*13142*/ uint16(xSetOp), uint16(IMUL), + /*13144*/ uint16(xArgRM32), + /*13145*/ uint16(xMatch), + /*13146*/ uint16(xCondDataSize), 13138, 13142, 13150, + /*13150*/ uint16(xSetOp), uint16(IMUL), + /*13152*/ uint16(xArgRM64), + /*13153*/ uint16(xMatch), + /*13154*/ uint16(xCondIs64), 13157, 13169, + /*13157*/ uint16(xCondDataSize), 13161, 13165, 0, + /*13161*/ uint16(xSetOp), uint16(DIV), + /*13163*/ uint16(xArgRM16), + /*13164*/ uint16(xMatch), + /*13165*/ uint16(xSetOp), uint16(DIV), + /*13167*/ uint16(xArgRM32), + /*13168*/ uint16(xMatch), + /*13169*/ uint16(xCondDataSize), 13161, 13165, 13173, + /*13173*/ uint16(xSetOp), uint16(DIV), + /*13175*/ uint16(xArgRM64), + /*13176*/ uint16(xMatch), + /*13177*/ uint16(xCondIs64), 13180, 13192, + /*13180*/ uint16(xCondDataSize), 13184, 13188, 0, + /*13184*/ uint16(xSetOp), uint16(IDIV), + /*13186*/ uint16(xArgRM16), + /*13187*/ uint16(xMatch), + /*13188*/ uint16(xSetOp), uint16(IDIV), + /*13190*/ uint16(xArgRM32), + /*13191*/ uint16(xMatch), + /*13192*/ uint16(xCondDataSize), 13184, 13188, 13196, + /*13196*/ uint16(xSetOp), uint16(IDIV), + /*13198*/ uint16(xArgRM64), + /*13199*/ uint16(xMatch), + /*13200*/ uint16(xSetOp), uint16(CLC), + /*13202*/ uint16(xMatch), + /*13203*/ uint16(xSetOp), uint16(STC), + /*13205*/ uint16(xMatch), + /*13206*/ uint16(xSetOp), uint16(CLI), + /*13208*/ uint16(xMatch), + /*13209*/ uint16(xSetOp), uint16(STI), + /*13211*/ uint16(xMatch), + /*13212*/ uint16(xSetOp), uint16(CLD), + /*13214*/ uint16(xMatch), + /*13215*/ uint16(xSetOp), uint16(STD), + /*13217*/ uint16(xMatch), + /*13218*/ uint16(xCondSlashR), + 13227, // 0 + 13231, // 1 + 0, // 2 + 0, // 3 + 0, // 4 + 0, // 5 + 0, // 6 + 0, // 7 + /*13227*/ uint16(xSetOp), uint16(INC), + /*13229*/ uint16(xArgRM8), + /*13230*/ uint16(xMatch), + /*13231*/ uint16(xSetOp), uint16(DEC), + /*13233*/ uint16(xArgRM8), + /*13234*/ uint16(xMatch), + /*13235*/ uint16(xCondSlashR), + 13244, // 0 + 13267, // 1 + 13290, // 2 + 13309, // 3 + 13332, // 4 + 13351, // 5 + 13374, // 6 + 0, // 7 + /*13244*/ uint16(xCondIs64), 13247, 13259, + /*13247*/ uint16(xCondDataSize), 13251, 13255, 0, + /*13251*/ uint16(xSetOp), uint16(INC), + /*13253*/ uint16(xArgRM16), + /*13254*/ uint16(xMatch), + /*13255*/ uint16(xSetOp), uint16(INC), + /*13257*/ uint16(xArgRM32), + /*13258*/ uint16(xMatch), + /*13259*/ uint16(xCondDataSize), 13251, 13255, 13263, + /*13263*/ uint16(xSetOp), uint16(INC), + /*13265*/ uint16(xArgRM64), + /*13266*/ uint16(xMatch), + /*13267*/ uint16(xCondIs64), 13270, 13282, + /*13270*/ uint16(xCondDataSize), 13274, 13278, 0, + /*13274*/ uint16(xSetOp), uint16(DEC), + /*13276*/ uint16(xArgRM16), + /*13277*/ uint16(xMatch), + /*13278*/ uint16(xSetOp), uint16(DEC), + /*13280*/ uint16(xArgRM32), + /*13281*/ uint16(xMatch), + /*13282*/ uint16(xCondDataSize), 13274, 13278, 13286, + /*13286*/ uint16(xSetOp), uint16(DEC), + /*13288*/ uint16(xArgRM64), + /*13289*/ uint16(xMatch), + /*13290*/ uint16(xCondIs64), 13293, 13305, + /*13293*/ uint16(xCondDataSize), 13297, 13301, 0, + /*13297*/ uint16(xSetOp), uint16(CALL), + /*13299*/ uint16(xArgRM16), + /*13300*/ uint16(xMatch), + /*13301*/ uint16(xSetOp), uint16(CALL), + /*13303*/ uint16(xArgRM32), + /*13304*/ uint16(xMatch), + /*13305*/ uint16(xSetOp), uint16(CALL), + /*13307*/ uint16(xArgRM64), + /*13308*/ uint16(xMatch), + /*13309*/ uint16(xCondIs64), 13312, 13324, + /*13312*/ uint16(xCondDataSize), 13316, 13320, 0, + /*13316*/ uint16(xSetOp), uint16(LCALL), + /*13318*/ uint16(xArgM16colon16), + /*13319*/ uint16(xMatch), + /*13320*/ uint16(xSetOp), uint16(LCALL), + /*13322*/ uint16(xArgM16colon32), + /*13323*/ uint16(xMatch), + /*13324*/ uint16(xCondDataSize), 13316, 13320, 13328, + /*13328*/ uint16(xSetOp), uint16(LCALL), + /*13330*/ uint16(xArgM16colon64), + /*13331*/ uint16(xMatch), + /*13332*/ uint16(xCondIs64), 13335, 13347, + /*13335*/ uint16(xCondDataSize), 13339, 13343, 0, + /*13339*/ uint16(xSetOp), uint16(JMP), + /*13341*/ uint16(xArgRM16), + /*13342*/ uint16(xMatch), + /*13343*/ uint16(xSetOp), uint16(JMP), + /*13345*/ uint16(xArgRM32), + /*13346*/ uint16(xMatch), + /*13347*/ uint16(xSetOp), uint16(JMP), + /*13349*/ uint16(xArgRM64), + /*13350*/ uint16(xMatch), + /*13351*/ uint16(xCondIs64), 13354, 13366, + /*13354*/ uint16(xCondDataSize), 13358, 13362, 0, + /*13358*/ uint16(xSetOp), uint16(LJMP), + /*13360*/ uint16(xArgM16colon16), + /*13361*/ uint16(xMatch), + /*13362*/ uint16(xSetOp), uint16(LJMP), + /*13364*/ uint16(xArgM16colon32), + /*13365*/ uint16(xMatch), + /*13366*/ uint16(xCondDataSize), 13358, 13362, 13370, + /*13370*/ uint16(xSetOp), uint16(LJMP), + /*13372*/ uint16(xArgM16colon64), + /*13373*/ uint16(xMatch), + /*13374*/ uint16(xCondIs64), 13377, 13389, + /*13377*/ uint16(xCondDataSize), 13381, 13385, 0, + /*13381*/ uint16(xSetOp), uint16(PUSH), + /*13383*/ uint16(xArgRM16), + /*13384*/ uint16(xMatch), + /*13385*/ uint16(xSetOp), uint16(PUSH), + /*13387*/ uint16(xArgRM32), + /*13388*/ uint16(xMatch), + /*13389*/ uint16(xCondDataSize), 13381, 13393, 13397, + /*13393*/ uint16(xSetOp), uint16(PUSH), + /*13395*/ uint16(xArgRM64), + /*13396*/ uint16(xMatch), + /*13397*/ uint16(xSetOp), uint16(PUSH), + /*13399*/ uint16(xArgRM64), + /*13400*/ uint16(xMatch), +} + +const ( + _ Op = iota + + AAA + AAD + AAM + AAS + ADC + ADD + ADDPD + ADDPS + ADDSD + ADDSS + ADDSUBPD + ADDSUBPS + AESDEC + AESDECLAST + AESENC + AESENCLAST + AESIMC + AESKEYGENASSIST + AND + ANDNPD + ANDNPS + ANDPD + ANDPS + ARPL + BLENDPD + BLENDPS + BLENDVPD + BLENDVPS + BOUND + BSF + BSR + BSWAP + BT + BTC + BTR + BTS + CALL + CBW + CDQ + CDQE + CLC + CLD + CLFLUSH + CLI + CLTS + CMC + CMOVA + CMOVAE + CMOVB + CMOVBE + CMOVE + CMOVG + CMOVGE + CMOVL + CMOVLE + CMOVNE + CMOVNO + CMOVNP + CMOVNS + CMOVO + CMOVP + CMOVS + CMP + CMPPD + CMPPS + CMPSB + CMPSD + CMPSD_XMM + CMPSQ + CMPSS + CMPSW + CMPXCHG + CMPXCHG16B + CMPXCHG8B + COMISD + COMISS + CPUID + CQO + CRC32 + CVTDQ2PD + CVTDQ2PS + CVTPD2DQ + CVTPD2PI + CVTPD2PS + CVTPI2PD + CVTPI2PS + CVTPS2DQ + CVTPS2PD + CVTPS2PI + CVTSD2SI + CVTSD2SS + CVTSI2SD + CVTSI2SS + CVTSS2SD + CVTSS2SI + CVTTPD2DQ + CVTTPD2PI + CVTTPS2DQ + CVTTPS2PI + CVTTSD2SI + CVTTSS2SI + CWD + CWDE + DAA + DAS + DEC + DIV + DIVPD + DIVPS + DIVSD + DIVSS + DPPD + DPPS + EMMS + ENTER + EXTRACTPS + F2XM1 + FABS + FADD + FADDP + FBLD + FBSTP + FCHS + FCMOVB + FCMOVBE + FCMOVE + FCMOVNB + FCMOVNBE + FCMOVNE + FCMOVNU + FCMOVU + FCOM + FCOMI + FCOMIP + FCOMP + FCOMPP + FCOS + FDECSTP + FDIV + FDIVP + FDIVR + FDIVRP + FFREE + FFREEP + FIADD + FICOM + FICOMP + FIDIV + FIDIVR + FILD + FIMUL + FINCSTP + FIST + FISTP + FISTTP + FISUB + FISUBR + FLD + FLD1 + FLDCW + FLDENV + FLDL2E + FLDL2T + FLDLG2 + FLDPI + FMUL + FMULP + FNCLEX + FNINIT + FNOP + FNSAVE + FNSTCW + FNSTENV + FNSTSW + FPATAN + FPREM + FPREM1 + FPTAN + FRNDINT + FRSTOR + FSCALE + FSIN + FSINCOS + FSQRT + FST + FSTP + FSUB + FSUBP + FSUBR + FSUBRP + FTST + FUCOM + FUCOMI + FUCOMIP + FUCOMP + FUCOMPP + FWAIT + FXAM + FXCH + FXRSTOR + FXRSTOR64 + FXSAVE + FXSAVE64 + FXTRACT + FYL2X + FYL2XP1 + HADDPD + HADDPS + HLT + HSUBPD + HSUBPS + ICEBP + IDIV + IMUL + IN + INC + INSB + INSD + INSERTPS + INSW + INT + INTO + INVD + INVLPG + INVPCID + IRET + IRETD + IRETQ + JA + JAE + JB + JBE + JCXZ + JE + JECXZ + JG + JGE + JL + JLE + JMP + JNE + JNO + JNP + JNS + JO + JP + JRCXZ + JS + LAHF + LAR + LCALL + LDDQU + LDMXCSR + LDS + LEA + LEAVE + LES + LFENCE + LFS + LGDT + LGS + LIDT + LJMP + LLDT + LMSW + LODSB + LODSD + LODSQ + LODSW + LOOP + LOOPE + LOOPNE + LRET + LSL + LSS + LTR + LZCNT + MASKMOVDQU + MASKMOVQ + MAXPD + MAXPS + MAXSD + MAXSS + MFENCE + MINPD + MINPS + MINSD + MINSS + MONITOR + MOV + MOVAPD + MOVAPS + MOVBE + MOVD + MOVDDUP + MOVDQ2Q + MOVDQA + MOVDQU + MOVHLPS + MOVHPD + MOVHPS + MOVLHPS + MOVLPD + MOVLPS + MOVMSKPD + MOVMSKPS + MOVNTDQ + MOVNTDQA + MOVNTI + MOVNTPD + MOVNTPS + MOVNTQ + MOVNTSD + MOVNTSS + MOVQ + MOVQ2DQ + MOVSB + MOVSD + MOVSD_XMM + MOVSHDUP + MOVSLDUP + MOVSQ + MOVSS + MOVSW + MOVSX + MOVSXD + MOVUPD + MOVUPS + MOVZX + MPSADBW + MUL + MULPD + MULPS + MULSD + MULSS + MWAIT + NEG + NOP + NOT + OR + ORPD + ORPS + OUT + OUTSB + OUTSD + OUTSW + PABSB + PABSD + PABSW + PACKSSDW + PACKSSWB + PACKUSDW + PACKUSWB + PADDB + PADDD + PADDQ + PADDSB + PADDSW + PADDUSB + PADDUSW + PADDW + PALIGNR + PAND + PANDN + PAUSE + PAVGB + PAVGW + PBLENDVB + PBLENDW + PCLMULQDQ + PCMPEQB + PCMPEQD + PCMPEQQ + PCMPEQW + PCMPESTRI + PCMPESTRM + PCMPGTB + PCMPGTD + PCMPGTQ + PCMPGTW + PCMPISTRI + PCMPISTRM + PEXTRB + PEXTRD + PEXTRQ + PEXTRW + PHADDD + PHADDSW + PHADDW + PHMINPOSUW + PHSUBD + PHSUBSW + PHSUBW + PINSRB + PINSRD + PINSRQ + PINSRW + PMADDUBSW + PMADDWD + PMAXSB + PMAXSD + PMAXSW + PMAXUB + PMAXUD + PMAXUW + PMINSB + PMINSD + PMINSW + PMINUB + PMINUD + PMINUW + PMOVMSKB + PMOVSXBD + PMOVSXBQ + PMOVSXBW + PMOVSXDQ + PMOVSXWD + PMOVSXWQ + PMOVZXBD + PMOVZXBQ + PMOVZXBW + PMOVZXDQ + PMOVZXWD + PMOVZXWQ + PMULDQ + PMULHRSW + PMULHUW + PMULHW + PMULLD + PMULLW + PMULUDQ + POP + POPA + POPAD + POPCNT + POPF + POPFD + POPFQ + POR + PREFETCHNTA + PREFETCHT0 + PREFETCHT1 + PREFETCHT2 + PREFETCHW + PSADBW + PSHUFB + PSHUFD + PSHUFHW + PSHUFLW + PSHUFW + PSIGNB + PSIGND + PSIGNW + PSLLD + PSLLDQ + PSLLQ + PSLLW + PSRAD + PSRAW + PSRLD + PSRLDQ + PSRLQ + PSRLW + PSUBB + PSUBD + PSUBQ + PSUBSB + PSUBSW + PSUBUSB + PSUBUSW + PSUBW + PTEST + PUNPCKHBW + PUNPCKHDQ + PUNPCKHQDQ + PUNPCKHWD + PUNPCKLBW + PUNPCKLDQ + PUNPCKLQDQ + PUNPCKLWD + PUSH + PUSHA + PUSHAD + PUSHF + PUSHFD + PUSHFQ + PXOR + RCL + RCPPS + RCPSS + RCR + RDFSBASE + RDGSBASE + RDMSR + RDPMC + RDRAND + RDTSC + RDTSCP + RET + ROL + ROR + ROUNDPD + ROUNDPS + ROUNDSD + ROUNDSS + RSM + RSQRTPS + RSQRTSS + SAHF + SAR + SBB + SCASB + SCASD + SCASQ + SCASW + SETA + SETAE + SETB + SETBE + SETE + SETG + SETGE + SETL + SETLE + SETNE + SETNO + SETNP + SETNS + SETO + SETP + SETS + SFENCE + SGDT + SHL + SHLD + SHR + SHRD + SHUFPD + SHUFPS + SIDT + SLDT + SMSW + SQRTPD + SQRTPS + SQRTSD + SQRTSS + STC + STD + STI + STMXCSR + STOSB + STOSD + STOSQ + STOSW + STR + SUB + SUBPD + SUBPS + SUBSD + SUBSS + SWAPGS + SYSCALL + SYSENTER + SYSEXIT + SYSRET + TEST + TZCNT + UCOMISD + UCOMISS + UD1 + UD2 + UNPCKHPD + UNPCKHPS + UNPCKLPD + UNPCKLPS + VERR + VERW + VMOVDQA + VMOVDQU + VMOVNTDQ + VMOVNTDQA + VZEROUPPER + WBINVD + WRFSBASE + WRGSBASE + WRMSR + XABORT + XADD + XBEGIN + XCHG + XEND + XGETBV + XLATB + XOR + XORPD + XORPS + XRSTOR + XRSTOR64 + XRSTORS + XRSTORS64 + XSAVE + XSAVE64 + XSAVEC + XSAVEC64 + XSAVEOPT + XSAVEOPT64 + XSAVES + XSAVES64 + XSETBV + XTEST +) + +const maxOp = XTEST + +var opNames = [...]string{ + AAA: "AAA", + AAD: "AAD", + AAM: "AAM", + AAS: "AAS", + ADC: "ADC", + ADD: "ADD", + ADDPD: "ADDPD", + ADDPS: "ADDPS", + ADDSD: "ADDSD", + ADDSS: "ADDSS", + ADDSUBPD: "ADDSUBPD", + ADDSUBPS: "ADDSUBPS", + AESDEC: "AESDEC", + AESDECLAST: "AESDECLAST", + AESENC: "AESENC", + AESENCLAST: "AESENCLAST", + AESIMC: "AESIMC", + AESKEYGENASSIST: "AESKEYGENASSIST", + AND: "AND", + ANDNPD: "ANDNPD", + ANDNPS: "ANDNPS", + ANDPD: "ANDPD", + ANDPS: "ANDPS", + ARPL: "ARPL", + BLENDPD: "BLENDPD", + BLENDPS: "BLENDPS", + BLENDVPD: "BLENDVPD", + BLENDVPS: "BLENDVPS", + BOUND: "BOUND", + BSF: "BSF", + BSR: "BSR", + BSWAP: "BSWAP", + BT: "BT", + BTC: "BTC", + BTR: "BTR", + BTS: "BTS", + CALL: "CALL", + CBW: "CBW", + CDQ: "CDQ", + CDQE: "CDQE", + CLC: "CLC", + CLD: "CLD", + CLFLUSH: "CLFLUSH", + CLI: "CLI", + CLTS: "CLTS", + CMC: "CMC", + CMOVA: "CMOVA", + CMOVAE: "CMOVAE", + CMOVB: "CMOVB", + CMOVBE: "CMOVBE", + CMOVE: "CMOVE", + CMOVG: "CMOVG", + CMOVGE: "CMOVGE", + CMOVL: "CMOVL", + CMOVLE: "CMOVLE", + CMOVNE: "CMOVNE", + CMOVNO: "CMOVNO", + CMOVNP: "CMOVNP", + CMOVNS: "CMOVNS", + CMOVO: "CMOVO", + CMOVP: "CMOVP", + CMOVS: "CMOVS", + CMP: "CMP", + CMPPD: "CMPPD", + CMPPS: "CMPPS", + CMPSB: "CMPSB", + CMPSD: "CMPSD", + CMPSD_XMM: "CMPSD_XMM", + CMPSQ: "CMPSQ", + CMPSS: "CMPSS", + CMPSW: "CMPSW", + CMPXCHG: "CMPXCHG", + CMPXCHG16B: "CMPXCHG16B", + CMPXCHG8B: "CMPXCHG8B", + COMISD: "COMISD", + COMISS: "COMISS", + CPUID: "CPUID", + CQO: "CQO", + CRC32: "CRC32", + CVTDQ2PD: "CVTDQ2PD", + CVTDQ2PS: "CVTDQ2PS", + CVTPD2DQ: "CVTPD2DQ", + CVTPD2PI: "CVTPD2PI", + CVTPD2PS: "CVTPD2PS", + CVTPI2PD: "CVTPI2PD", + CVTPI2PS: "CVTPI2PS", + CVTPS2DQ: "CVTPS2DQ", + CVTPS2PD: "CVTPS2PD", + CVTPS2PI: "CVTPS2PI", + CVTSD2SI: "CVTSD2SI", + CVTSD2SS: "CVTSD2SS", + CVTSI2SD: "CVTSI2SD", + CVTSI2SS: "CVTSI2SS", + CVTSS2SD: "CVTSS2SD", + CVTSS2SI: "CVTSS2SI", + CVTTPD2DQ: "CVTTPD2DQ", + CVTTPD2PI: "CVTTPD2PI", + CVTTPS2DQ: "CVTTPS2DQ", + CVTTPS2PI: "CVTTPS2PI", + CVTTSD2SI: "CVTTSD2SI", + CVTTSS2SI: "CVTTSS2SI", + CWD: "CWD", + CWDE: "CWDE", + DAA: "DAA", + DAS: "DAS", + DEC: "DEC", + DIV: "DIV", + DIVPD: "DIVPD", + DIVPS: "DIVPS", + DIVSD: "DIVSD", + DIVSS: "DIVSS", + DPPD: "DPPD", + DPPS: "DPPS", + EMMS: "EMMS", + ENTER: "ENTER", + EXTRACTPS: "EXTRACTPS", + F2XM1: "F2XM1", + FABS: "FABS", + FADD: "FADD", + FADDP: "FADDP", + FBLD: "FBLD", + FBSTP: "FBSTP", + FCHS: "FCHS", + FCMOVB: "FCMOVB", + FCMOVBE: "FCMOVBE", + FCMOVE: "FCMOVE", + FCMOVNB: "FCMOVNB", + FCMOVNBE: "FCMOVNBE", + FCMOVNE: "FCMOVNE", + FCMOVNU: "FCMOVNU", + FCMOVU: "FCMOVU", + FCOM: "FCOM", + FCOMI: "FCOMI", + FCOMIP: "FCOMIP", + FCOMP: "FCOMP", + FCOMPP: "FCOMPP", + FCOS: "FCOS", + FDECSTP: "FDECSTP", + FDIV: "FDIV", + FDIVP: "FDIVP", + FDIVR: "FDIVR", + FDIVRP: "FDIVRP", + FFREE: "FFREE", + FFREEP: "FFREEP", + FIADD: "FIADD", + FICOM: "FICOM", + FICOMP: "FICOMP", + FIDIV: "FIDIV", + FIDIVR: "FIDIVR", + FILD: "FILD", + FIMUL: "FIMUL", + FINCSTP: "FINCSTP", + FIST: "FIST", + FISTP: "FISTP", + FISTTP: "FISTTP", + FISUB: "FISUB", + FISUBR: "FISUBR", + FLD: "FLD", + FLD1: "FLD1", + FLDCW: "FLDCW", + FLDENV: "FLDENV", + FLDL2E: "FLDL2E", + FLDL2T: "FLDL2T", + FLDLG2: "FLDLG2", + FLDPI: "FLDPI", + FMUL: "FMUL", + FMULP: "FMULP", + FNCLEX: "FNCLEX", + FNINIT: "FNINIT", + FNOP: "FNOP", + FNSAVE: "FNSAVE", + FNSTCW: "FNSTCW", + FNSTENV: "FNSTENV", + FNSTSW: "FNSTSW", + FPATAN: "FPATAN", + FPREM: "FPREM", + FPREM1: "FPREM1", + FPTAN: "FPTAN", + FRNDINT: "FRNDINT", + FRSTOR: "FRSTOR", + FSCALE: "FSCALE", + FSIN: "FSIN", + FSINCOS: "FSINCOS", + FSQRT: "FSQRT", + FST: "FST", + FSTP: "FSTP", + FSUB: "FSUB", + FSUBP: "FSUBP", + FSUBR: "FSUBR", + FSUBRP: "FSUBRP", + FTST: "FTST", + FUCOM: "FUCOM", + FUCOMI: "FUCOMI", + FUCOMIP: "FUCOMIP", + FUCOMP: "FUCOMP", + FUCOMPP: "FUCOMPP", + FWAIT: "FWAIT", + FXAM: "FXAM", + FXCH: "FXCH", + FXRSTOR: "FXRSTOR", + FXRSTOR64: "FXRSTOR64", + FXSAVE: "FXSAVE", + FXSAVE64: "FXSAVE64", + FXTRACT: "FXTRACT", + FYL2X: "FYL2X", + FYL2XP1: "FYL2XP1", + HADDPD: "HADDPD", + HADDPS: "HADDPS", + HLT: "HLT", + HSUBPD: "HSUBPD", + HSUBPS: "HSUBPS", + ICEBP: "ICEBP", + IDIV: "IDIV", + IMUL: "IMUL", + IN: "IN", + INC: "INC", + INSB: "INSB", + INSD: "INSD", + INSERTPS: "INSERTPS", + INSW: "INSW", + INT: "INT", + INTO: "INTO", + INVD: "INVD", + INVLPG: "INVLPG", + INVPCID: "INVPCID", + IRET: "IRET", + IRETD: "IRETD", + IRETQ: "IRETQ", + JA: "JA", + JAE: "JAE", + JB: "JB", + JBE: "JBE", + JCXZ: "JCXZ", + JE: "JE", + JECXZ: "JECXZ", + JG: "JG", + JGE: "JGE", + JL: "JL", + JLE: "JLE", + JMP: "JMP", + JNE: "JNE", + JNO: "JNO", + JNP: "JNP", + JNS: "JNS", + JO: "JO", + JP: "JP", + JRCXZ: "JRCXZ", + JS: "JS", + LAHF: "LAHF", + LAR: "LAR", + LCALL: "LCALL", + LDDQU: "LDDQU", + LDMXCSR: "LDMXCSR", + LDS: "LDS", + LEA: "LEA", + LEAVE: "LEAVE", + LES: "LES", + LFENCE: "LFENCE", + LFS: "LFS", + LGDT: "LGDT", + LGS: "LGS", + LIDT: "LIDT", + LJMP: "LJMP", + LLDT: "LLDT", + LMSW: "LMSW", + LODSB: "LODSB", + LODSD: "LODSD", + LODSQ: "LODSQ", + LODSW: "LODSW", + LOOP: "LOOP", + LOOPE: "LOOPE", + LOOPNE: "LOOPNE", + LRET: "LRET", + LSL: "LSL", + LSS: "LSS", + LTR: "LTR", + LZCNT: "LZCNT", + MASKMOVDQU: "MASKMOVDQU", + MASKMOVQ: "MASKMOVQ", + MAXPD: "MAXPD", + MAXPS: "MAXPS", + MAXSD: "MAXSD", + MAXSS: "MAXSS", + MFENCE: "MFENCE", + MINPD: "MINPD", + MINPS: "MINPS", + MINSD: "MINSD", + MINSS: "MINSS", + MONITOR: "MONITOR", + MOV: "MOV", + MOVAPD: "MOVAPD", + MOVAPS: "MOVAPS", + MOVBE: "MOVBE", + MOVD: "MOVD", + MOVDDUP: "MOVDDUP", + MOVDQ2Q: "MOVDQ2Q", + MOVDQA: "MOVDQA", + MOVDQU: "MOVDQU", + MOVHLPS: "MOVHLPS", + MOVHPD: "MOVHPD", + MOVHPS: "MOVHPS", + MOVLHPS: "MOVLHPS", + MOVLPD: "MOVLPD", + MOVLPS: "MOVLPS", + MOVMSKPD: "MOVMSKPD", + MOVMSKPS: "MOVMSKPS", + MOVNTDQ: "MOVNTDQ", + MOVNTDQA: "MOVNTDQA", + MOVNTI: "MOVNTI", + MOVNTPD: "MOVNTPD", + MOVNTPS: "MOVNTPS", + MOVNTQ: "MOVNTQ", + MOVNTSD: "MOVNTSD", + MOVNTSS: "MOVNTSS", + MOVQ: "MOVQ", + MOVQ2DQ: "MOVQ2DQ", + MOVSB: "MOVSB", + MOVSD: "MOVSD", + MOVSD_XMM: "MOVSD_XMM", + MOVSHDUP: "MOVSHDUP", + MOVSLDUP: "MOVSLDUP", + MOVSQ: "MOVSQ", + MOVSS: "MOVSS", + MOVSW: "MOVSW", + MOVSX: "MOVSX", + MOVSXD: "MOVSXD", + MOVUPD: "MOVUPD", + MOVUPS: "MOVUPS", + MOVZX: "MOVZX", + MPSADBW: "MPSADBW", + MUL: "MUL", + MULPD: "MULPD", + MULPS: "MULPS", + MULSD: "MULSD", + MULSS: "MULSS", + MWAIT: "MWAIT", + NEG: "NEG", + NOP: "NOP", + NOT: "NOT", + OR: "OR", + ORPD: "ORPD", + ORPS: "ORPS", + OUT: "OUT", + OUTSB: "OUTSB", + OUTSD: "OUTSD", + OUTSW: "OUTSW", + PABSB: "PABSB", + PABSD: "PABSD", + PABSW: "PABSW", + PACKSSDW: "PACKSSDW", + PACKSSWB: "PACKSSWB", + PACKUSDW: "PACKUSDW", + PACKUSWB: "PACKUSWB", + PADDB: "PADDB", + PADDD: "PADDD", + PADDQ: "PADDQ", + PADDSB: "PADDSB", + PADDSW: "PADDSW", + PADDUSB: "PADDUSB", + PADDUSW: "PADDUSW", + PADDW: "PADDW", + PALIGNR: "PALIGNR", + PAND: "PAND", + PANDN: "PANDN", + PAUSE: "PAUSE", + PAVGB: "PAVGB", + PAVGW: "PAVGW", + PBLENDVB: "PBLENDVB", + PBLENDW: "PBLENDW", + PCLMULQDQ: "PCLMULQDQ", + PCMPEQB: "PCMPEQB", + PCMPEQD: "PCMPEQD", + PCMPEQQ: "PCMPEQQ", + PCMPEQW: "PCMPEQW", + PCMPESTRI: "PCMPESTRI", + PCMPESTRM: "PCMPESTRM", + PCMPGTB: "PCMPGTB", + PCMPGTD: "PCMPGTD", + PCMPGTQ: "PCMPGTQ", + PCMPGTW: "PCMPGTW", + PCMPISTRI: "PCMPISTRI", + PCMPISTRM: "PCMPISTRM", + PEXTRB: "PEXTRB", + PEXTRD: "PEXTRD", + PEXTRQ: "PEXTRQ", + PEXTRW: "PEXTRW", + PHADDD: "PHADDD", + PHADDSW: "PHADDSW", + PHADDW: "PHADDW", + PHMINPOSUW: "PHMINPOSUW", + PHSUBD: "PHSUBD", + PHSUBSW: "PHSUBSW", + PHSUBW: "PHSUBW", + PINSRB: "PINSRB", + PINSRD: "PINSRD", + PINSRQ: "PINSRQ", + PINSRW: "PINSRW", + PMADDUBSW: "PMADDUBSW", + PMADDWD: "PMADDWD", + PMAXSB: "PMAXSB", + PMAXSD: "PMAXSD", + PMAXSW: "PMAXSW", + PMAXUB: "PMAXUB", + PMAXUD: "PMAXUD", + PMAXUW: "PMAXUW", + PMINSB: "PMINSB", + PMINSD: "PMINSD", + PMINSW: "PMINSW", + PMINUB: "PMINUB", + PMINUD: "PMINUD", + PMINUW: "PMINUW", + PMOVMSKB: "PMOVMSKB", + PMOVSXBD: "PMOVSXBD", + PMOVSXBQ: "PMOVSXBQ", + PMOVSXBW: "PMOVSXBW", + PMOVSXDQ: "PMOVSXDQ", + PMOVSXWD: "PMOVSXWD", + PMOVSXWQ: "PMOVSXWQ", + PMOVZXBD: "PMOVZXBD", + PMOVZXBQ: "PMOVZXBQ", + PMOVZXBW: "PMOVZXBW", + PMOVZXDQ: "PMOVZXDQ", + PMOVZXWD: "PMOVZXWD", + PMOVZXWQ: "PMOVZXWQ", + PMULDQ: "PMULDQ", + PMULHRSW: "PMULHRSW", + PMULHUW: "PMULHUW", + PMULHW: "PMULHW", + PMULLD: "PMULLD", + PMULLW: "PMULLW", + PMULUDQ: "PMULUDQ", + POP: "POP", + POPA: "POPA", + POPAD: "POPAD", + POPCNT: "POPCNT", + POPF: "POPF", + POPFD: "POPFD", + POPFQ: "POPFQ", + POR: "POR", + PREFETCHNTA: "PREFETCHNTA", + PREFETCHT0: "PREFETCHT0", + PREFETCHT1: "PREFETCHT1", + PREFETCHT2: "PREFETCHT2", + PREFETCHW: "PREFETCHW", + PSADBW: "PSADBW", + PSHUFB: "PSHUFB", + PSHUFD: "PSHUFD", + PSHUFHW: "PSHUFHW", + PSHUFLW: "PSHUFLW", + PSHUFW: "PSHUFW", + PSIGNB: "PSIGNB", + PSIGND: "PSIGND", + PSIGNW: "PSIGNW", + PSLLD: "PSLLD", + PSLLDQ: "PSLLDQ", + PSLLQ: "PSLLQ", + PSLLW: "PSLLW", + PSRAD: "PSRAD", + PSRAW: "PSRAW", + PSRLD: "PSRLD", + PSRLDQ: "PSRLDQ", + PSRLQ: "PSRLQ", + PSRLW: "PSRLW", + PSUBB: "PSUBB", + PSUBD: "PSUBD", + PSUBQ: "PSUBQ", + PSUBSB: "PSUBSB", + PSUBSW: "PSUBSW", + PSUBUSB: "PSUBUSB", + PSUBUSW: "PSUBUSW", + PSUBW: "PSUBW", + PTEST: "PTEST", + PUNPCKHBW: "PUNPCKHBW", + PUNPCKHDQ: "PUNPCKHDQ", + PUNPCKHQDQ: "PUNPCKHQDQ", + PUNPCKHWD: "PUNPCKHWD", + PUNPCKLBW: "PUNPCKLBW", + PUNPCKLDQ: "PUNPCKLDQ", + PUNPCKLQDQ: "PUNPCKLQDQ", + PUNPCKLWD: "PUNPCKLWD", + PUSH: "PUSH", + PUSHA: "PUSHA", + PUSHAD: "PUSHAD", + PUSHF: "PUSHF", + PUSHFD: "PUSHFD", + PUSHFQ: "PUSHFQ", + PXOR: "PXOR", + RCL: "RCL", + RCPPS: "RCPPS", + RCPSS: "RCPSS", + RCR: "RCR", + RDFSBASE: "RDFSBASE", + RDGSBASE: "RDGSBASE", + RDMSR: "RDMSR", + RDPMC: "RDPMC", + RDRAND: "RDRAND", + RDTSC: "RDTSC", + RDTSCP: "RDTSCP", + RET: "RET", + ROL: "ROL", + ROR: "ROR", + ROUNDPD: "ROUNDPD", + ROUNDPS: "ROUNDPS", + ROUNDSD: "ROUNDSD", + ROUNDSS: "ROUNDSS", + RSM: "RSM", + RSQRTPS: "RSQRTPS", + RSQRTSS: "RSQRTSS", + SAHF: "SAHF", + SAR: "SAR", + SBB: "SBB", + SCASB: "SCASB", + SCASD: "SCASD", + SCASQ: "SCASQ", + SCASW: "SCASW", + SETA: "SETA", + SETAE: "SETAE", + SETB: "SETB", + SETBE: "SETBE", + SETE: "SETE", + SETG: "SETG", + SETGE: "SETGE", + SETL: "SETL", + SETLE: "SETLE", + SETNE: "SETNE", + SETNO: "SETNO", + SETNP: "SETNP", + SETNS: "SETNS", + SETO: "SETO", + SETP: "SETP", + SETS: "SETS", + SFENCE: "SFENCE", + SGDT: "SGDT", + SHL: "SHL", + SHLD: "SHLD", + SHR: "SHR", + SHRD: "SHRD", + SHUFPD: "SHUFPD", + SHUFPS: "SHUFPS", + SIDT: "SIDT", + SLDT: "SLDT", + SMSW: "SMSW", + SQRTPD: "SQRTPD", + SQRTPS: "SQRTPS", + SQRTSD: "SQRTSD", + SQRTSS: "SQRTSS", + STC: "STC", + STD: "STD", + STI: "STI", + STMXCSR: "STMXCSR", + STOSB: "STOSB", + STOSD: "STOSD", + STOSQ: "STOSQ", + STOSW: "STOSW", + STR: "STR", + SUB: "SUB", + SUBPD: "SUBPD", + SUBPS: "SUBPS", + SUBSD: "SUBSD", + SUBSS: "SUBSS", + SWAPGS: "SWAPGS", + SYSCALL: "SYSCALL", + SYSENTER: "SYSENTER", + SYSEXIT: "SYSEXIT", + SYSRET: "SYSRET", + TEST: "TEST", + TZCNT: "TZCNT", + UCOMISD: "UCOMISD", + UCOMISS: "UCOMISS", + UD1: "UD1", + UD2: "UD2", + UNPCKHPD: "UNPCKHPD", + UNPCKHPS: "UNPCKHPS", + UNPCKLPD: "UNPCKLPD", + UNPCKLPS: "UNPCKLPS", + VERR: "VERR", + VERW: "VERW", + VMOVDQA: "VMOVDQA", + VMOVDQU: "VMOVDQU", + VMOVNTDQ: "VMOVNTDQ", + VMOVNTDQA: "VMOVNTDQA", + VZEROUPPER: "VZEROUPPER", + WBINVD: "WBINVD", + WRFSBASE: "WRFSBASE", + WRGSBASE: "WRGSBASE", + WRMSR: "WRMSR", + XABORT: "XABORT", + XADD: "XADD", + XBEGIN: "XBEGIN", + XCHG: "XCHG", + XEND: "XEND", + XGETBV: "XGETBV", + XLATB: "XLATB", + XOR: "XOR", + XORPD: "XORPD", + XORPS: "XORPS", + XRSTOR: "XRSTOR", + XRSTOR64: "XRSTOR64", + XRSTORS: "XRSTORS", + XRSTORS64: "XRSTORS64", + XSAVE: "XSAVE", + XSAVE64: "XSAVE64", + XSAVEC: "XSAVEC", + XSAVEC64: "XSAVEC64", + XSAVEOPT: "XSAVEOPT", + XSAVEOPT64: "XSAVEOPT64", + XSAVES: "XSAVES", + XSAVES64: "XSAVES64", + XSETBV: "XSETBV", + XTEST: "XTEST", +} |