diff options
Diffstat (limited to 'vendor/github.com/klauspost')
9 files changed, 186 insertions, 109 deletions
diff --git a/vendor/github.com/klauspost/cpuid/v2/README.md b/vendor/github.com/klauspost/cpuid/v2/README.md index 465f4b77..bc2f98f0 100644 --- a/vendor/github.com/klauspost/cpuid/v2/README.md +++ b/vendor/github.com/klauspost/cpuid/v2/README.md @@ -39,10 +39,10 @@ func main() { fmt.Println("ThreadsPerCore:", CPU.ThreadsPerCore) fmt.Println("LogicalCores:", CPU.LogicalCores) fmt.Println("Family", CPU.Family, "Model:", CPU.Model, "Vendor ID:", CPU.VendorID) - fmt.Println("Features:", fmt.Sprintf(strings.Join(CPU.FeatureSet(), ","))) + fmt.Println("Features:", strings.Join(CPU.FeatureSet(), ",")) fmt.Println("Cacheline bytes:", CPU.CacheLine) fmt.Println("L1 Data Cache:", CPU.Cache.L1D, "bytes") - fmt.Println("L1 Instruction Cache:", CPU.Cache.L1D, "bytes") + fmt.Println("L1 Instruction Cache:", CPU.Cache.L1I, "bytes") fmt.Println("L2 Cache:", CPU.Cache.L2, "bytes") fmt.Println("L3 Cache:", CPU.Cache.L3, "bytes") fmt.Println("Frequency", CPU.Hz, "hz") diff --git a/vendor/github.com/klauspost/cpuid/v2/cpuid.go b/vendor/github.com/klauspost/cpuid/v2/cpuid.go index 1d88736b..3d543ce9 100644 --- a/vendor/github.com/klauspost/cpuid/v2/cpuid.go +++ b/vendor/github.com/klauspost/cpuid/v2/cpuid.go @@ -95,10 +95,13 @@ const ( AVXSLOW // Indicates the CPU performs 2 128 bit operations instead of one. BMI1 // Bit Manipulation Instruction Set 1 BMI2 // Bit Manipulation Instruction Set 2 + CETIBT // Intel CET Indirect Branch Tracking + CETSS // Intel CET Shadow Stack CLDEMOTE // Cache Line Demote CLMUL // Carry-less Multiplication CLZERO // CLZERO instruction supported CMOV // i686 CMOV + CMPXCHG8 // CMPXCHG8 instruction CPBOOST // Core Performance Boost CX16 // CMPXCHG16B Instruction ENQCMD // Enqueue Command @@ -106,6 +109,8 @@ const ( F16C // Half-precision floating-point conversion FMA3 // Intel FMA 3. Does not imply AVX. FMA4 // Bulldozer FMA4 functions + FXSR // FXSAVE, FXRESTOR instructions, CR4 bit 9 + FXSROPT // FXSAVE/FXRSTOR optimizations GFNI // Galois Field New Instructions HLE // Hardware Lock Elision HTT // Hyperthreading (enabled) @@ -123,16 +128,19 @@ const ( IBSRIPINVALIDCHK // Instruction Based Sampling Feature (AMD) INT_WBINVD // WBINVD/WBNOINVD are interruptible. INVLPGB // NVLPGB and TLBSYNC instruction supported + LAHF // LAHF/SAHF in long mode LZCNT // LZCNT instruction MCAOVERFLOW // MCA overflow recovery support. MCOMMIT // MCOMMIT instruction supported MMX // standard MMX MMXEXT // SSE integer functions or AMD MMX ext + MOVBE // MOVBE instruction (big-endian) MOVDIR64B // Move 64 Bytes as Direct Store MOVDIRI // Move Doubleword as Direct Store MPX // Intel MPX (Memory Protection Extensions) MSRIRC // Instruction Retired Counter MSR available NX // NX (No-Execute) bit + OSXSAVE // XSAVE enabled by OS POPCNT // POPCNT instruction RDPRU // RDPRU instruction supported RDRAND // RDRAND instruction is available @@ -140,6 +148,7 @@ const ( RDTSCP // RDTSCP Instruction RTM // Restricted Transactional Memory RTM_ALWAYS_ABORT // Indicates that the loaded microcode is forcing RTM abort. + SCE // SYSENTER and SYSEXIT instructions SERIALIZE // Serialize Instruction Execution SGX // Software Guard Extensions SGXLC // Software Guard Extensions Launch Control @@ -160,7 +169,9 @@ const ( VPCLMULQDQ // Carry-Less Multiplication Quadword WAITPKG // TPAUSE, UMONITOR, UMWAIT WBNOINVD // Write Back and Do Not Invalidate Cache + X87 // FPU XOP // Bulldozer XOP functions + XSAVE // XSAVE, XRESTOR, XSETBV, XGETBV // ARM features: AESARM // AES instructions @@ -311,6 +322,31 @@ func (c CPUInfo) Has(id FeatureID) bool { return c.featureSet.inSet(id) } +// https://en.wikipedia.org/wiki/X86-64#Microarchitecture_levels +var level1Features = flagSetWith(CMOV, CMPXCHG8, X87, FXSR, MMX, SCE, SSE, SSE2) +var level2Features = flagSetWith(CMOV, CMPXCHG8, X87, FXSR, MMX, SCE, SSE, SSE2, CX16, LAHF, POPCNT, SSE3, SSE4, SSE42, SSSE3) +var level3Features = flagSetWith(CMOV, CMPXCHG8, X87, FXSR, MMX, SCE, SSE, SSE2, CX16, LAHF, POPCNT, SSE3, SSE4, SSE42, SSSE3, AVX, AVX2, BMI1, BMI2, F16C, FMA3, LZCNT, MOVBE, OSXSAVE) +var level4Features = flagSetWith(CMOV, CMPXCHG8, X87, FXSR, MMX, SCE, SSE, SSE2, CX16, LAHF, POPCNT, SSE3, SSE4, SSE42, SSSE3, AVX, AVX2, BMI1, BMI2, F16C, FMA3, LZCNT, MOVBE, OSXSAVE, AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL) + +// X64Level returns the microarchitecture level detected on the CPU. +// If features are lacking or non x64 mode, 0 is returned. +// See https://en.wikipedia.org/wiki/X86-64#Microarchitecture_levels +func (c CPUInfo) X64Level() int { + if c.featureSet.hasSet(level4Features) { + return 4 + } + if c.featureSet.hasSet(level3Features) { + return 3 + } + if c.featureSet.hasSet(level2Features) { + return 2 + } + if c.featureSet.hasSet(level1Features) { + return 1 + } + return 0 +} + // Disable will disable one or several features. func (c *CPUInfo) Disable(ids ...FeatureID) bool { for _, id := range ids { @@ -335,9 +371,7 @@ func (c CPUInfo) IsVendor(v Vendor) bool { func (c CPUInfo) FeatureSet() []string { s := make([]string, 0) - for _, f := range c.featureSet.Strings() { - s = append(s, f) - } + s = append(s, c.featureSet.Strings()...) return s } @@ -499,6 +533,24 @@ func (s *flagSet) or(other flagSet) { } } +// hasSet returns whether all features are present. +func (s flagSet) hasSet(other flagSet) bool { + for i, v := range other[:] { + if s[i]&v != v { + return false + } + } + return true +} + +func flagSetWith(feat ...FeatureID) flagSet { + var res flagSet + for _, f := range feat { + res.set(f) + } + return res +} + // ParseFeature will parse the string and return the ID of the matching feature. // Will return UNKNOWN if not found. func ParseFeature(s string) FeatureID { @@ -708,6 +760,7 @@ func (c *CPUInfo) cacheSize() { if maxFunctionID() < 4 { return } + c.Cache.L1I, c.Cache.L1D, c.Cache.L2, c.Cache.L3 = 0, 0, 0, 0 for i := uint32(0); ; i++ { eax, ebx, ecx, _ := cpuidex(4, i) cacheType := eax & 15 @@ -800,8 +853,6 @@ func (c *CPUInfo) cacheSize() { } } } - - return } type SGXEPCSection struct { @@ -865,9 +916,14 @@ func support() flagSet { family, model := familyModel() _, _, c, d := cpuid(1) + fs.setIf((d&(1<<0)) != 0, X87) + fs.setIf((d&(1<<8)) != 0, CMPXCHG8) + fs.setIf((d&(1<<11)) != 0, SCE) fs.setIf((d&(1<<15)) != 0, CMOV) + fs.setIf((d&(1<<22)) != 0, MMXEXT) fs.setIf((d&(1<<23)) != 0, MMX) - fs.setIf((d&(1<<25)) != 0, MMXEXT) + fs.setIf((d&(1<<24)) != 0, FXSR) + fs.setIf((d&(1<<25)) != 0, FXSROPT) fs.setIf((d&(1<<25)) != 0, SSE) fs.setIf((d&(1<<26)) != 0, SSE2) fs.setIf((c&1) != 0, SSE3) @@ -877,6 +933,7 @@ func support() flagSet { fs.setIf((c&0x00100000) != 0, SSE42) fs.setIf((c&(1<<25)) != 0, AESNI) fs.setIf((c&(1<<1)) != 0, CLMUL) + fs.setIf(c&(1<<22) != 0, MOVBE) fs.setIf(c&(1<<23) != 0, POPCNT) fs.setIf(c&(1<<30) != 0, RDRAND) @@ -892,6 +949,8 @@ func support() flagSet { if vend == AMD && (d&(1<<28)) != 0 && mfi >= 4 { fs.setIf(threadsPerCore() > 1, HTT) } + fs.setIf(c&1<<26 != 0, XSAVE) + fs.setIf(c&1<<27 != 0, OSXSAVE) // Check XGETBV/XSAVE (26), OXSAVE (27) and AVX (28) bits const avxCheck = 1<<26 | 1<<27 | 1<<28 if c&avxCheck == avxCheck { @@ -936,6 +995,7 @@ func support() flagSet { fs.setIf(ebx&(1<<29) != 0, SHA) // CPUID.(EAX=7, ECX=0).ECX fs.setIf(ecx&(1<<5) != 0, WAITPKG) + fs.setIf(ecx&(1<<7) != 0, CETSS) fs.setIf(ecx&(1<<25) != 0, CLDEMOTE) fs.setIf(ecx&(1<<27) != 0, MOVDIRI) fs.setIf(ecx&(1<<28) != 0, MOVDIR64B) @@ -945,6 +1005,7 @@ func support() flagSet { fs.setIf(edx&(1<<11) != 0, RTM_ALWAYS_ABORT) fs.setIf(edx&(1<<14) != 0, SERIALIZE) fs.setIf(edx&(1<<16) != 0, TSXLDTRK) + fs.setIf(edx&(1<<20) != 0, CETIBT) fs.setIf(edx&(1<<26) != 0, IBPB) fs.setIf(edx&(1<<27) != 0, STIBP) @@ -996,6 +1057,7 @@ func support() flagSet { fs.set(LZCNT) fs.set(POPCNT) } + fs.setIf((c&(1<<0)) != 0, LAHF) fs.setIf((c&(1<<10)) != 0, IBS) fs.setIf((d&(1<<31)) != 0, AMD3DNOW) fs.setIf((d&(1<<30)) != 0, AMD3DNOWEXT) diff --git a/vendor/github.com/klauspost/cpuid/v2/detect_arm64.go b/vendor/github.com/klauspost/cpuid/v2/detect_arm64.go index 9bf9f77f..9a53504a 100644 --- a/vendor/github.com/klauspost/cpuid/v2/detect_arm64.go +++ b/vendor/github.com/klauspost/cpuid/v2/detect_arm64.go @@ -1,6 +1,7 @@ // Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file. -//+build arm64,!gccgo,!noasm,!appengine +//go:build arm64 && !gccgo && !noasm && !appengine +// +build arm64,!gccgo,!noasm,!appengine package cpuid diff --git a/vendor/github.com/klauspost/cpuid/v2/detect_ref.go b/vendor/github.com/klauspost/cpuid/v2/detect_ref.go index e9c8606a..9636c2bc 100644 --- a/vendor/github.com/klauspost/cpuid/v2/detect_ref.go +++ b/vendor/github.com/klauspost/cpuid/v2/detect_ref.go @@ -1,6 +1,7 @@ // Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file. -//+build !amd64,!386,!arm64 gccgo noasm appengine +//go:build (!amd64 && !386 && !arm64) || gccgo || noasm || appengine +// +build !amd64,!386,!arm64 gccgo noasm appengine package cpuid diff --git a/vendor/github.com/klauspost/cpuid/v2/detect_x86.go b/vendor/github.com/klauspost/cpuid/v2/detect_x86.go index 367c35c8..35678d8a 100644 --- a/vendor/github.com/klauspost/cpuid/v2/detect_x86.go +++ b/vendor/github.com/klauspost/cpuid/v2/detect_x86.go @@ -1,6 +1,7 @@ // Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file. -//+build 386,!gccgo,!noasm,!appengine amd64,!gccgo,!noasm,!appengine +//go:build (386 && !gccgo && !noasm && !appengine) || (amd64 && !gccgo && !noasm && !appengine) +// +build 386,!gccgo,!noasm,!appengine amd64,!gccgo,!noasm,!appengine package cpuid diff --git a/vendor/github.com/klauspost/cpuid/v2/featureid_string.go b/vendor/github.com/klauspost/cpuid/v2/featureid_string.go index b1fe42e4..02fe232a 100644 --- a/vendor/github.com/klauspost/cpuid/v2/featureid_string.go +++ b/vendor/github.com/klauspost/cpuid/v2/featureid_string.go @@ -36,103 +36,114 @@ func _() { _ = x[AVXSLOW-26] _ = x[BMI1-27] _ = x[BMI2-28] - _ = x[CLDEMOTE-29] - _ = x[CLMUL-30] - _ = x[CLZERO-31] - _ = x[CMOV-32] - _ = x[CPBOOST-33] - _ = x[CX16-34] - _ = x[ENQCMD-35] - _ = x[ERMS-36] - _ = x[F16C-37] - _ = x[FMA3-38] - _ = x[FMA4-39] - _ = x[GFNI-40] - _ = x[HLE-41] - _ = x[HTT-42] - _ = x[HWA-43] - _ = x[HYPERVISOR-44] - _ = x[IBPB-45] - _ = x[IBS-46] - _ = x[IBSBRNTRGT-47] - _ = x[IBSFETCHSAM-48] - _ = x[IBSFFV-49] - _ = x[IBSOPCNT-50] - _ = x[IBSOPCNTEXT-51] - _ = x[IBSOPSAM-52] - _ = x[IBSRDWROPCNT-53] - _ = x[IBSRIPINVALIDCHK-54] - _ = x[INT_WBINVD-55] - _ = x[INVLPGB-56] - _ = x[LZCNT-57] - _ = x[MCAOVERFLOW-58] - _ = x[MCOMMIT-59] - _ = x[MMX-60] - _ = x[MMXEXT-61] - _ = x[MOVDIR64B-62] - _ = x[MOVDIRI-63] - _ = x[MPX-64] - _ = x[MSRIRC-65] - _ = x[NX-66] - _ = x[POPCNT-67] - _ = x[RDPRU-68] - _ = x[RDRAND-69] - _ = x[RDSEED-70] - _ = x[RDTSCP-71] - _ = x[RTM-72] - _ = x[RTM_ALWAYS_ABORT-73] - _ = x[SERIALIZE-74] - _ = x[SGX-75] - _ = x[SGXLC-76] - _ = x[SHA-77] - _ = x[SSE-78] - _ = x[SSE2-79] - _ = x[SSE3-80] - _ = x[SSE4-81] - _ = x[SSE42-82] - _ = x[SSE4A-83] - _ = x[SSSE3-84] - _ = x[STIBP-85] - _ = x[SUCCOR-86] - _ = x[TBM-87] - _ = x[TSXLDTRK-88] - _ = x[VAES-89] - _ = x[VMX-90] - _ = x[VPCLMULQDQ-91] - _ = x[WAITPKG-92] - _ = x[WBNOINVD-93] - _ = x[XOP-94] - _ = x[AESARM-95] - _ = x[ARMCPUID-96] - _ = x[ASIMD-97] - _ = x[ASIMDDP-98] - _ = x[ASIMDHP-99] - _ = x[ASIMDRDM-100] - _ = x[ATOMICS-101] - _ = x[CRC32-102] - _ = x[DCPOP-103] - _ = x[EVTSTRM-104] - _ = x[FCMA-105] - _ = x[FP-106] - _ = x[FPHP-107] - _ = x[GPA-108] - _ = x[JSCVT-109] - _ = x[LRCPC-110] - _ = x[PMULL-111] - _ = x[SHA1-112] - _ = x[SHA2-113] - _ = x[SHA3-114] - _ = x[SHA512-115] - _ = x[SM3-116] - _ = x[SM4-117] - _ = x[SVE-118] - _ = x[lastID-119] + _ = x[CETIBT-29] + _ = x[CETSS-30] + _ = x[CLDEMOTE-31] + _ = x[CLMUL-32] + _ = x[CLZERO-33] + _ = x[CMOV-34] + _ = x[CMPXCHG8-35] + _ = x[CPBOOST-36] + _ = x[CX16-37] + _ = x[ENQCMD-38] + _ = x[ERMS-39] + _ = x[F16C-40] + _ = x[FMA3-41] + _ = x[FMA4-42] + _ = x[FXSR-43] + _ = x[FXSROPT-44] + _ = x[GFNI-45] + _ = x[HLE-46] + _ = x[HTT-47] + _ = x[HWA-48] + _ = x[HYPERVISOR-49] + _ = x[IBPB-50] + _ = x[IBS-51] + _ = x[IBSBRNTRGT-52] + _ = x[IBSFETCHSAM-53] + _ = x[IBSFFV-54] + _ = x[IBSOPCNT-55] + _ = x[IBSOPCNTEXT-56] + _ = x[IBSOPSAM-57] + _ = x[IBSRDWROPCNT-58] + _ = x[IBSRIPINVALIDCHK-59] + _ = x[INT_WBINVD-60] + _ = x[INVLPGB-61] + _ = x[LAHF-62] + _ = x[LZCNT-63] + _ = x[MCAOVERFLOW-64] + _ = x[MCOMMIT-65] + _ = x[MMX-66] + _ = x[MMXEXT-67] + _ = x[MOVBE-68] + _ = x[MOVDIR64B-69] + _ = x[MOVDIRI-70] + _ = x[MPX-71] + _ = x[MSRIRC-72] + _ = x[NX-73] + _ = x[OSXSAVE-74] + _ = x[POPCNT-75] + _ = x[RDPRU-76] + _ = x[RDRAND-77] + _ = x[RDSEED-78] + _ = x[RDTSCP-79] + _ = x[RTM-80] + _ = x[RTM_ALWAYS_ABORT-81] + _ = x[SCE-82] + _ = x[SERIALIZE-83] + _ = x[SGX-84] + _ = x[SGXLC-85] + _ = x[SHA-86] + _ = x[SSE-87] + _ = x[SSE2-88] + _ = x[SSE3-89] + _ = x[SSE4-90] + _ = x[SSE42-91] + _ = x[SSE4A-92] + _ = x[SSSE3-93] + _ = x[STIBP-94] + _ = x[SUCCOR-95] + _ = x[TBM-96] + _ = x[TSXLDTRK-97] + _ = x[VAES-98] + _ = x[VMX-99] + _ = x[VPCLMULQDQ-100] + _ = x[WAITPKG-101] + _ = x[WBNOINVD-102] + _ = x[X87-103] + _ = x[XOP-104] + _ = x[XSAVE-105] + _ = x[AESARM-106] + _ = x[ARMCPUID-107] + _ = x[ASIMD-108] + _ = x[ASIMDDP-109] + _ = x[ASIMDHP-110] + _ = x[ASIMDRDM-111] + _ = x[ATOMICS-112] + _ = x[CRC32-113] + _ = x[DCPOP-114] + _ = x[EVTSTRM-115] + _ = x[FCMA-116] + _ = x[FP-117] + _ = x[FPHP-118] + _ = x[GPA-119] + _ = x[JSCVT-120] + _ = x[LRCPC-121] + _ = x[PMULL-122] + _ = x[SHA1-123] + _ = x[SHA2-124] + _ = x[SHA3-125] + _ = x[SHA512-126] + _ = x[SM3-127] + _ = x[SM4-128] + _ = x[SVE-129] + _ = x[lastID-130] _ = x[firstID-0] } -const _FeatureID_name = "firstIDADXAESNIAMD3DNOWAMD3DNOWEXTAMXBF16AMXINT8AMXTILEAVXAVX2AVX512BF16AVX512BITALGAVX512BWAVX512CDAVX512DQAVX512ERAVX512FAVX512FP16AVX512IFMAAVX512PFAVX512VBMIAVX512VBMI2AVX512VLAVX512VNNIAVX512VP2INTERSECTAVX512VPOPCNTDQAVXSLOWBMI1BMI2CLDEMOTECLMULCLZEROCMOVCPBOOSTCX16ENQCMDERMSF16CFMA3FMA4GFNIHLEHTTHWAHYPERVISORIBPBIBSIBSBRNTRGTIBSFETCHSAMIBSFFVIBSOPCNTIBSOPCNTEXTIBSOPSAMIBSRDWROPCNTIBSRIPINVALIDCHKINT_WBINVDINVLPGBLZCNTMCAOVERFLOWMCOMMITMMXMMXEXTMOVDIR64BMOVDIRIMPXMSRIRCNXPOPCNTRDPRURDRANDRDSEEDRDTSCPRTMRTM_ALWAYS_ABORTSERIALIZESGXSGXLCSHASSESSE2SSE3SSE4SSE42SSE4ASSSE3STIBPSUCCORTBMTSXLDTRKVAESVMXVPCLMULQDQWAITPKGWBNOINVDXOPAESARMARMCPUIDASIMDASIMDDPASIMDHPASIMDRDMATOMICSCRC32DCPOPEVTSTRMFCMAFPFPHPGPAJSCVTLRCPCPMULLSHA1SHA2SHA3SHA512SM3SM4SVElastID" +const _FeatureID_name = "firstIDADXAESNIAMD3DNOWAMD3DNOWEXTAMXBF16AMXINT8AMXTILEAVXAVX2AVX512BF16AVX512BITALGAVX512BWAVX512CDAVX512DQAVX512ERAVX512FAVX512FP16AVX512IFMAAVX512PFAVX512VBMIAVX512VBMI2AVX512VLAVX512VNNIAVX512VP2INTERSECTAVX512VPOPCNTDQAVXSLOWBMI1BMI2CETIBTCETSSCLDEMOTECLMULCLZEROCMOVCMPXCHG8CPBOOSTCX16ENQCMDERMSF16CFMA3FMA4FXSRFXSROPTGFNIHLEHTTHWAHYPERVISORIBPBIBSIBSBRNTRGTIBSFETCHSAMIBSFFVIBSOPCNTIBSOPCNTEXTIBSOPSAMIBSRDWROPCNTIBSRIPINVALIDCHKINT_WBINVDINVLPGBLAHFLZCNTMCAOVERFLOWMCOMMITMMXMMXEXTMOVBEMOVDIR64BMOVDIRIMPXMSRIRCNXOSXSAVEPOPCNTRDPRURDRANDRDSEEDRDTSCPRTMRTM_ALWAYS_ABORTSCESERIALIZESGXSGXLCSHASSESSE2SSE3SSE4SSE42SSE4ASSSE3STIBPSUCCORTBMTSXLDTRKVAESVMXVPCLMULQDQWAITPKGWBNOINVDX87XOPXSAVEAESARMARMCPUIDASIMDASIMDDPASIMDHPASIMDRDMATOMICSCRC32DCPOPEVTSTRMFCMAFPFPHPGPAJSCVTLRCPCPMULLSHA1SHA2SHA3SHA512SM3SM4SVElastID" -var _FeatureID_index = [...]uint16{0, 7, 10, 15, 23, 34, 41, 48, 55, 58, 62, 72, 84, 92, 100, 108, 116, 123, 133, 143, 151, 161, 172, 180, 190, 208, 223, 230, 234, 238, 246, 251, 257, 261, 268, 272, 278, 282, 286, 290, 294, 298, 301, 304, 307, 317, 321, 324, 334, 345, 351, 359, 370, 378, 390, 406, 416, 423, 428, 439, 446, 449, 455, 464, 471, 474, 480, 482, 488, 493, 499, 505, 511, 514, 530, 539, 542, 547, 550, 553, 557, 561, 565, 570, 575, 580, 585, 591, 594, 602, 606, 609, 619, 626, 634, 637, 643, 651, 656, 663, 670, 678, 685, 690, 695, 702, 706, 708, 712, 715, 720, 725, 730, 734, 738, 742, 748, 751, 754, 757, 763} +var _FeatureID_index = [...]uint16{0, 7, 10, 15, 23, 34, 41, 48, 55, 58, 62, 72, 84, 92, 100, 108, 116, 123, 133, 143, 151, 161, 172, 180, 190, 208, 223, 230, 234, 238, 244, 249, 257, 262, 268, 272, 280, 287, 291, 297, 301, 305, 309, 313, 317, 324, 328, 331, 334, 337, 347, 351, 354, 364, 375, 381, 389, 400, 408, 420, 436, 446, 453, 457, 462, 473, 480, 483, 489, 494, 503, 510, 513, 519, 521, 528, 534, 539, 545, 551, 557, 560, 576, 579, 588, 591, 596, 599, 602, 606, 610, 614, 619, 624, 629, 634, 640, 643, 651, 655, 658, 668, 675, 683, 686, 689, 694, 700, 708, 713, 720, 727, 735, 742, 747, 752, 759, 763, 765, 769, 772, 777, 782, 787, 791, 795, 799, 805, 808, 811, 814, 820} func (i FeatureID) String() string { if i < 0 || i >= FeatureID(len(_FeatureID_index)-1) { diff --git a/vendor/github.com/klauspost/cpuid/v2/os_other_arm64.go b/vendor/github.com/klauspost/cpuid/v2/os_other_arm64.go index 1a951e6c..8733ba34 100644 --- a/vendor/github.com/klauspost/cpuid/v2/os_other_arm64.go +++ b/vendor/github.com/klauspost/cpuid/v2/os_other_arm64.go @@ -1,8 +1,7 @@ // Copyright (c) 2020 Klaus Post, released under MIT License. See LICENSE file. -// +build arm64 -// +build !linux -// +build !darwin +//go:build arm64 && !linux && !darwin +// +build arm64,!linux,!darwin package cpuid diff --git a/vendor/github.com/klauspost/cpuid/v2/os_safe_linux_arm64.go b/vendor/github.com/klauspost/cpuid/v2/os_safe_linux_arm64.go index 4d0b8b46..f8f201b5 100644 --- a/vendor/github.com/klauspost/cpuid/v2/os_safe_linux_arm64.go +++ b/vendor/github.com/klauspost/cpuid/v2/os_safe_linux_arm64.go @@ -1,6 +1,7 @@ // Copyright (c) 2021 Klaus Post, released under MIT License. See LICENSE file. -//+build nounsafe +//go:build nounsafe +// +build nounsafe package cpuid diff --git a/vendor/github.com/klauspost/cpuid/v2/os_unsafe_linux_arm64.go b/vendor/github.com/klauspost/cpuid/v2/os_unsafe_linux_arm64.go index 32980028..92af622e 100644 --- a/vendor/github.com/klauspost/cpuid/v2/os_unsafe_linux_arm64.go +++ b/vendor/github.com/klauspost/cpuid/v2/os_unsafe_linux_arm64.go @@ -1,6 +1,7 @@ // Copyright (c) 2021 Klaus Post, released under MIT License. See LICENSE file. -//+build !nounsafe +//go:build !nounsafe +// +build !nounsafe package cpuid |