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authorWim <wim@42.be>2021-07-31 18:27:55 +0200
committerGitHub <noreply@github.com>2021-07-31 18:27:55 +0200
commit44f3e2557dad86129419ed098c29e67638519f4f (patch)
tree17b8ddba49057cd8bf39cdf2618b31c7f6bc8c6a /vendor/golang.org/x/sys/cpu/cpu.go
parent1f365c716eae44b64dc5bdace5cb70441d7eb4c2 (diff)
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Update vendor (#1560)
Diffstat (limited to 'vendor/golang.org/x/sys/cpu/cpu.go')
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu.go5
1 files changed, 2 insertions, 3 deletions
diff --git a/vendor/golang.org/x/sys/cpu/cpu.go b/vendor/golang.org/x/sys/cpu/cpu.go
index f77701fe..abbec2d4 100644
--- a/vendor/golang.org/x/sys/cpu/cpu.go
+++ b/vendor/golang.org/x/sys/cpu/cpu.go
@@ -154,14 +154,13 @@ var MIPS64X struct {
// For ppc64/ppc64le, it is safe to check only for ISA level starting on ISA v3.00,
// since there are no optional categories. There are some exceptions that also
// require kernel support to work (DARN, SCV), so there are feature bits for
-// those as well. The minimum processor requirement is POWER8 (ISA 2.07).
-// The struct is padded to avoid false sharing.
+// those as well. The struct is padded to avoid false sharing.
var PPC64 struct {
_ CacheLinePad
HasDARN bool // Hardware random number generator (requires kernel enablement)
HasSCV bool // Syscall vectored (requires kernel enablement)
IsPOWER8 bool // ISA v2.07 (POWER8)
- IsPOWER9 bool // ISA v3.00 (POWER9)
+ IsPOWER9 bool // ISA v3.00 (POWER9), implies IsPOWER8
_ CacheLinePad
}