From 51062863a5c34d81e296cf15c61140911037cf3b Mon Sep 17 00:00:00 2001 From: Wim Date: Mon, 6 Aug 2018 21:47:05 +0200 Subject: Use mod vendor for vendored directory (backwards compatible) --- vendor/golang.org/x/arch/arm/armasm/LICENSE | 27 - vendor/golang.org/x/arch/arm/armasm/decode.go | 567 -- vendor/golang.org/x/arch/arm/armasm/gnu.go | 164 - vendor/golang.org/x/arch/arm/armasm/inst.go | 438 -- vendor/golang.org/x/arch/arm/armasm/plan9x.go | 215 - vendor/golang.org/x/arch/arm/armasm/tables.go | 9448 ------------------------- 6 files changed, 10859 deletions(-) delete mode 100644 vendor/golang.org/x/arch/arm/armasm/LICENSE delete mode 100644 vendor/golang.org/x/arch/arm/armasm/decode.go delete mode 100644 vendor/golang.org/x/arch/arm/armasm/gnu.go delete mode 100644 vendor/golang.org/x/arch/arm/armasm/inst.go delete mode 100644 vendor/golang.org/x/arch/arm/armasm/plan9x.go delete mode 100644 vendor/golang.org/x/arch/arm/armasm/tables.go (limited to 'vendor/golang.org/x/arch/arm') diff --git a/vendor/golang.org/x/arch/arm/armasm/LICENSE b/vendor/golang.org/x/arch/arm/armasm/LICENSE deleted file mode 100644 index d29b3726..00000000 --- a/vendor/golang.org/x/arch/arm/armasm/LICENSE +++ /dev/null @@ -1,27 +0,0 @@ -Copyright (c) 2015 The Go Authors. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are -met: - - * Redistributions of source code must retain the above copyright -notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above -copyright notice, this list of conditions and the following disclaimer -in the documentation and/or other materials provided with the -distribution. - * Neither the name of Google Inc. nor the names of its -contributors may be used to endorse or promote products derived from -this software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/vendor/golang.org/x/arch/arm/armasm/decode.go b/vendor/golang.org/x/arch/arm/armasm/decode.go deleted file mode 100644 index 6b4d7384..00000000 --- a/vendor/golang.org/x/arch/arm/armasm/decode.go +++ /dev/null @@ -1,567 +0,0 @@ -// Copyright 2014 The Go Authors. All rights reserved. -// Use of this source code is governed by a BSD-style -// license that can be found in the LICENSE file. - -package armasm - -import ( - "encoding/binary" - "fmt" -) - -// An instFormat describes the format of an instruction encoding. -// An instruction with 32-bit value x matches the format if x&mask == value -// and the condition matches. -// The condition matches if x>>28 == 0xF && value>>28==0xF -// or if x>>28 != 0xF and value>>28 == 0. -// If x matches the format, then the rest of the fields describe how to interpret x. -// The opBits describe bits that should be extracted from x and added to the opcode. -// For example opBits = 0x1234 means that the value -// (2 bits at offset 1) followed by (4 bits at offset 3) -// should be added to op. -// Finally the args describe how to decode the instruction arguments. -// args is stored as a fixed-size array; if there are fewer than len(args) arguments, -// args[i] == 0 marks the end of the argument list. -type instFormat struct { - mask uint32 - value uint32 - priority int8 - op Op - opBits uint64 - args instArgs -} - -type instArgs [4]instArg - -var ( - errMode = fmt.Errorf("unsupported execution mode") - errShort = fmt.Errorf("truncated instruction") - errUnknown = fmt.Errorf("unknown instruction") -) - -var decoderCover []bool - -// Decode decodes the leading bytes in src as a single instruction. -func Decode(src []byte, mode Mode) (inst Inst, err error) { - if mode != ModeARM { - return Inst{}, errMode - } - if len(src) < 4 { - return Inst{}, errShort - } - - if decoderCover == nil { - decoderCover = make([]bool, len(instFormats)) - } - - x := binary.LittleEndian.Uint32(src) - - // The instFormat table contains both conditional and unconditional instructions. - // Considering only the top 4 bits, the conditional instructions use mask=0, value=0, - // while the unconditional instructions use mask=f, value=f. - // Prepare a version of x with the condition cleared to 0 in conditional instructions - // and then assume mask=f during matching. - const condMask = 0xf0000000 - xNoCond := x - if x&condMask != condMask { - xNoCond &^= condMask - } - var priority int8 -Search: - for i := range instFormats { - f := &instFormats[i] - if xNoCond&(f.mask|condMask) != f.value || f.priority <= priority { - continue - } - delta := uint32(0) - deltaShift := uint(0) - for opBits := f.opBits; opBits != 0; opBits >>= 16 { - n := uint(opBits & 0xFF) - off := uint((opBits >> 8) & 0xFF) - delta |= (x >> off) & (1<> 8) & (1<<4 - 1)) - case arg_R_12: - return Reg((x >> 12) & (1<<4 - 1)) - case arg_R_16: - return Reg((x >> 16) & (1<<4 - 1)) - - case arg_R_12_nzcv: - r := Reg((x >> 12) & (1<<4 - 1)) - if r == R15 { - return APSR_nzcv - } - return r - - case arg_R_16_WB: - mode := AddrLDM - if (x>>21)&1 != 0 { - mode = AddrLDM_WB - } - return Mem{Base: Reg((x >> 16) & (1<<4 - 1)), Mode: mode} - - case arg_R_rotate: - Rm := Reg(x & (1<<4 - 1)) - typ, count := decodeShift(x) - // ROR #0 here means ROR #0, but decodeShift rewrites to RRX #1. - if typ == RotateRightExt { - return Reg(Rm) - } - return RegShift{Rm, typ, uint8(count)} - - case arg_R_shift_R: - Rm := Reg(x & (1<<4 - 1)) - Rs := Reg((x >> 8) & (1<<4 - 1)) - typ := Shift((x >> 5) & (1<<2 - 1)) - return RegShiftReg{Rm, typ, Rs} - - case arg_R_shift_imm: - Rm := Reg(x & (1<<4 - 1)) - typ, count := decodeShift(x) - if typ == ShiftLeft && count == 0 { - return Reg(Rm) - } - return RegShift{Rm, typ, uint8(count)} - - case arg_R1_0: - return Reg((x & (1<<4 - 1))) - case arg_R1_12: - return Reg(((x >> 12) & (1<<4 - 1))) - case arg_R2_0: - return Reg((x & (1<<4 - 1)) | 1) - case arg_R2_12: - return Reg(((x >> 12) & (1<<4 - 1)) | 1) - - case arg_SP: - return SP - - case arg_Sd_Dd: - v := (x >> 12) & (1<<4 - 1) - vx := (x >> 22) & 1 - sz := (x >> 8) & 1 - if sz != 0 { - return D0 + Reg(vx<<4+v) - } else { - return S0 + Reg(v<<1+vx) - } - - case arg_Dd_Sd: - return decodeArg(arg_Sd_Dd, x^(1<<8)) - - case arg_Sd: - v := (x >> 12) & (1<<4 - 1) - vx := (x >> 22) & 1 - return S0 + Reg(v<<1+vx) - - case arg_Sm_Dm: - v := (x >> 0) & (1<<4 - 1) - vx := (x >> 5) & 1 - sz := (x >> 8) & 1 - if sz != 0 { - return D0 + Reg(vx<<4+v) - } else { - return S0 + Reg(v<<1+vx) - } - - case arg_Sm: - v := (x >> 0) & (1<<4 - 1) - vx := (x >> 5) & 1 - return S0 + Reg(v<<1+vx) - - case arg_Dn_half: - v := (x >> 16) & (1<<4 - 1) - vx := (x >> 7) & 1 - return RegX{D0 + Reg(vx<<4+v), int((x >> 21) & 1)} - - case arg_Sn_Dn: - v := (x >> 16) & (1<<4 - 1) - vx := (x >> 7) & 1 - sz := (x >> 8) & 1 - if sz != 0 { - return D0 + Reg(vx<<4+v) - } else { - return S0 + Reg(v<<1+vx) - } - - case arg_Sn: - v := (x >> 16) & (1<<4 - 1) - vx := (x >> 7) & 1 - return S0 + Reg(v<<1+vx) - - case arg_const: - v := x & (1<<8 - 1) - rot := (x >> 8) & (1<<4 - 1) * 2 - if rot > 0 && v&3 == 0 { - // could rotate less - return ImmAlt{uint8(v), uint8(rot)} - } - if rot >= 24 && ((v<<(32-rot))&0xFF)>>(32-rot) == v { - // could wrap around to rot==0. - return ImmAlt{uint8(v), uint8(rot)} - } - return Imm(v>>rot | v<<(32-rot)) - - case arg_endian: - return Endian((x >> 9) & 1) - - case arg_fbits: - return Imm((16 << ((x >> 7) & 1)) - ((x&(1<<4-1))<<1 | (x>>5)&1)) - - case arg_fp_0: - return Imm(0) - - case arg_imm24: - return Imm(x & (1<<24 - 1)) - - case arg_imm5: - return Imm((x >> 7) & (1<<5 - 1)) - - case arg_imm5_32: - x = (x >> 7) & (1<<5 - 1) - if x == 0 { - x = 32 - } - return Imm(x) - - case arg_imm5_nz: - x = (x >> 7) & (1<<5 - 1) - if x == 0 { - return nil - } - return Imm(x) - - case arg_imm_4at16_12at0: - return Imm((x>>16)&(1<<4-1)<<12 | x&(1<<12-1)) - - case arg_imm_12at8_4at0: - return Imm((x>>8)&(1<<12-1)<<4 | x&(1<<4-1)) - - case arg_imm_vfp: - x = (x>>16)&(1<<4-1)<<4 | x&(1<<4-1) - return Imm(x) - - case arg_label24: - imm := (x & (1<<24 - 1)) << 2 - return PCRel(int32(imm<<6) >> 6) - - case arg_label24H: - h := (x >> 24) & 1 - imm := (x&(1<<24-1))<<2 | h<<1 - return PCRel(int32(imm<<6) >> 6) - - case arg_label_m_12: - d := int32(x & (1<<12 - 1)) - return Mem{Base: PC, Mode: AddrOffset, Offset: int16(-d)} - - case arg_label_p_12: - d := int32(x & (1<<12 - 1)) - return Mem{Base: PC, Mode: AddrOffset, Offset: int16(d)} - - case arg_label_pm_12: - d := int32(x & (1<<12 - 1)) - u := (x >> 23) & 1 - if u == 0 { - d = -d - } - return Mem{Base: PC, Mode: AddrOffset, Offset: int16(d)} - - case arg_label_pm_4_4: - d := int32((x>>8)&(1<<4-1)<<4 | x&(1<<4-1)) - u := (x >> 23) & 1 - if u == 0 { - d = -d - } - return PCRel(d) - - case arg_lsb_width: - lsb := (x >> 7) & (1<<5 - 1) - msb := (x >> 16) & (1<<5 - 1) - if msb < lsb || msb >= 32 { - return nil - } - return Imm(msb + 1 - lsb) - - case arg_mem_R: - Rn := Reg((x >> 16) & (1<<4 - 1)) - return Mem{Base: Rn, Mode: AddrOffset} - - case arg_mem_R_pm_R_postindex: - // Treat [],+/- like [,+/-{,}]{!} - // by forcing shift bits to <<0 and P=0, W=0 (postindex=true). - return decodeArg(arg_mem_R_pm_R_shift_imm_W, x&^((1<<7-1)<<5|1<<24|1<<21)) - - case arg_mem_R_pm_R_W: - // Treat [,+/-]{!} like [,+/-{,}]{!} - // by forcing shift bits to <<0. - return decodeArg(arg_mem_R_pm_R_shift_imm_W, x&^((1<<7-1)<<5)) - - case arg_mem_R_pm_R_shift_imm_offset: - // Treat [],+/-{,} like [,+/-{,}]{!} - // by forcing P=1, W=0 (index=false, wback=false). - return decodeArg(arg_mem_R_pm_R_shift_imm_W, x&^(1<<21)|1<<24) - - case arg_mem_R_pm_R_shift_imm_postindex: - // Treat [],+/-{,} like [,+/-{,}]{!} - // by forcing P=0, W=0 (postindex=true). - return decodeArg(arg_mem_R_pm_R_shift_imm_W, x&^(1<<24|1<<21)) - - case arg_mem_R_pm_R_shift_imm_W: - Rn := Reg((x >> 16) & (1<<4 - 1)) - Rm := Reg(x & (1<<4 - 1)) - typ, count := decodeShift(x) - u := (x >> 23) & 1 - w := (x >> 21) & 1 - p := (x >> 24) & 1 - if p == 0 && w == 1 { - return nil - } - sign := int8(+1) - if u == 0 { - sign = -1 - } - mode := AddrMode(uint8(p<<1) | uint8(w^1)) - return Mem{Base: Rn, Mode: mode, Sign: sign, Index: Rm, Shift: typ, Count: count} - - case arg_mem_R_pm_imm12_offset: - // Treat [,#+/-] like [{,#+/-}]{!} - // by forcing P=1, W=0 (index=false, wback=false). - return decodeArg(arg_mem_R_pm_imm12_W, x&^(1<<21)|1<<24) - - case arg_mem_R_pm_imm12_postindex: - // Treat [],#+/- like [{,#+/-}]{!} - // by forcing P=0, W=0 (postindex=true). - return decodeArg(arg_mem_R_pm_imm12_W, x&^(1<<24|1<<21)) - - case arg_mem_R_pm_imm12_W: - Rn := Reg((x >> 16) & (1<<4 - 1)) - u := (x >> 23) & 1 - w := (x >> 21) & 1 - p := (x >> 24) & 1 - if p == 0 && w == 1 { - return nil - } - sign := int8(+1) - if u == 0 { - sign = -1 - } - imm := int16(x & (1<<12 - 1)) - mode := AddrMode(uint8(p<<1) | uint8(w^1)) - return Mem{Base: Rn, Mode: mode, Offset: int16(sign) * imm} - - case arg_mem_R_pm_imm8_postindex: - // Treat [],#+/- like [{,#+/-}]{!} - // by forcing P=0, W=0 (postindex=true). - return decodeArg(arg_mem_R_pm_imm8_W, x&^(1<<24|1<<21)) - - case arg_mem_R_pm_imm8_W: - Rn := Reg((x >> 16) & (1<<4 - 1)) - u := (x >> 23) & 1 - w := (x >> 21) & 1 - p := (x >> 24) & 1 - if p == 0 && w == 1 { - return nil - } - sign := int8(+1) - if u == 0 { - sign = -1 - } - imm := int16((x>>8)&(1<<4-1)<<4 | x&(1<<4-1)) - mode := AddrMode(uint8(p<<1) | uint8(w^1)) - return Mem{Base: Rn, Mode: mode, Offset: int16(sign) * imm} - - case arg_mem_R_pm_imm8at0_offset: - Rn := Reg((x >> 16) & (1<<4 - 1)) - u := (x >> 23) & 1 - sign := int8(+1) - if u == 0 { - sign = -1 - } - imm := int16(x&(1<<8-1)) << 2 - return Mem{Base: Rn, Mode: AddrOffset, Offset: int16(sign) * imm} - - case arg_option: - return Imm(x & (1<<4 - 1)) - - case arg_registers: - return RegList(x & (1<<16 - 1)) - - case arg_registers2: - x &= 1<<16 - 1 - n := 0 - for i := 0; i < 16; i++ { - if x>>uint(i)&1 != 0 { - n++ - } - } - if n < 2 { - return nil - } - return RegList(x) - - case arg_registers1: - Rt := (x >> 12) & (1<<4 - 1) - return RegList(1 << Rt) - - case arg_satimm4: - return Imm((x >> 16) & (1<<4 - 1)) - - case arg_satimm5: - return Imm((x >> 16) & (1<<5 - 1)) - - case arg_satimm4m1: - return Imm((x>>16)&(1<<4-1) + 1) - - case arg_satimm5m1: - return Imm((x>>16)&(1<<5-1) + 1) - - case arg_widthm1: - return Imm((x>>16)&(1<<5-1) + 1) - - } -} - -// decodeShift decodes the shift-by-immediate encoded in x. -func decodeShift(x uint32) (Shift, uint8) { - count := (x >> 7) & (1<<5 - 1) - typ := Shift((x >> 5) & (1<<2 - 1)) - switch typ { - case ShiftRight, ShiftRightSigned: - if count == 0 { - count = 32 - } - case RotateRight: - if count == 0 { - typ = RotateRightExt - count = 1 - } - } - return typ, uint8(count) -} diff --git a/vendor/golang.org/x/arch/arm/armasm/gnu.go b/vendor/golang.org/x/arch/arm/armasm/gnu.go deleted file mode 100644 index 1a97a5a8..00000000 --- a/vendor/golang.org/x/arch/arm/armasm/gnu.go +++ /dev/null @@ -1,164 +0,0 @@ -// Copyright 2014 The Go Authors. All rights reserved. -// Use of this source code is governed by a BSD-style -// license that can be found in the LICENSE file. - -package armasm - -import ( - "bytes" - "fmt" - "strings" -) - -var saveDot = strings.NewReplacer( - ".F16", "_dot_F16", - ".F32", "_dot_F32", - ".F64", "_dot_F64", - ".S32", "_dot_S32", - ".U32", "_dot_U32", - ".FXS", "_dot_S", - ".FXU", "_dot_U", - ".32", "_dot_32", -) - -// GNUSyntax returns the GNU assembler syntax for the instruction, as defined by GNU binutils. -// This form typically matches the syntax defined in the ARM Reference Manual. -func GNUSyntax(inst Inst) string { - var buf bytes.Buffer - op := inst.Op.String() - op = saveDot.Replace(op) - op = strings.Replace(op, ".", "", -1) - op = strings.Replace(op, "_dot_", ".", -1) - op = strings.ToLower(op) - buf.WriteString(op) - sep := " " - for i, arg := range inst.Args { - if arg == nil { - break - } - text := gnuArg(&inst, i, arg) - if text == "" { - continue - } - buf.WriteString(sep) - sep = ", " - buf.WriteString(text) - } - return buf.String() -} - -func gnuArg(inst *Inst, argIndex int, arg Arg) string { - switch inst.Op &^ 15 { - case LDRD_EQ, LDREXD_EQ, STRD_EQ: - if argIndex == 1 { - // second argument in consecutive pair not printed - return "" - } - case STREXD_EQ: - if argIndex == 2 { - // second argument in consecutive pair not printed - return "" - } - } - - switch arg := arg.(type) { - case Imm: - switch inst.Op &^ 15 { - case BKPT_EQ: - return fmt.Sprintf("%#04x", uint32(arg)) - case SVC_EQ: - return fmt.Sprintf("%#08x", uint32(arg)) - } - return fmt.Sprintf("#%d", int32(arg)) - - case ImmAlt: - return fmt.Sprintf("#%d, %d", arg.Val, arg.Rot) - - case Mem: - R := gnuArg(inst, -1, arg.Base) - X := "" - if arg.Sign != 0 { - X = "" - if arg.Sign < 0 { - X = "-" - } - X += gnuArg(inst, -1, arg.Index) - if arg.Shift == ShiftLeft && arg.Count == 0 { - // nothing - } else if arg.Shift == RotateRightExt { - X += ", rrx" - } else { - X += fmt.Sprintf(", %s #%d", strings.ToLower(arg.Shift.String()), arg.Count) - } - } else { - X = fmt.Sprintf("#%d", arg.Offset) - } - - switch arg.Mode { - case AddrOffset: - if X == "#0" { - return fmt.Sprintf("[%s]", R) - } - return fmt.Sprintf("[%s, %s]", R, X) - case AddrPreIndex: - return fmt.Sprintf("[%s, %s]!", R, X) - case AddrPostIndex: - return fmt.Sprintf("[%s], %s", R, X) - case AddrLDM: - if X == "#0" { - return R - } - case AddrLDM_WB: - if X == "#0" { - return R + "!" - } - } - return fmt.Sprintf("[%s Mode(%d) %s]", R, int(arg.Mode), X) - - case PCRel: - return fmt.Sprintf(".%+#x", int32(arg)+4) - - case Reg: - switch inst.Op &^ 15 { - case LDREX_EQ: - if argIndex == 0 { - return fmt.Sprintf("r%d", int32(arg)) - } - } - switch arg { - case R10: - return "sl" - case R11: - return "fp" - case R12: - return "ip" - } - - case RegList: - var buf bytes.Buffer - fmt.Fprintf(&buf, "{") - sep := "" - for i := 0; i < 16; i++ { - if arg&(1<= Op(len(opstr)) || opstr[op] == "" { - return fmt.Sprintf("Op(%d)", int(op)) - } - return opstr[op] -} - -// An Inst is a single instruction. -type Inst struct { - Op Op // Opcode mnemonic - Enc uint32 // Raw encoding bits. - Len int // Length of encoding in bytes. - Args Args // Instruction arguments, in ARM manual order. -} - -func (i Inst) String() string { - var buf bytes.Buffer - buf.WriteString(i.Op.String()) - for j, arg := range i.Args { - if arg == nil { - break - } - if j == 0 { - buf.WriteString(" ") - } else { - buf.WriteString(", ") - } - buf.WriteString(arg.String()) - } - return buf.String() -} - -// An Args holds the instruction arguments. -// If an instruction has fewer than 4 arguments, -// the final elements in the array are nil. -type Args [4]Arg - -// An Arg is a single instruction argument, one of these types: -// Endian, Imm, Mem, PCRel, Reg, RegList, RegShift, RegShiftReg. -type Arg interface { - IsArg() - String() string -} - -type Float32Imm float32 - -func (Float32Imm) IsArg() {} - -func (f Float32Imm) String() string { - return fmt.Sprintf("#%v", float32(f)) -} - -type Float64Imm float32 - -func (Float64Imm) IsArg() {} - -func (f Float64Imm) String() string { - return fmt.Sprintf("#%v", float64(f)) -} - -// An Imm is an integer constant. -type Imm uint32 - -func (Imm) IsArg() {} - -func (i Imm) String() string { - return fmt.Sprintf("#%#x", uint32(i)) -} - -// A ImmAlt is an alternate encoding of an integer constant. -type ImmAlt struct { - Val uint8 - Rot uint8 -} - -func (ImmAlt) IsArg() {} - -func (i ImmAlt) Imm() Imm { - v := uint32(i.Val) - r := uint(i.Rot) - return Imm(v>>r | v<<(32-r)) -} - -func (i ImmAlt) String() string { - return fmt.Sprintf("#%#x, %d", i.Val, i.Rot) -} - -// A Label is a text (code) address. -type Label uint32 - -func (Label) IsArg() {} - -func (i Label) String() string { - return fmt.Sprintf("%#x", uint32(i)) -} - -// A Reg is a single register. -// The zero value denotes R0, not the absence of a register. -type Reg uint8 - -const ( - R0 Reg = iota - R1 - R2 - R3 - R4 - R5 - R6 - R7 - R8 - R9 - R10 - R11 - R12 - R13 - R14 - R15 - - S0 - S1 - S2 - S3 - S4 - S5 - S6 - S7 - S8 - S9 - S10 - S11 - S12 - S13 - S14 - S15 - S16 - S17 - S18 - S19 - S20 - S21 - S22 - S23 - S24 - S25 - S26 - S27 - S28 - S29 - S30 - S31 - - D0 - D1 - D2 - D3 - D4 - D5 - D6 - D7 - D8 - D9 - D10 - D11 - D12 - D13 - D14 - D15 - D16 - D17 - D18 - D19 - D20 - D21 - D22 - D23 - D24 - D25 - D26 - D27 - D28 - D29 - D30 - D31 - - APSR - APSR_nzcv - FPSCR - - SP = R13 - LR = R14 - PC = R15 -) - -func (Reg) IsArg() {} - -func (r Reg) String() string { - switch r { - case APSR: - return "APSR" - case APSR_nzcv: - return "APSR_nzcv" - case FPSCR: - return "FPSCR" - case SP: - return "SP" - case PC: - return "PC" - case LR: - return "LR" - } - if R0 <= r && r <= R15 { - return fmt.Sprintf("R%d", int(r-R0)) - } - if S0 <= r && r <= S31 { - return fmt.Sprintf("S%d", int(r-S0)) - } - if D0 <= r && r <= D31 { - return fmt.Sprintf("D%d", int(r-D0)) - } - return fmt.Sprintf("Reg(%d)", int(r)) -} - -// A RegX represents a fraction of a multi-value register. -// The Index field specifies the index number, -// but the size of the fraction is not specified. -// It must be inferred from the instruction and the register type. -// For example, in a VMOV instruction, RegX{D5, 1} represents -// the top 32 bits of the 64-bit D5 register. -type RegX struct { - Reg Reg - Index int -} - -func (RegX) IsArg() {} - -func (r RegX) String() string { - return fmt.Sprintf("%s[%d]", r.Reg, r.Index) -} - -// A RegList is a register list. -// Bits at indexes x = 0 through 15 indicate whether the corresponding Rx register is in the list. -type RegList uint16 - -func (RegList) IsArg() {} - -func (r RegList) String() string { - var buf bytes.Buffer - fmt.Fprintf(&buf, "{") - sep := "" - for i := 0; i < 16; i++ { - if r&(1< is a lie; the assembler uses @> 0 -// instead of @x> 1, but i wanted to be clear that it -// was a different operation (rotate right extended, not rotate right). -var plan9Shift = []string{"<<", ">>", "->", "@>", "@x>"} - -func plan9Arg(inst *Inst, pc uint64, symname func(uint64) (string, uint64), arg Arg) string { - switch a := arg.(type) { - case Endian: - - case Imm: - return fmt.Sprintf("$%d", int(a)) - - case Mem: - - case PCRel: - addr := uint32(pc) + 8 + uint32(a) - if s, base := symname(uint64(addr)); s != "" && uint64(addr) == base { - return fmt.Sprintf("%s(SB)", s) - } - return fmt.Sprintf("%#x", addr) - - case Reg: - if a < 16 { - return fmt.Sprintf("R%d", int(a)) - } - - case RegList: - var buf bytes.Buffer - start := -2 - end := -2 - fmt.Fprintf(&buf, "[") - flush := func() { - if start >= 0 { - if buf.Len() > 1 { - fmt.Fprintf(&buf, ",") - } - if start == end { - fmt.Fprintf(&buf, "R%d", start) - } else { - fmt.Fprintf(&buf, "R%d-R%d", start, end) - } - start = -2 - end = -2 - } - } - for i := 0; i < 16; i++ { - if a&(1< ,,# cond:4|0|0|1|0|1|0|1|S|Rn:4|Rd:4|imm12:12 - {0x0fe00090, 0x00a00010, 4, ADC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // ADC{S} ,,, cond:4|0|0|0|0|1|0|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 - {0x0fe00010, 0x00a00000, 2, ADC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // ADC{S} ,,{,} cond:4|0|0|0|0|1|0|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 - {0x0fe00000, 0x02800000, 2, ADD_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // ADD{S} ,,# cond:4|0|0|1|0|1|0|0|S|Rn:4|Rd:4|imm12:12 - {0x0fe00090, 0x00800010, 4, ADD_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // ADD{S} ,,, cond:4|0|0|0|0|1|0|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 - {0x0fe00010, 0x00800000, 2, ADD_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // ADD{S} ,,{,} cond:4|0|0|0|0|1|0|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 - {0x0fef0000, 0x028d0000, 2, ADD_EQ, 0x14011c04, instArgs{arg_R_12, arg_SP, arg_const}}, // ADD{S} ,SP,# cond:4|0|0|1|0|1|0|0|S|1|1|0|1|Rd:4|imm12:12 - {0x0fef0010, 0x008d0000, 2, ADD_EQ, 0x14011c04, instArgs{arg_R_12, arg_SP, arg_R_shift_imm}}, // ADD{S} ,SP,{,} cond:4|0|0|0|0|1|0|0|S|1|1|0|1|Rd:4|imm5:5|type:2|0|Rm:4 - {0x0fe00000, 0x02000000, 2, AND_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // AND{S} ,,# cond:4|0|0|1|0|0|0|0|S|Rn:4|Rd:4|imm12:12 - {0x0fe00090, 0x00000010, 4, AND_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // AND{S} ,,, cond:4|0|0|0|0|0|0|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 - {0x0fe00010, 0x00000000, 2, AND_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // AND{S} ,,{,} cond:4|0|0|0|0|0|0|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 - {0x0fef0070, 0x01a00040, 4, ASR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_imm5_32}}, // ASR{S} ,,# cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|1|0|0|Rm:4 - {0x0fef00f0, 0x01a00050, 4, ASR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_R_8}}, // ASR{S} ,, cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|1|0|1|Rn:4 - {0x0f000000, 0x0a000000, 4, B_EQ, 0x1c04, instArgs{arg_label24}}, // B cond:4|1|0|1|0|imm24:24 - {0x0fe0007f, 0x07c0001f, 4, BFC_EQ, 0x1c04, instArgs{arg_R_12, arg_imm5, arg_lsb_width}}, // BFC ,#,# cond:4|0|1|1|1|1|1|0|msb:5|Rd:4|lsb:5|0|0|1|1|1|1|1 - {0x0fe00070, 0x07c00010, 2, BFI_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_imm5, arg_lsb_width}}, // BFI ,,#,# cond:4|0|1|1|1|1|1|0|msb:5|Rd:4|lsb:5|0|0|1|Rn:4 - {0x0fe00000, 0x03c00000, 2, BIC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // BIC{S} ,,# cond:4|0|0|1|1|1|1|0|S|Rn:4|Rd:4|imm12:12 - {0x0fe00090, 0x01c00010, 4, BIC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // BIC{S} ,,, cond:4|0|0|0|1|1|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 - {0x0fe00010, 0x01c00000, 2, BIC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // BIC{S} ,,{,} cond:4|0|0|0|1|1|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 - {0x0ff000f0, 0x01200070, 4, BKPT_EQ, 0x1c04, instArgs{arg_imm_12at8_4at0}}, // BKPT # cond:4|0|0|0|1|0|0|1|0|imm12:12|0|1|1|1|imm4:4 - {0x0f000000, 0x0b000000, 4, BL_EQ, 0x1c04, instArgs{arg_label24}}, // BL cond:4|1|0|1|1|imm24:24 - {0xfe000000, 0xfa000000, 4, BLX, 0x0, instArgs{arg_label24H}}, // BLX 1|1|1|1|1|0|1|H|imm24:24 - {0x0ffffff0, 0x012fff30, 4, BLX_EQ, 0x1c04, instArgs{arg_R_0}}, // BLX cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 - {0x0ff000f0, 0x012fff30, 3, BLX_EQ, 0x1c04, instArgs{arg_R_0}}, // BLX cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 - {0x0ffffff0, 0x012fff10, 4, BX_EQ, 0x1c04, instArgs{arg_R_0}}, // BX cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 - {0x0ff000f0, 0x012fff10, 3, BX_EQ, 0x1c04, instArgs{arg_R_0}}, // BX cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 - {0x0ffffff0, 0x012fff20, 4, BXJ_EQ, 0x1c04, instArgs{arg_R_0}}, // BXJ cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|0|Rm:4 - {0x0ff000f0, 0x012fff20, 3, BXJ_EQ, 0x1c04, instArgs{arg_R_0}}, // BXJ cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|0|Rm:4 - {0xffffffff, 0xf57ff01f, 4, CLREX, 0x0, instArgs{}}, // CLREX 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|1|(1)|(1)|(1)|(1) - {0xfff000f0, 0xf57ff01f, 3, CLREX, 0x0, instArgs{}}, // CLREX 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|1|(1)|(1)|(1)|(1) - {0x0fff0ff0, 0x016f0f10, 4, CLZ_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // CLZ , cond:4|0|0|0|1|0|1|1|0|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 - {0x0ff000f0, 0x016f0f10, 3, CLZ_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // CLZ , cond:4|0|0|0|1|0|1|1|0|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 - {0x0ff0f000, 0x03700000, 4, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // CMN ,# cond:4|0|0|1|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 - {0x0ff00000, 0x03700000, 3, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // CMN ,# cond:4|0|0|1|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 - {0x0ff0f090, 0x01700010, 4, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // CMN ,, cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 - {0x0ff00090, 0x01700010, 3, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // CMN ,, cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 - {0x0ff0f010, 0x01700000, 4, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // CMN ,{,} cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 - {0x0ff00010, 0x01700000, 3, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // CMN ,{,} cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 - {0x0ff0f000, 0x03500000, 4, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // CMP ,# cond:4|0|0|1|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 - {0x0ff00000, 0x03500000, 3, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // CMP ,# cond:4|0|0|1|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 - {0x0ff0f090, 0x01500010, 4, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // CMP ,, cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 - {0x0ff00090, 0x01500010, 3, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // CMP ,, cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 - {0x0ff0f010, 0x01500000, 4, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // CMP ,{,} cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 - {0x0ff00010, 0x01500000, 3, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // CMP ,{,} cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 - {0x0ffffff0, 0x0320f0f0, 4, DBG_EQ, 0x1c04, instArgs{arg_option}}, // DBG #